JPS63188957A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63188957A JPS63188957A JP2200287A JP2200287A JPS63188957A JP S63188957 A JPS63188957 A JP S63188957A JP 2200287 A JP2200287 A JP 2200287A JP 2200287 A JP2200287 A JP 2200287A JP S63188957 A JPS63188957 A JP S63188957A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- electrode
- layer
- layer electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000010354 integration Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 23
- 238000002955 isolation Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特に多層配線を行なう半導体装
置の電極間の接続の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a structure of connection between electrodes of a semiconductor device, particularly a semiconductor device in which multilayer wiring is performed.
本発明は、３１基板やゲート電極と多層配線との接続に
おいて、Ｓｉ基板と１層目のｉＩｉ極とのコンタクト上
に、１層目電極と２層目電極とのコンタクトを形成し、
しかも、１層目電極と２層目電極とのコンタクトの大き
さを、Ｓｉ基板と１８目電極のコンタクトの大きさより
も大きくすることにより、コンタクト上分の占を面積を
小さくし、微細化、高集積化をさせたものである。In the connection between the 31 substrate or the gate electrode and the multilayer wiring, the present invention forms a contact between the first layer electrode and the second layer electrode on the contact between the Si substrate and the first layer iIi electrode,
Moreover, by making the size of the contact between the first layer electrode and the second layer electrode larger than the size of the contact between the Si substrate and the 18th electrode, the area of the contact area can be reduced, and miniaturization can be achieved. It is highly integrated.
従来の、半導体装置の多層配線に於ける電極の接続方法
は、第２図のように、Ｓｉ基板を、７のコンタクトで１
層目の電Ｐｉ６とｔ！！−続し、１層目の電極と２層目
の電極とは分離領域上で８のコンタクトを介して接続さ
れていた。The conventional method for connecting electrodes in multilayer wiring of semiconductor devices is as shown in Figure 2.
Layered electric Pi6 and t! ! - Subsequently, the first layer electrode and the second layer electrode were connected through eight contacts on the separation region.
しかし、前述の従来技術では、第１コンタクトと第２コ
ンタクトを別の局所で形成するため、コンタクト部の占
を面積が大きく成り、微細化、高集積化が出来ないとい
う問題点ををする。そこで本発明はこのような問題点を
解決するもので、その目的とする屑は、コンタクト部の
６仔面積が小さく、微細化、高集積化が可能な半導体装
置を提供する所にある。However, in the above-mentioned prior art, since the first contact and the second contact are formed in different locations, the area of the contact portion becomes large, which poses a problem in that miniaturization and high integration are not possible. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device in which the area of the contact portion is small and which can be miniaturized and highly integrated.
本発明の半導体装置は、Ｓｉ基板と１層目電極とのコン
タクト上に、１層目電極と２層目電極とのコンタクトを
形成し、しかも、１層目電極と２層目電極とのコンタク
トの大きさが、Ｓｉ基板と１層電極とのコンタクトの大
きさよりも大きいことを特徴とする。In the semiconductor device of the present invention, the contact between the first layer electrode and the second layer electrode is formed on the contact between the Si substrate and the first layer electrode, and the contact between the first layer electrode and the second layer electrode is formed. The size of the contact between the Si substrate and the single-layer electrode is larger than that of the contact between the Si substrate and the single-layer electrode.
ｍ１図は本発明の半導体装置の実施例に於ける断面図で
ある。１はＳｉ基板であり、２は分離領域となる酸化膜
であり例えば、熱酸化法により形成する。３はＳｉ基板
と第１層電極とを分離する絶縁膜で有り、例えば酸化膜
を例えば気相成長により形成する。４は第１層電極と第
２層電極とを分離すり絶縁膜であり、３と同じく、例え
ば酸化膜を、例えば気相成長により形成する。６は第１
層電極であり、例えばＡρ−３ｉｓ例えばスパッタ法に
よる形成する。５は第２府電極であり、同じく例えばＡ
ρ−３ｉを、例えばスパッタ法により形成する。７がＳ
ｉ基板と第１府電極とを接続するための第１コンタクト
であり、例えばプラズマが用いたドライエツチング法で
形成する。８が第１層電極と第２届電極とを接続する第
２コンタクトであり、同じく、例えばプラズマを用いた
ドライエツチングなどで形成する。第１図のように第２
コンタクト８は第１コンタクト７上に形成されており、
その大きさは、第１コンタクト部の段差による第２電極
の段線を防ぐために、第２フンタクトのほうが、第１フ
ンタクトよりも大きくなっている。第３図には本発明の
実施例の平面図を示すが、第２図の従来例と比較しても
分かる通り、本発明ではコンタクト部の占有面積が小さ
くできる。Figure m1 is a cross-sectional view of an embodiment of the semiconductor device of the present invention. 1 is a Si substrate, and 2 is an oxide film serving as an isolation region, which is formed by, for example, a thermal oxidation method. Reference numeral 3 denotes an insulating film that separates the Si substrate and the first layer electrode, and is formed of, for example, an oxide film by, for example, vapor phase growth. 4 is an insulating film for separating the first layer electrode and the second layer electrode, and like 3, an oxide film, for example, is formed by, for example, vapor phase growth. 6 is the first
It is a layered electrode, and is formed, for example, by Aρ-3is, for example, by sputtering method. 5 is the second electrode, and similarly, for example, A
ρ-3i is formed by, for example, a sputtering method. 7 is S
This is a first contact for connecting the i-substrate and the first electrode, and is formed by, for example, a dry etching method using plasma. A second contact 8 connects the first layer electrode and the second contact electrode, and is similarly formed by, for example, dry etching using plasma. As shown in Figure 1, the second
Contact 8 is formed on first contact 7,
The size of the second contact portion is larger than that of the first contact portion in order to prevent a dashed line in the second electrode due to the step difference in the first contact portion. FIG. 3 shows a plan view of an embodiment of the present invention, and as can be seen from a comparison with the conventional example shown in FIG. 2, the area occupied by the contact portion can be reduced in the present invention.
第４図は本発明の別の実施例の断面図である。FIG. 4 is a cross-sectional view of another embodiment of the invention.
この実施例ではＳｉ基板ではな（、例えばポリＳｉなど
のゲート電極、及び配線電極に本発明を適用した例であ
り、１０が例えばポリＳｉゲート電極であり、ポリＳｉ
と第１電極６との第１コンタクト７上に第１電極と第２
電極５との第２フンタクト８が形成されており、第１コ
ンタクトよりも第２コンタクトのほうが大きい。This example is an example in which the present invention is applied to a gate electrode made of poly-Si (for example, a poly-Si gate electrode) and a wiring electrode, and 10 is a poly-Si gate electrode.
and the first electrode 6 on the first contact 7 and the first electrode and the second electrode 6.
A second contact 8 with the electrode 5 is formed, and the second contact is larger than the first contact.
以上述べた様に本発明によれば、３１基板、及びポリＳ
ｉなどのゲート電極と１層目の配線との第１コンタクト
上に、１層目と２層目との第２コンタクトを形成し、し
かも第２コンタクトの大きさを第１コ７ククトよりも大
きくすることにより、第２層電極が断線する事なく、コ
ンタクト部の占有面積が小さく成り、高集積化が可能に
成るという効果ををする。As described above, according to the present invention, the 31 substrate and polyS
A second contact between the first layer and the second layer is formed on the first contact between the gate electrode such as i and the first layer wiring, and the size of the second contact is made larger than the first layer. By increasing the size, the second layer electrode will not be disconnected, the area occupied by the contact portion will be reduced, and high integration will be possible.
第１図は、本発明の半導体装置の一実施例を示す主要断
面図。
第２図は従来の半導体装置を示す平面図。
第３図は本発要の半導体装置の一実施例を示す平面図。
第４図は本発明の別の実施例を示す主要断面図。
１・・・Ｓｉ基板
２・・・分離領域の酸化膜
３・・・居間絶縁膜
４・・・居間絶縁膜
５・・・第２層電極
６・・・第１層電極
７・・・第１コンタクト
８・・・第２コンタクト
９・・・素子領域と分離領域との境界
１０ ・・・ ボ リ Ｓｉ
以 上
惧 １ 図
ｇ
箋２日
箋 ３ 図
５！−４凹FIG. 1 is a main sectional view showing an embodiment of a semiconductor device of the present invention. FIG. 2 is a plan view showing a conventional semiconductor device. FIG. 3 is a plan view showing an embodiment of the semiconductor device of the present invention. FIG. 4 is a main sectional view showing another embodiment of the present invention. 1... Si substrate 2... Oxide film in isolation region 3... Living room insulating film 4... Living room insulating film 5... Second layer electrode 6... First layer electrode 7... 1 Contact 8...Second contact 9...Boundary 10 between element region and isolation region...Bori Si 1 Figure G Note 2 Note 3 Figure 5! -4 concave
Claims (1)
置において、Ｓｉ基板、またはゲート電極と第１電極と
の接続を行なう第１コンタクト上に、第１電極と第２電
極との接続を行なう第２コンタクトが形成されており、
前記第２コンタクトの大きさが前記第１コンタクトの大
きさよりも大きいことを特徴とする半導体装置。In a semiconductor device in which wiring is performed using at least two or more layers of electrodes, a second contact that connects the first electrode and the second electrode is placed on the Si substrate or the first contact that connects the gate electrode and the first electrode. is formed,
A semiconductor device characterized in that the size of the second contact is larger than the size of the first contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2200287A JPS63188957A (en) | 1987-02-02 | 1987-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2200287A JPS63188957A (en) | 1987-02-02 | 1987-02-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63188957A true JPS63188957A (en) | 1988-08-04 |
Family
ID=12070799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2200287A Pending JPS63188957A (en) | 1987-02-02 | 1987-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63188957A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267470A (en) * | 1992-03-17 | 1993-10-15 | Fujitsu Ltd | Integrated circuit device and its manufacture |
-
1987
- 1987-02-02 JP JP2200287A patent/JPS63188957A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267470A (en) * | 1992-03-17 | 1993-10-15 | Fujitsu Ltd | Integrated circuit device and its manufacture |
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