JPS631755B2 - - Google Patents
Info
- Publication number
- JPS631755B2 JPS631755B2 JP55093612A JP9361280A JPS631755B2 JP S631755 B2 JPS631755 B2 JP S631755B2 JP 55093612 A JP55093612 A JP 55093612A JP 9361280 A JP9361280 A JP 9361280A JP S631755 B2 JPS631755 B2 JP S631755B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- container
- lid
- opening
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 58
- 238000005192 partition Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 239000003566 sealing material Substances 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 230000005260 alpha ray Effects 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 239000011888 foil Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910000833 kovar Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- 229910052776 Thorium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にその外囲器
（パツケージ）の構造に関するものである。一般
に半導体装置は、たとえばセラミツクあるいはコ
バールなどの支持台上に半導体素子を固着し、そ
の半導体素子を、たとえばセラミツクなどの壁部
材および蓋部材などを用いて気密封入している。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of its envelope (package). Generally, in a semiconductor device, a semiconductor element is fixed on a support base made of ceramic or Kovar, and the semiconductor element is hermetically sealed using a wall member made of ceramic, a lid member, and the like.
この封入されるべき半導体素子が高密度の集積
回路、特にMOSデバイスや電荷転送デバイスな
どで構成される場合、外囲器構成部材特に封止材
からの放射線照射、特にα線照射により半導体素
子に例えば、一般にソフトエラーと称される記憶
情報の破壊等の特性劣化を生ずる恐れがある。 When the semiconductor element to be encapsulated is composed of a high-density integrated circuit, especially a MOS device or a charge transfer device, the semiconductor element may be exposed to radiation from the envelope components, especially the encapsulant, especially α-ray irradiation. For example, there is a possibility that characteristic deterioration such as destruction of stored information, which is generally referred to as a soft error, may occur.
これは、自然界に存在し放射性崩壊する際にα
線を生ずるウラニウム（Ｕ）あるいはトリウム
（Th）等の放射性同位元素が、前記封止材として
の低融点ガラスや鉛と錫等から成るソルダーの中
に含まれていることによる。 This exists in the natural world and when radioactively decays, α
This is because radioactive isotopes such as uranium (U) or thorium (Th) that generate lines are contained in the low-melting glass or solder made of lead and tin as the sealing material.
発生したα線は半導体素子内に侵入すると、正
孔と電子の対を発生し、該正孔あるいは電子のい
ずれかが該半導体素子内の活性領域に注入され
て、例えば前述の如く記憶情報の破壊を招く。従
つて、該半導体素子において活性領域が形成され
ている半導体基板表面領域へのα線の照射、侵入
の防止を図ることが重要であり、前記外囲器にあ
つて、一般に該半導体素子の表面付近に位置する
蓋部材及び封止材から発生するα線の抑制が必要
となる。 When the generated α rays enter the semiconductor element, they generate pairs of holes and electrons, and either the holes or the electrons are injected into the active region within the semiconductor element, and for example, as described above, storage information is generated. Invite destruction. Therefore, it is important to prevent alpha rays from irradiating and penetrating the surface area of the semiconductor substrate where the active region is formed in the semiconductor element. It is necessary to suppress alpha rays generated from the lid member and sealing material located nearby.
蓋部材から発生されるα線は、該蓋部材の内面
すなわち半導体素子に対向する面に例えばシリコ
ン板あるいはポリイミド板等をはり付けることに
よりα線の半導体素子への侵入を阻止することが
できるとされている。しかしながら、かかるシリ
コン板、ポリイミド板等のみでは封止材から発生
されるα線を有効に阻止することができない。一
方、封止材を金―錫（Au―Sn）等の金系鑞材か
ら構成すればα線の発生が極めて少ない。しかし
ながら、金系鑞材の使用は当該半導体装置の高価
格化を招いてしまう。 The alpha rays generated from the lid member can be prevented from entering the semiconductor element by attaching, for example, a silicon plate or a polyimide plate to the inner surface of the lid member, that is, the surface facing the semiconductor element. has been done. However, such silicon plates, polyimide plates, etc. alone cannot effectively block α rays generated from the sealing material. On the other hand, if the sealing material is made of a gold-based solder material such as gold-tin (Au-Sn), the generation of α rays is extremely small. However, the use of gold-based brazing material increases the cost of the semiconductor device.
本発明は前述の点に鑑みなされたもので、その
目的は半導体素子表面への放射線照射、特にα線
照射をより簡単な構造をもつて阻止し、α線照射
による半導体素子の特性劣化を防止することがで
きる構造を有して成る半導体装置を提供すること
にある。 The present invention has been made in view of the above-mentioned points, and its purpose is to prevent radiation irradiation, particularly alpha ray irradiation, to the surface of a semiconductor element with a simpler structure, and prevent characteristic deterioration of the semiconductor element due to alpha ray irradiation. An object of the present invention is to provide a semiconductor device having a structure that allows for
このため本発明によれば、半導体素子と、該半
導体素子を収容する開口が形成された収容容器
と、前記開口内の所定の面に形成され前記半導体
素子及び外部接続端子に電気的に接続された配線
層と、前記半導体素子を前記容器内に気密封止す
る蓋とを備え、前記半導体素子及びワイヤを覆う
平板と、該平板の縁部から前記容器の開口の内壁
面にほぼ平行に延在し、該内壁面と前記半導体素
子の間を仕切る仕切り板と、該仕切り板及び平板
を支持し前記配線層が形成された面上の該配線層
が形成された領域以外の部分に接続された支持脚
とを有する表面がα線遮蔽用の導電体からなる内
蓋を備えてなる半導体装置、及び半導体素子と、
該半導体素子を収容する開口が形成された収容容
器と、前記開口内の所定の面に形成され前記半導
体素子及び外部接続端子に電気的に接続された配
線層と、前記半導体素子を前記容器内に気密封止
する蓋とを備え、前記半導体素子及びワイヤを覆
う平板と、該平板の縁部から前記容器の開口の内
壁面にほぼ平行に延在し、該内壁面と前記半導体
素子の間を仕切る仕切り板を有する表面がα線遮
蔽用の導電体からなる内蓋を備え、該内蓋が前記
気密封止の蓋の裏面に支持固定さてなる半導体装
置が提供される。 Therefore, according to the present invention, there is provided a semiconductor element, a container having an opening for accommodating the semiconductor element, and a container formed on a predetermined surface inside the opening and electrically connected to the semiconductor element and external connection terminals. a flat plate that covers the semiconductor element and wires; and a flat plate extending substantially parallel to an inner wall surface of the opening of the container from an edge of the flat plate. a partition plate that partitions between the inner wall surface and the semiconductor element, and a surface that supports the partition plate and the flat plate and is connected to a portion other than the area where the wiring layer is formed on the surface where the wiring layer is formed. a semiconductor device and a semiconductor element, the semiconductor device comprising an inner lid having support legs whose surface is made of a conductor for shielding alpha rays;
a storage container having an opening for accommodating the semiconductor element; a wiring layer formed on a predetermined surface within the opening and electrically connected to the semiconductor element and external connection terminals; a flat plate that hermetically seals the semiconductor element and the wire; a flat plate that extends from the edge of the flat plate substantially parallel to the inner wall surface of the opening of the container, and that extends between the inner wall surface and the semiconductor element; There is provided a semiconductor device comprising an inner cover whose surface is made of a conductor for shielding alpha rays and has a partition plate for partitioning the inner cover, and the inner cover is supported and fixed to the back surface of the hermetically sealed cover.
次に本発明を実施例をもつて詳細に説明する。 Next, the present invention will be explained in detail using examples.
第１図は本発明による半導体装置の一部破断平
面を示す。また、第２図は第１図のＡ―Ａ断面を
示す。 FIG. 1 shows a partially cutaway plane of a semiconductor device according to the present invention. Further, FIG. 2 shows a cross section taken along the line AA in FIG.
図において、１１は半導体集積回路素子、１２
は該素子１１を金―シリコン（Au―Sl）等の鑞
材１３をもつて固着し収容してなる多層セラミツ
ク製容器、１４は該容器１２に半田等の封止材１
５をもつて固着され容器１２内を気密封止するセ
ラミツク蓋である。また１６は容器１２の外側面
各面に配設された外部接続端子であり、前記素子
１１の電極は金線またはアルミニウム線からなる
リード線１７及び該リード線１７が接続されるモ
リブデンまたはタングステン等を主体とするメタ
ライズ配線層１８を介して外部接続端子１６に接
続される。一般にメタライズ層１８の表面には金
めつき処理が施される。このような半導体集積回
路素子の気密封止構造は周知である。 In the figure, 11 is a semiconductor integrated circuit element, 12
14 is a multilayer ceramic container in which the element 11 is fixed and housed with a solder material 13 such as gold-silicon (Au-Sl), and 14 is a sealing material 1 such as solder in the container 12.
5 is a ceramic lid that is fixed with a cylindrical ring 5 to hermetically seal the inside of the container 12. Reference numeral 16 denotes external connection terminals disposed on each outer surface of the container 12, and the electrodes of the element 11 include a lead wire 17 made of gold wire or aluminum wire and a molybdenum or tungsten wire to which the lead wire 17 is connected. It is connected to the external connection terminal 16 via a metallized wiring layer 18 mainly composed of. Generally, the surface of the metallized layer 18 is subjected to gold plating treatment. Such hermetically sealed structures for semiconductor integrated circuit elements are well known.
本発明によれば、このような半導体装置におい
て、素子１１と蓋１４との間に素子１１表面を覆
う如くα線遮蔽用内蓋１００を配設する。内蓋１
００は表面が金メツキされたコバールまたは銅等
から選択された厚さ300μm〜0.1mm程の金属の板
または箔からプレス法等により形成され、容器１
２内の開口をほぼ覆う面積を有し、四隅に設けら
れた支持脚１０１が容器１２内に設けられた内蓋
固定用パツド１８Ａに固着され、該容器内に収容
される。該内蓋固定用パツド１８Ａは、前記メタ
ライズ配線層１８の製造と同一工程において容器
１２内の四隅にモリブデンまたはタングステン等
を主体するメタライズ層及びその表面に形成され
た金めつき層をもつて構成される。また前記内蓋
１００の支持脚１０１の長さ及び方向は内蓋１０
０がリード線１７に接触することのないよう選択
され、当該支持脚１０１は内壁固定用パツド１８
Ａへ熱圧着あるいはポリイミド系接着剤を用いた
接着により固着される。また内蓋１００は必要に
応じて各辺縁部に容器１２の内壁面１２Ａにほぼ
平行に延在し、該容器１２の内壁面と素子１１と
の間を仕切る仕切り板１０２を有する。第３図に
内蓋１００のみの外観を示す。 According to the present invention, in such a semiconductor device, an α-ray shielding inner lid 100 is disposed between the element 11 and the lid 14 so as to cover the surface of the element 11. Inner lid 1
00 is formed by a pressing method or the like from a metal plate or foil with a thickness of about 300 μm to 0.1 mm selected from Kovar or copper with a gold-plated surface.
Support legs 101 provided at the four corners are fixed to inner lid fixing pads 18A provided within the container 12, and are accommodated within the container. The inner lid fixing pad 18A is formed by having a metallized layer mainly made of molybdenum or tungsten at the four corners of the container 12 and a gold plating layer formed on the surface thereof in the same process as the manufacturing of the metallized wiring layer 18. be done. Further, the length and direction of the support legs 101 of the inner cover 100 are determined by the inner cover 100.
0 does not touch the lead wire 17, and the support leg 101 is selected so that the support leg 101 does not touch the inner wall fixing pad 18.
It is fixed to A by thermocompression bonding or adhesion using polyimide adhesive. Further, the inner lid 100 has a partition plate 102 on each edge portion thereof, if necessary, which extends substantially parallel to the inner wall surface 12A of the container 12 and partitions between the inner wall surface of the container 12 and the element 11. FIG. 3 shows the appearance of only the inner lid 100.
このような本発明による半導体装置にあつては
蓋１４、封止材１５等から発生し素子１１へ向う
α線は内蓋１００によつて阻止され、素子１１表
面へは到達しない。また容器１２内の側壁面１２
Ａから発生するα線も内蓋１００及びその仕切り
板１０２により有効に阻止され素子１１表面へは
到達しない。 In such a semiconductor device according to the present invention, alpha rays generated from the lid 14, the sealing material 15, etc. and directed toward the element 11 are blocked by the inner lid 100 and do not reach the surface of the element 11. Also, the side wall surface 12 inside the container 12
The α rays generated from A are also effectively blocked by the inner lid 100 and its partition plate 102, and do not reach the surface of the element 11.
なお、容器１２の側壁面１２Ａの高さが低いか
あるいは容器を構成する材料のα線放出量が少い
場合には前記仕切り板１０２を省略することがで
きる。 Note that when the height of the side wall surface 12A of the container 12 is low or the amount of alpha rays emitted from the material constituting the container is small, the partition plate 102 can be omitted.
このような本発明による変形例を第４図に示
す。本実施例にあつては内蓋１００の支持脚１０
１が蓋１４の内面に固着され、該内蓋１００は蓋
１４により支持される。このような構造であつて
も素子１１に対するα線の阻止を有効に行なうこ
とができる。 Such a modification according to the present invention is shown in FIG. In this embodiment, the support leg 10 of the inner lid 100
1 is fixed to the inner surface of the lid 14, and the inner lid 100 is supported by the lid 14. Even with such a structure, alpha rays can be effectively blocked from the element 11.
なお、本発明の半導体装置においては封止処理
の際に容器１２内へ収容されている内蓋１００の
上面が封止材１５により濡れることを防止するた
めに内蓋１００の上面が容器１２の封止面（頂
面）の高さよりも0.1〜0.15〔mm〕程低くなるよう
内蓋１００の支持脚１０１の高さを設定する。 In addition, in the semiconductor device of the present invention, in order to prevent the top surface of the inner lid 100 housed in the container 12 from getting wet with the sealing material 15 during the sealing process, the top surface of the inner lid 100 is placed inside the container 12. The height of the support leg 101 of the inner lid 100 is set to be about 0.1 to 0.15 [mm] lower than the height of the sealing surface (top surface).
以上実施例をもつて説明したように、本発明に
よれば、容器内において、半導体素子と蓋、封止
材との間に金属板または金属箔からなる内蓋が配
設される。このため蓋、封止材等から発生する放
射線特にα線はかかる内蓋によつて阻止される。
またかる内蓋は容器の内壁面にほぼ平行に延びる
仕切り板を有し、該容器内壁面及び封止材から発
生するα線の該半導体素子への到達を阻止するこ
とができる。 As described above with reference to the embodiments, according to the present invention, an inner lid made of a metal plate or metal foil is provided between the semiconductor element, the lid, and the sealing material in the container. Therefore, radiation, especially alpha rays, generated from the lid, sealing material, etc. is blocked by the inner lid.
Further, the inner lid has a partition plate extending substantially parallel to the inner wall surface of the container, and can prevent alpha rays generated from the inner wall surface of the container and the sealing material from reaching the semiconductor element.
このような内蓋の配設は当該半導体装置の組立
て工程に工程の増加を来たすが、前述の如く封止
剤として金―錫等からなる鑞材を用いるよりも製
造コストを低下させることができ、より低価格化
が要求される半導体装置の製造においては有利で
ある。 Providing such an inner cover increases the number of steps in the assembly process of the semiconductor device, but as described above, it can reduce manufacturing costs compared to using a solder material made of gold-tin or the like as a sealant. This is advantageous in the manufacture of semiconductor devices, which requires lower costs.
なお、前記実施例にあつては内蓋としてコバー
ル、銅等の金属からなる板または箔を用いる例を
掲げたが、これらの金属板または箔の表面を耐熱
性樹脂、例えばポリイミドにより被覆してリード
線等この接触を防止してもよい。 In the above embodiments, a plate or foil made of metal such as Kovar or copper was used as the inner cover, but the surface of these metal plates or foils may be coated with a heat-resistant resin such as polyimide. This contact may be prevented by a lead wire or the like.
第１図及び第２図は本発明の半導体装置の第１
の実施例を示す一部破断平面図であり、第２図は
第１図Ａ―Ａ断面を示す。第３図は本発明の第１
の実施例に適用される内蓋を示す外観斜視図であ
る。第４図は本発明の半導体装置の他の実施例を
示す断面図である。
図において、１１……半導体集積回路素子、１
２……容器、１４……蓋、１５……封止材、１６
……外部接続端子、１００……内蓋、１０１……
支持脚、１０２……仕切り板。
FIGS. 1 and 2 show a first diagram of a semiconductor device of the present invention.
FIG. 2 is a partially cutaway plan view showing an embodiment of the present invention, and FIG. 2 shows a cross section taken along line AA in FIG. Figure 3 shows the first embodiment of the present invention.
FIG. 2 is an external perspective view showing an inner lid applied to the embodiment. FIG. 4 is a sectional view showing another embodiment of the semiconductor device of the present invention. In the figure, 11...semiconductor integrated circuit element, 1
2... Container, 14... Lid, 15... Sealing material, 16
...External connection terminal, 100...Inner cover, 101...
Support leg, 102...partition plate.
Claims (1)
が形成された収容容器と、前記開口内の所定の面
に形成され前記半導体素子にワイヤを介して接続
された配線層と、前記半導体素子を前記容器内に
気密封止する蓋とを備えた半導体装置において、 前記半導体素子及び前記ワイヤを覆う平板と、
該平板の縁部から前記容器の開口の内壁面にほぼ
平行に延在し、該内壁面と前記半導体素子の間を
仕切る仕切り板と、該仕切り板及び平板を支持し
前記配線層が形成された面上の該配線層が形成さ
れた領域以外の部分に接続された支持脚とを有す
る表面がα線遮蔽用の導電体からなる内蓋を備え
てなることを特徴とする半導体装置。 ２ 半導体素子と、該半導体素子を収容する開口
が形成された収容容器と、前記開口内の所定の面
に形成され前記半導体素子及び外部接続端子に電
気的に接続された配線層と、前記半導体素子を前
記容器内に気密封止する蓋とを備えた半導体装置
において、 前記半導体素子及びワイヤを覆う平板と、該平
板の縁部から前記容器の開口の内壁面にほぼ平行
に延在し、該内壁面と前記半導体素子の間を仕切
る仕切り板を有する表面がα線遮蔽用の導電体か
らなる内蓋を備え、 該内蓋が前記気密封止の蓋の裏面に支持固定さ
てなることを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor element, a housing container having an opening for accommodating the semiconductor element, and a wiring layer formed on a predetermined surface inside the opening and connected to the semiconductor element via a wire. , a semiconductor device comprising: a lid for hermetically sealing the semiconductor element in the container; a flat plate covering the semiconductor element and the wire;
A partition plate extending from an edge of the flat plate substantially parallel to an inner wall surface of the opening of the container and partitioning between the inner wall surface and the semiconductor element, and supporting the partition plate and the flat plate and forming the wiring layer. 1. A semiconductor device comprising: an inner lid made of a conductor for shielding alpha rays; 2. A semiconductor element, a housing container having an opening for accommodating the semiconductor element, a wiring layer formed on a predetermined surface inside the opening and electrically connected to the semiconductor element and external connection terminals, and the semiconductor element. A semiconductor device including a lid for hermetically sealing an element in the container, comprising: a flat plate covering the semiconductor element and wire; and a lid extending from an edge of the flat plate substantially parallel to an inner wall surface of the opening of the container, The surface having a partition plate that partitions between the inner wall surface and the semiconductor element is provided with an inner cover made of a conductor for shielding alpha rays, and the inner cover is supported and fixed to the back surface of the hermetically sealed cover. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9361280A JPS5718339A (en) | 1980-07-09 | 1980-07-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9361280A JPS5718339A (en) | 1980-07-09 | 1980-07-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5718339A JPS5718339A (en) | 1982-01-30 |
| JPS631755B2 true JPS631755B2 (en) | 1988-01-13 |
Family
ID=14087144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9361280A Granted JPS5718339A (en) | 1980-07-09 | 1980-07-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5718339A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59227722A (en) * | 1983-05-09 | 1984-12-21 | Mitsubishi Metal Corp | Lead oxide for low-melting glass for sealing semiconductor device and its preparation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588356A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Ltd | Semiconductor device |
-
1980
- 1980-07-09 JP JP9361280A patent/JPS5718339A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588356A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5718339A (en) | 1982-01-30 |
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