JPS63144284A - Pulse period measuring circuit - Google Patents

Abstract

PURPOSE:To output an error signal when a ring counter makes one round and accurate measurement can not be taken by latching the output of a 2nd counter with the output of a synchronizing means which synchronizes a pulse signal with a clock. CONSTITUTION:The clock is inputted to a 1st counter 2 and a 2nd counter which have stages as many as the counter 2 and latches its carry output. A latch means 11 latches the latched carry output of the counter 10 and the output of the counter 2. The synchronizing means 4 inputs a pulse signal whose period is to be measured and synchronizes the pulse signal with the clock. The output of the counter 2 and the latched carry output of the counter 10 are latched by the latch means 11 with the output of the synchronizing means 4 and the counter 10 is cleared. Consequently, even if the counter 2 overflows, an error signal indicating the overflow is latched by the latch means 11, so there is no error in measurement even if an input pulse signal having a longer period than expected is inputted and the counter 2 overflows.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement in a pulse frequency Ill measurement path for measuring the period of an input pulse signal.

<Prior Art> The period of an input pulse signal is measured by counting clocks whose period is sufficiently shorter than the period of the input pulse signal during the period of the input pulse signal. Such a pulse period measuring circuit is shown in FIG. In FIG. 4, reference numeral 1 denotes a clock generating means, which generates a clock at a constant point II. This clock is input to the ring counter 2 and counted. The count value of the ring counter 2 is input to the latch means 3. Reference numeral 4 denotes a synchronizing means, into which an input pulse signal for measuring the period is input, and synchronizes the signal with the clock of the clock generating means 1. The synchronization means 4 consist of two D-type flip-flops 41, 42. An input clock signal is input to the clock terminal of the flip-flop 41, its inverted output Q is connected to the data terminal, and its non-inverted output Q is connected to the data terminal of the flip-flop 42. The clock of the clock generating means 1 is inputted to the clock terminal of the flip-flop 42, and its inverted output Q is connected to the reset terminal of the flip-flop 41 and outputted to the outside. The count output of the ring counter 2 is latched into the latch means 3 by the output of the synchronization means. The number of stages of the ring counter 2 is set so that the counter does not complete one cycle even for a sufficiently long period of the input pulse signal.

In such a configuration, the period of the input pulse signal can be measured by reading the side latched by the latch means 3 using an external circuit (not shown) and taking the difference from the value latched immediately before. I can do it.

<Problems to be Solved by the Invention> However, such a pulse period measuring circuit has the following problems. After the ring counter 2 completes one cycle, the ring counter 2 returns to the beginning and repeats the same operation. Therefore, when an input pulse signal with a cycle longer than expected is input, the ring counter 2 completes one cycle, making it impossible to accurately measure the cycle.

<Object of the Invention> An object of the present invention is to provide a pulse frequency rrns constant circuit that outputs an error signal when the ring counter completes one cycle and cannot measure an accurate period.

Means for Solving the Problems> In order to solve the above problems, the present invention provides a first counter to which a clock is input, a first counter to which the clock is input,
a second counter that has the same number of stages as the first counter and whose carry is latched; a latch means that latches the carry output latched by the second counter and the output of the first counter; an input pulse signal, the period of which is measured, is input and synchronizing means synchronizes with the clock, and the output of the synchronizing means causes the output of the first counter and the latched clock of the second counter to be input. The carry output is latched by the latch means and the second counter is cleared.

Embodiment> FIG. 1 shows an embodiment of the pulse period measurement rgJ path according to the present invention. Note that the same elements as in FIG. 4 are given the same reference numerals, and their explanations will be omitted. In FIG. 1, 2 is a ring counter, for example, National Semiconductor's 4bi counter.
A 74HC161 t counter is used. 10 is a counter that has the same number of stages as ring counter 2 and whose carry is latched; for example, 74 of a 4-bit counter.
1-I Consists of C161 and a latch that latches its carry. 11 is a latch means, and a ring counter 2
The number of stages is one more than the number of stages. This latch means 11
is the count output of ring counter 2 and the count output of counter 1.
A latched carry of zero is input. counter 70
The output of the equalization means 4 is inputted to the clear terminal CLR of.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG. Note that this time chart shows a case where 2-bit counters are used as the ring counter 2 and the counter 10. In FIG. 2, (A> is the output clock of the clock generation means 1, and (B) is the count output of the ring counter 2. The number in (B) represents the output value. The ring counter 2 starts counting up by this clock. (C) is an input pulse signal, which is synchronized with the rising edge of the clock (A) by the synchronization means 4 @(D)
is converted to (E) is the carry signal of counter 10,
(F) is the count output.

The outputs of the counter 10, ie, outputs (E) and (F), are cleared by the output (D). Further, the count output (B) of the ring counter 2 and the latched carry signal (E) of the counter 10 are latched by the latch means 11 at the timing of the fall of the output (D). The value latched in the latch means 11 is read out at an appropriate timing by an external means (not shown), and the period of the input pulse signal is measured from the difference. In such an operation, times ■, ■, ■, ■ are the timings at which the output of the synchronizing means 4 falls. Since the counter 10 does not overflow between times ■ and ■ and between times ■ and ■, a key (E) does not occur. The time between time ■ and ■ is long, and carry (E) rises at time ■. This carry signal @(E) is held as it is, and is latched as an error signal by the latch means 11 at time ①, that is, at the falling and falling timings of (D), and the counter 10 is cleared. (G) is the latch means 11
shows the error signal latched in. If this error signal is present, it is determined that the period of the input pulse signal cannot be accurately measured.

FIG. 3 shows an embodiment in which there are two input pulse signals. Note that the same elements as in the embodiment in FIG. 1 are given the same reference numerals.
The explanation will be omitted. This embodiment includes synchronization means 4, counter 10. Two lines of latch means 11 are installed, and an input pulse signal is input to each of them. That is, the input pulse signal @1 is input to the synchronization means 4, and the output of the synchronization means 4 latches the output of the ring counter 2 and the latched carry of the counter 10 to the latch means 11, and also clears the counter 10. do. Input pulse signal 2 is synchronized by synchronization means 1
2, and the output of the synchronizing means 12 latches the output of the ring counter 2 and the latched carry signal of the counter 13, and also clears the counter 13.

The synchronizing means 4 and 12, the counters 10 and 13, and the latching means 11 and 14 are respectively the same. In this way, the clock generating means 1 and the ring counter 2 can be used in common, so that the configuration becomes simple. Note that even when there are three or more input pulse signals, it is sufficient to provide as many series of synchronizing means, counters, and latch means as there are input pulse signals.

<Effects of the Invention TA> As described above in detail based on the embodiments, in this invention, the output clock of the clock generation means is generated by the first counter, which has the same number of stages as the first counter, and whose carry is latched. a second counter that receives an input pulse signal and synchronizes the pulse signal with the clock, and a latch means, and the output of the synchronization means causes the first counter and the first counter to The output of the second counter is latched in the latch means and the second counter is cleared. Therefore, even if the first counter overflows, an error signal indicating that it has overflowed is latched in the latch means, so if another input pulse signal with a period longer than the expected period is input, the first counter will overflow. This also has the effect of preventing incorrect measurements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the pulse period measuring circuit according to the present invention, FIG. 2 is a time chart for explaining the operation, FIG. 3 is a block diagram showing another embodiment, and FIG. 4 1 is a configuration diagram showing the configuration of a conventional pulse period measuring circuit. 1... Clock generation means, 2... Ring counter,
3.11.14... Latch means, 4... Synchronization means, 10.13... Counter. Atsushi 2 ■ ■ ■ ■■

Claims (1)

[Claims] a first counter to which a clock is input; a second counter to which the clock is input, has the same number of stages as the first counter and has its carry output latched; and a latched carry output of the second counter. Carry output and the first
latching means for latching the output of the counter, and synchronizing means for receiving a pulse signal whose period is measured and synchronizing the pulse signal with the clock, and the output of the synchronizing means for latching the output of the first counter. A pulse period measuring circuit characterized in that the output of the counter and the latched carry output of the second counter are latched in the latch means, and the second counter is cleared.