JP2021526226A - High-precision time measurement method based on FPGA - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-precision time measurement method based on FPGA, which obtains the number S1 of carry chains through which a Start signal has passed by adding the output values of all carry chains of the Start signal. , The time T1 = S1 * τ is calculated based on S1, and the output values of all the carry chains of the Stop signal are added to obtain the number S2 of the carry chains through which the Stop signal has passed. It includes calculating the time T2 = S2 * τ based on the time T2 and outputting the measurement result T = T1 + nTp + (Tp−T2) based on the time T1 and the time T2. Therefore, by adding the output values of all the carry chains, even if a factor of instability occurs in signal transmission and 1 and 0 appear alternately, 1 is added to the result of the addition. Since the carry chain in which is displayed is calculated, the position of the carry chain through which the calculated signal has passed is closer to the position of the carry chain in which the calculated signal has actually passed, which can improve the time accuracy of the measurement. [Selection diagram] Fig. 4

Description

The present application relates to the field of clock measurement, and specifically to a high-precision time measurement method based on FPGA.

In a communication system, both communications employ a synchronous signal transmission scheme to achieve both synchronizations, and both communications achieve signal synchronization with the synchronization signal as a time reference. Specifically, the transmitting side periodically transmits the signal light according to the synchronization signal, and the receiving side measures the time difference between the signal light and the synchronization light after receiving the signal light, thereby performing both. Achieve signal synchronization.

The time measurement accuracy between signal lights is required to reach a level of several tens of picoseconds. Therefore, as one of the currently used measurement methods, there is a method of realizing time measurement by using a carry chain inside the FPGA, further linking it with a clock count, and combining a coarse delay and a slight delay. Specifically, the coarse delay can be roughly measured by the clock counting method, and the obtained time is _{the product of the number n of clocks and a single clock period T p} , that is, nT _p . Yes, the slight delay is used to introduce the carry chain inside the FPGA into the time measurement and mainly to solve the measurement of the fine time interval between the rising edge of the clock and the rising edge of the input signal, FIG. As shown in, the fine time interval of the Start signal is T ₁ , and the fine time interval of the Stop signal is T _2. Therefore, _{after measuring T 1} and T _2, it is linked to the time measured by the coarse delay. This makes it possible to complete the measurement at fine time intervals.

Here, _{the measurement principle of T 1} and T ₂ hours is shown in FIG. Specifically, the Start and Stop signals enter a series of delay units consisting of carry chains, each carry chain having one output terminal connected to a D-type flip-flop, and a D-type flip-flop. The clock is uniformly connected to the operating clock of the system. The main principle of measurement is to use the carry chain to record the time difference between the input signal and the system clock, that is, the amount of slight delay, and every time the rising edge of the internal clock arrives, all the carry chain signals are D. The number of carry chains latched by the type flip-flop and through which the Start signal passes until the clock arrives represents the time difference between the signal under test and the rising edge of the clock signal, and the stepping of two adjacent carry chains is τ. Is to be. According to this method, the relative times of the Start and Stop signals with respect to the internal clock rising edge of the system, that is, T ₁ = 6 * τ and T ₂ = 9 * τ shown in FIG. 2, are recorded, respectively. The number of complete cycles to and from the Stop signal is recorded, and thus the combination of coarse and slight delays can provide fine time measurement results.

However, research has shown that the output carry chain can be misaligned when the Start or Stop signals are unstable. Taking the Start signal as an example, as shown in FIG. 3, there are a plurality of methods for identifying the position where the Start signal arrives in the carry chain, but the most common method is to identify the position corresponding to the first output value 0. be. For example, if the Start signal becomes unstable and the first 0 value appears in the 7th carry chain, the D-type flip-flop latches at the position of the 6th carry chain, and the carry chain through which the Start signal passes. It will be recorded as the position of, and T ₁ = 6 * τ will be output, but the actual position is on the 8th carry chain of the Start signal, and T ₁ = 8 * τ should actually be output. .. Therefore, due to the factor of instability during signal transmission, 1 and 0 may appear alternately, resulting in an error in position identification, and the measured carry chain position is actually passed by the Start signal. It does not match the position of the carry chain, and the error of the measured time becomes large.

The present application provides a high-precision time measurement method based on FPGA in order to solve the problem that the time error measured by the conventional time measurement method is large.

The high-precision time measurement method based on FPGA is
By adding the output values of all the carry chain of the Start signal, and obtaining the number S ₁ of the carry chain of Start signal has passed,
And calculating the time _{T 1} = _S 1 * _τ based on S _1,
By adding the output values of all the carry chain of the Stop signal, and obtaining the number S ₂ carry chains Stop signal has passed,
To calculate the time T ₂ = S ₂ * τ based on S _2,
It includes outputting the measurement result T = T ₁ + nT _p + (T _p −T ₂ ) based on the time T ₁ and the time T _2.

Preferably, the addition is completed by an adder inside the FPGA.

Preferably, the addition method uses the addition tree summing method to perform the calculation.

Preferably, it includes a step of performing an OR operation on the Start signal and the Stop signal to merge into one composite signal before performing the addition, and a step of pointing out the pulse property of the composite signal using the flag signal. Further includes signal preprocessing.

Preferably, the flag signal 1 labels the Start signal in the composite signal and the flag signal 2 labels the Stop signal in the composite signal.
Identifying the rising edge of the composite signal
Includes identifying Start or Stop signals based on rising edges and flag signals.
The flag signal 1 is for labeling the Start signal in the composite signal.
The flag signal 2 is for labeling the Stop signal in the composite signal.

Preferably, when a plurality of Stop signals are continuously input, the time between each Stop signal and the Start signal is measured, and the measurement result is output.

Preferably, it is possible to measure the time between each Stop signal and the Start signal and output the measurement result.
When the first Stop signal is input, the time T ₂ of the first Stop signal is measured, the number n _{1 of T p} between the Start signal and the first Stop signal is recorded, and 1 To output the second time measurement result and
When the second Stop signal is input, the time T ₂ of the second Stop signal is measured, the number n _{2 of T p} between the Start signal and the second Stop signal is recorded, and 2 To output the second time measurement result and
In this way, including continuing until the Nth Stop signal is input and the Nth measurement result is output.
Here, N is a positive integer, the number of recorded T _ps is not cleared, and the time measurement result between each Stop signal and Start signal is output.

As can be seen from the above aspects, the FPGA-based high-precision time measurement method provided in the present application adds the output values of all the carry chains of the Start signal to the number S of carry chains through which the Start signal has passed. and to obtain a _1, and calculating the time T _{1 =} S 1 _* tau based on S _1, by adding the output values of all the carry chain of the Stop signal, the number of carry chains Stop signal has passed and obtaining the S _2, and calculating the time _{T 2} = _S 2 * _τ based on _{S 2,} on the basis of the time _{T 1} and time _{T 2,} outputs the measurement result _{T = T 1 + nT p -T} 2 Including to do. Therefore, by adding the output values of all the carry chains, even if a factor of instability occurs in the signal transmission and 1s and 0s appear alternately, the carry chain in which 1 appears in the result of the addition. Is calculated, the position of the carry chain through which the calculated signal has passed is closer to the position of the carry chain through which the calculated signal has actually passed, which can improve the time accuracy of the measurement.

In order to more clearly explain the technical solutions of the present application, the drawings that need to be used in the examples will be briefly described below, and of course, those skilled in the art will not make any creative effort. Other drawings can be obtained based on the drawings of.
It is a figure which shows the principle of the conventional time measurement. It is a figure which shows the principle of the conventional fine time interval measurement. It is a figure which shows the principle of the error cause of the conventional fine time interval measurement. It is a figure which shows the principle of the fine time interval measurement of this application. It is a figure which shows the principle of the signal preprocessing of this application. It is a figure which shows the flow of the measurement of this application.

In order to make the above objectives, features and advantages of the present application clearer and easier to understand, the present application will be described in more detail below together with the drawings and specific embodiments.

The embodiments of the present application provide a high-precision time measurement method based on FPGA, the principle of the time measurement is referred to in FIG. 4, which method is performed by adding the output values of all carry chains of the Start signal. , Obtaining _{the number S 1 of} carry chains through which the Start signal has passed, calculating the time T ₁ = S _{1 * τ based on S 1} , and adding the output values of all the carry chains of the Stop signal. _{As a result, the number S 2 of} carry chains through which the Stop signal has passed is obtained, the time T ₂ = S ₂ * τ is calculated _{based on S 2} , and the measurement result is based on the _{time T 1} and the time T _2. It includes outputting T = T ₁ + nT _p + (T _p −T _2).

As can be seen from the background technology, the conventional method directly records the number of carry chains that the signal has passed through, and this method can accurately measure the time only when the signal is stable, and the signal When a factor of instability occurs in transmission, 1s and 0s may appear alternately in the carry chain, and when the first 0 appears, it is judged that the rising edge of the signal has already reached, but the signal is actually The result of the measurement will be inaccurate because it may not match the position of the carry chain that passed through and the rising edge of the actual signal may appear at the position of 1 just before the arrival of the non-first 0. It ends up. Therefore, in the present application, by adding the output values of all the carry chains, even if a factor of instability occurs in the signal transmission and 1 and 0 appear alternately, 1 appears in the result of the addition. Since the carry chain has been calculated, the position of the carry chain through which the signal provided in this way has passed is closer to the position of the carry chain through which the calculated signal has passed. position is closer to the actual located carry chain through, i.e., time T ₁ and time T ₂ are so consistent with actual time, it is possible to increase the time accuracy of the measurement.

Further, in the method of the present application, since addition is performed to the output values of all the carry chains, the number of carry chains through which the signal passes, which is calculated when the signal is stable, is the carry chain through which the signal actually passes. Is the same as the number of. Therefore, the method of the present application can provide high-precision time measurement regardless of whether the signal is stable or unstable.

In a preferred embodiment of the method of the present application, the addition of the present application is completed by an adder inside the FPGA, so that the method can effectively utilize internal resources, and the processing method is simple and efficient. Also, the adder inside the FPGA provides the basis for the realization of subsequent algorithms by being able to operate at clocks of 400M and above. Of course, the method of the present application can also perform addition using an adder of an external resource.

Specifically, the addition method performs an calculation using the addition tree totaling method. The principle of the addition tree operation is shown in FIG. 4. The so-called addition tree (adder tree) is the addition of two adjacent numerical values to the numerical value output to the first layer, and each numerical value is only once. It is calculated, and after the calculation, the added data is transmitted to the second layer, and the numerical value output to the second layer also adds two adjacent numerical values, and each numerical value is calculated only once. After the calculation, the added data is transmitted to the third layer, and similarly, the addition is performed until only two numerical values are finally added and one total value is output. Therefore, when the calculation is performed by adopting the addition tree method, not only the addition is simple and clear, but also the position where the unstable state appears in the signal is determined based on the calculation result of the first layer. Can be done.

In a preferred embodiment of the method of the present application, as shown in FIG. 5, a step of performing an OR operation of a Start signal and a Stop signal to merge into one composite signal and a flag signal are used before the addition is performed. Further includes preprocessing of the signal, including the step of pointing out the pulse nature of the synthesized signal.

The processing of Start and Stop signals is a very important step in the design process of the system, which is related to the result of the measurement system, and if the processing is improper, the time information of the signal will be lost and the direct measurement accuracy will be lost. Will be reduced and the measurement will fail directly. The most common idea is to measure the Start signal and Stop signal, respectively, obtain time T ₁ and time T ₂ , respectively, and then perform comprehensive processing. The advantage of this method is that the idea is Although it is clear, the drawbacks are also obvious. The Start signal and Stop signal are processed using two processing units, respectively, and such a processing method causes a fixed system error between the two signals. Exists, and the routing delays do not match due to the difference in the configuration inside the FPGA, which increases the system error.

The OR operation of the two signals is performed inside the FPGA to merge them into one composite signal, and the arrival of the Start signal and the Stop signal is indicated, respectively. The flag signal 1 indicates that the pulse is a Start signal. The flag signal 2 represents that the pulse is a Stop signal, the flag signal is used only to point out the nature of the pulse of the combined signal that arrives at the same time, and the flag signal is used directly for the measurement. Instead, only the composite signal is used directly for subsequent measurements.

It should be noted during processing that an OR gate is used to merge the Start and Stop signals into one OR signal, and this OR gate must be located closest to the input Start and Stop signals. Since both the Start and Stop signals are input from an external pin, the position of this OR gate is particularly important and needs to be sufficiently close to the pin. Each of the Start and Stop signals provides one branch connected to one D-type flipflop, and it is necessary to sample the Start and Stop signals using a clock, and the Start and Stop signals are the clock and the Stop signal. It is a signal to be synchronized, its width is a period of an integral multiple of the clock, and in the subsequent function, the role of determining whether the pulse in the OR signal corresponds to the Start signal or the Stop signal is explained. Fulfill.

The total delay time of the Start signal or Stop signal is greater than the time _{T p} of a single clock cycle. In other words, the width of the high level of the input signal Start and Stop signals must be greater than the width of one sampling period, otherwise there may be situations where the Start and Stop signals cannot be identified, followed by The module will not work.

The pulse of the combined signal and the pulse of the flag signal representing the nature of the pulse arrive at the same time. Reaching at the same time can clearly and accurately indicate whether the pulse of the combined signal is a Start signal or a Stop signal. Further, the input signals Start and Stop have at least one or more period intervals because the input signals must not be overlapped in time and the input signals cannot be distinguished if there is overlap in time.

In the above technical proposal, the method of the present application can avoid the difference due to the measurement of the Start and Stop signals using the two carry chains by using the same carry chain resource. It is possible to improve the accuracy of time measurement and avoid the influence on the measurement accuracy and the result due to changes in external conditions such as temperature changes.

In a preferred embodiment of the method of the present application, the carry chains are continuous and the delay between the carry chains is uniform. The carry chain structure is a core member of the entire time measurement module, and the carry chain structure directly determines the accuracy of the time measurement. An example of the chip used in the present application is as follows. The maximum length of a continuous carry chain inside one logic block of this chip is 50, the time delay of a single carry chain is about 53 ps, and the total delay is about 2650 ps, so that the clock signal. At the time of selection, it is necessary to consider that the clock period must be smaller than the delay value, so the clock frequency is defined as 400M and the corresponding clock period is defined as 2500ps. The result is that, according to actual tests, the chip can withstand an operating frequency of 400M. Of course, the length of the carry chain and the delay time of a single carry chain are determined by the chip selected, and at the time of clock signal selection, an appropriate value is set according to the above description according to the parameters of the chip. You can select it.

The D-type flip-flop structure is immediately after the carry chain, and of course, the flip-flop may select other devices, has two stable states "0" and "1", and has a constant outside world. It suffices if the action of the signal can invert from one stable state to another stable state. Its function is to latch the tap signal of the carry chain and acquire its output state when the clock signal arrives, the input signal arrives earlier than the clock signal, and the input signal begins to be transmitted in the carry chain. , The level is high at the position where the input signal is reached, low at the position where it is not reached, latches 50 D-type flipflop signals when the clock signal arrives, and the number of high-level taps among them, That is, by calculating the time advance amount of the input signal with respect to the clock rising edge, the function of fine time measurement is realized, and the accuracy of the measurement is the time delay amount of a single carry chain, which is about 53 ps.

Positional constraints are an important part of the carry chain structure, ensuring continuity of the carry chains, ensuring that the carry chains are not distributed and distributed, and ensuring uniform delay between the carry chains. This is one of the important points for guaranteeing the measurement accuracy, and further, it is necessary to secure the positional relationship between the subsequent D-type flip-flop and the carry chain, and the D-type flip-flop is separated from the carry chain. The D-type flip-flops should be immediately adjacent to the carry chain and in the same logic block so that distance uncertainty avoids excessive delays affecting final measurement accuracy. preferable.

In a preferred embodiment of the method of the present application, the flag signal 1 labeling the Start signal in the composite signal and the flag signal 2 labeling the Stop signal in the composite signal identifies the rising edge of the composite signal and the rising edge and the flag. It comprises identifying a Start signal or a Stop signal based on the signal, where the flag signal 1 is for labeling the Start signal in the composite signal and the flag signal 2 is for labeling the Start signal in the composite signal. It is a sign. That is, when the rising edge of the Start signal or Stop signal arrives, the flip-flop inverts from one stable state to another, identifies the rising edge of the signal, and then aligns with the flag signal after the rising edge is identified. To identify the Start signal and the Stop signal.

Identification of the Start signal and the Stop signal is one of the important processes of time measurement, and in the present technical proposal, the Start and Stop signals are merged into one signal, and the flag signal 1 and the flag signal 2 are provided. This flag signal is used only to distinguish between the Start and Stop signals and does not participate in the subsequent time measurement function. When the Start signal arrives, the time scale is reset, and when the Stop signal arrives, the time measurement result corresponding to the Start signal is provided. How to distinguish the rising edge of the Start signal and the Stop signal from the composite signal is one of the important processes in the time measurement process, and when the addition method is adopted, the pipeline operation of the adder is performed. Therefore, each clock can provide one addition result, identify that the addition result jumps from 0 to non-zero, and identify the rising edge of the signal, and after the rising edge is recognized, the flag signal. In combination with, the Start signal and the Stop signal can be identified.

In a preferred embodiment of the method of the present application, when a plurality of Stop signals are continuously input, the time between each Stop signal and the Start signal is measured, and the measurement result is output.

Continuous measurement is one of the important functions in the time measurement system, and after identifying the Start signal and Stop signal by using the above method, the time measurement result is provided and the continuous time measurement process is realized. to obtain a T ₁ times after a single Start signal is identified, continuously records the number N of clock periods in this period, when the Stop signal is input, recording the T ₂ values, corresponding The measurement result is obtained, but the number N of the clock period is not cleared so that the measurement result value is re-output when the next Stop value arrives. By adopting such a method, a continuous measurement function can be realized.

Specifically, measuring the time between each Stop signal and the Start signal and outputting the measurement result means that when the first Stop signal is input, the time T of the first Stop signal is T. ₂ was measured and recorded the number _{n 1} of _{T p} between the Start signal and the first Stop signal, and outputting a first time measurement, the second Stop signal is input Then, the time T ₂ of the second Stop signal is measured, the number n _{2 of T p} between the Start signal and the second Stop signal is recorded, and the second time measurement result is output. Including that, and thus continuing from the input of the Nth Stop signal to the output of the Nth measurement result, where N is a positive integer and the recorded T _p. None of the numbers are cleared, and the time measurement result between each Stop signal and Start signal is output.

Summarizing the above, the flow of the optimum embodiment of the present application is shown in FIG. 6, which mainly realizes the function of measuring the time difference between the Start signal and the Stop signal, and the accuracy is several tens of picoseconds. Reaching the order, it mainly uses the carry chain inside the FPGA, and realizes the function of high-precision time measurement by using the delay between the carry chains. The measurement process mainly includes steps such as input signal preprocessing, carry chain measurement, addition tree processing, pulse recognition, data processing, continuous measurement, and measurement result output.

Regarding the measurement result output, the present application states that the time delay of a single carry chain is about 53 ps and the clock period is 2500 ps as an example, a count unit is designed in the program, and the Start signal is identified. , The current addition result S ₁ is recorded and set to T ₁ hour, and before the Stop signal arrives, the clock cycle is counted and marked as N to set the total cycle time to T _{0. When} the Stop signal is identified, the current addition is performed. The result S ₂ is recorded and set to T ₂ hours, and the measurement result is calculated based on the following formula.
T = T ₁ + nT _p + (T _p −T ₂ ) = S ₁ × 53 ps + N × 2500 ps + (2500 _{ps − S 2} × 53 ps)
Here, 53 ps is the average time scale of a single carry chain.

As described above, the high-precision time measurement method based on the FPGA of the present application includes steps such as signal preprocessing, carry chain measurement, addition tree processing, and pulse recognition, all of which can improve the accuracy of the measurement time. Therefore, it is possible to solve the problem that the time error measured by the conventional time measuring method is large.

The present application has been described in detail with reference to specific embodiments and exemplary examples, but these descriptions are not limited to the present application. Those skilled in the art can make various uniform substitutions, modifications or improvements to the technical solutions and embodiments of the present application without departing from the spirit and scope of the present application, all of which are described in the present application. Is included in the range of. The scope of protection of the present application is based on the appended claims.

Coarse delay time nT by clock counting method _p And the slight delay time T of the Start signal using the carry chain inside the FPGA. ₁ And the slight delay time T of the Stop signal ₂ And the coarse delay time nT _p And slight delay time T ₁ And the slight delay time of the Stop signal T ₂ In a high-precision time measurement method based on FPGA, which includes outputting the time T between the Stop signal and the Start signal as a measurement result based on the above.
It is determined whether or not there is an unstable state in the transmission of the Start signal or Stop signal in which 1s and 0s as output values of the carry chain appear alternately.
When it is determined that there is no unstable state, the slight delay time T of the Start signal or Stop signal is based on the position of the output value 1 immediately before the position where the first output value 0 appears in each carry chain. ₁ , T ₂ Measure and
When it is determined that there is an unstable state, the position where the instability occurs is determined by adding the output values of each carry chain and calculating each output value only once, and this unstable state occurs. Slight delay time T of Start signal and Stop signal with reference to position ₁ , T ₂ To measure.

As can be seen from the above aspects, the high-precision time measurement method based on the FPGA provided in the present application measures the coarse delay time nT _p by the clock counting method and starts using the carry chain inside the FPGA. As a measurement result, based on the measurement of the minute delay time T ₁ of the signal and the minute delay time T ₂ of the Stop signal, and the coarse delay time nT _p , the slight delay time T _1, and the minute delay time T _{2 of the Stop signal.} Including the output of the time T between the Stop signal and the Start signal, there is an unstable state in which 1 and 0 as the output value of the carry chain appear alternately in the transmission of the Start signal and the Start signal. If it is determined that there is no unstable state, the start signal or Stop signal is fine with reference to the position of the output value 1 immediately before the position where the first output value 0 appears in each carry chain. If the delay times T ₁ and T ₂ are measured and it is determined that there is an unstable state, the instability is caused by adding the output values of each carry chain and calculating each output value only once. The position where the occurrence occurs is determined, and the minute delay times T ₁ and T ₂ of the Start signal and the Stop signal are measured with reference to the position where the instability occurs. Therefore, by adding the output values of all the carry chains, even if a factor of instability occurs in the signal transmission and 1s and 0s appear alternately, the carry chain in which 1 appears in the result of the addition. Is calculated, the position of the carry chain through which the calculated signal has passed is closer to the position of the carry chain through which the calculated signal has actually passed, which can improve the time accuracy of the measurement.

An embodiment of the present application provides a high-precision time measurement method based on FPGA, and the principle of the time measurement is referred to in FIG. 4, in which the method measures the coarse delay time nT _{p by a clock counting method.} , slight delay of the fact and the coarse delay time nT _p and fine delay time _{T 1} and the Stop signal using the FPGA internal carry chain to measure the fine delay time _{T 2} of the fine delay time _{T 1} and Stop signal Start signal Including the output of the time T between the Stop signal and the Start signal as a measurement result based on the time T _{2, and 1 as the output value of the carry chain in the transmission of the Start signal and the Stop signal.} It is determined whether there is an unstable state in which 0s appear alternately, and if it is determined that there is no unstable state, the output value 1 immediately before the position where the first output value 0 appears in each carry chain is determined. _{The slight delay times T 1} and T ₂ of the Start signal and Stop signal are measured with reference to the position, and if it is determined that there is the unstable state, the output values of each carry chain are added together and each output value is calculated. The position where the instability occurs is determined by performing the calculation only once, and the slight delay times T ₁ and T ₂ of the Start signal and the Stop signal are measured with reference to the position where the instability occurs.

The total delay time of the Start signal or Stop signal is greater than the time _{T p} of a single clock cycle. In other words, the width of the high level of the Start signal or Stop signal as an input signal must be larger than the width of one sampling period, otherwise there may be situations where the Start and Stop signals cannot be identified. , Subsequent modules will not work.

The pulse of the combined signal and the pulse of the flag signal representing the nature of the pulse arrive at the same time. Reaching at the same time can clearly and accurately indicate whether the pulse of the combined signal is a Start signal or a Stop signal. Further, the Start signal and the Stop signal as the input signal must have a time overlap, and if there is a time overlap, the input signal cannot be distinguished. Therefore, the Start signal and the Stop signal have at least one or more period intervals.

Claims (7)

By adding the output values of all the carry chain of the Start signal, and obtaining the number S ₁ of the carry chain of Start signal has passed,
And calculating the time _{T 1} = _S 1 * _τ based on S _1,
By adding the output values of all the carry chain of the Stop signal, and obtaining the number S ₂ carry chains Stop signal has passed,
To calculate the time T ₂ = S ₂ * τ based on S _2,
It includes outputting the measurement result T = T ₁ + nT _p + (T _p −T ₂ ) based on the time T ₁ and the time T _2.
A high-precision time measurement method based on FPGA. The addition is completed by an adder inside the FPGA.
The method according to claim 1. The addition method uses the addition tree summing method to perform the calculation.
The method according to claim 1. Prior to the addition, the signal includes a step of performing an OR operation on the Start signal and the Stop signal to merge into one composite signal, and a step of pointing out the pulse property of the composite signal using the flag signal. Including further pretreatment,
The method according to any one of claims 1 to 3, wherein the method is characterized by the above. It is possible that the flag signal 1 labels the Start signal in the composite signal and the flag signal 2 labels the Stop signal in the composite signal.
Identifying the rising edge of the composite signal
Includes identifying Start or Stop signals based on rising edges and flag signals.
The flag signal 1 is for labeling the Start signal in the composite signal.
The flag signal 2 is for labeling the Stop signal in the composite signal.
The method according to claim 4, wherein the method is characterized by the above. When a plurality of Stop signals are continuously input, the time between each Stop signal and the Start signal is measured, and the measurement result is output.
The method according to claim 5, wherein the method is characterized by the above. Measuring the time between each Stop signal and the Start signal and outputting the measurement result is
When the first Stop signal is input, the time T ₂ of the first Stop signal is measured, the number n _{1 of T p} between the Start signal and the first Stop signal is recorded, and 1 To output the second time measurement result and
When the second Stop signal is input, the time T ₂ of the second Stop signal is measured, the number n _{2 of T p} between the Start signal and the second Stop signal is recorded, and 2 To output the second time measurement result and
In this way, including the fact that the Nth Stop signal is input and the Nth measurement result is output.
Here, claim 6 is characterized in that N is a positive integer, the number of recorded T _ps is not cleared, and the time measurement result between each Stop signal and Start signal is output. The method described in.

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