JPS63101781A - Tester of logic integrated circuit element - Google Patents

Abstract

PURPOSE:To prevent the damage of the content of rewritable ROM due to the erroneous operation of a logic integrated circuit element to be measured, by using dummy rewritable ROM as a memory device to test the logic integrated circuit element. CONSTITUTION:A logic integrated circuit element 1 and a dummy rewritable ROM(EEPROM) apparatus 6 are combined and an input pattern is given to the logic integrated circuit element 1 by an input pattern generator 2 and the controller 3 thereof and the element 1 is tested while the reading, writing and erasure of the dummy EEPROM apparatus 6 are performed. The data necessary for performing the testing of the element 1 are preset to the part of ROM contained in the apparatus 6. A quality judge part 5 judges the quality of the element 1 from the state of the output terminal of the element 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to electrically rewritable ROM (hereinafter referred to as EE
The present invention relates to a testing device for logic integrated circuit devices that is performed in combination with a ROM (referred to as FROM).

A test performed by combining a conventional technology logic integrated circuit device with a normal EEPROM is, as shown in FIG. A cover pattern is applied to the integrated circuit element 1, and the logic integrated circuit element 1 is tested while reading, writing, and erasing the EEFROM 4. In addition, in Fig. 2, EEFROM
4, 110 is an input/output control section, RAM is a random access memory section, and P is a peripheral control section including a power supply. The quality determination section 5 determines the quality of the logic integrated circuit element 1 based on the status of the output terminal of the element. The test of the logic integrated circuit device 1 in this case is EE
This is performed in connection with the FROM 4, and tests are performed to see if the EEFROM 4 can be written to, read from, and erased correctly, as well as a functional test of the logic integrated circuit element 1. Therefore, for example, by applying a pattern given by the input pattern generator 2 to the logic integrated circuit element 1, data in the EEFROM 4 is read out, and the logic integrated circuit element 1 itself performs predetermined arithmetic processing using the data. Based on the output results, the quality determination section 5 may determine the quality of the logic integrated circuit element.

Problems to be Solved by the Invention However, such a test can be performed without any problems if the logic integrated circuit element 1 operates correctly, but if the integrated circuit element 1 operates incorrectly, the fixed data in the EEPROM 4 may be (In other words, the part that needs to function as a ROM) may be destroyed, and in that case, it is necessary to set the so-called initial conditions again to make the data correct.

Therefore, such a test of the logic integrated circuit device 1 necessarily requires setting the initial conditions to the EEPROM 4, but the writing time of the EEPROM 4 is usually shorter than the normal RA.
It is very long compared to M (as a result, the test time becomes long and at the same time the test procedure itself becomes complicated.

Means for Solving the Problem In order to solve this problem, the present invention does not use an EEPROM when testing logic integrated circuit devices, but provides a pseudo EEPROM that operates in the same manner as the EEPROM. is used as a memory device to test logic integrated circuit elements.

Operation: With this configuration, it is possible to prevent the logic integrated circuit element itself from malfunctioning and destroy ROM-equivalent data in the EEPROM, and it is possible to test the logic integrated circuit element stably and efficiently.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention, in which a logic integrated circuit element 1 and a pseudo EEPROM device 6 are combined, an input pattern generator 2 and its controller 3 are used to create a logic integrated circuit. The logic integrated circuit element 1 is tested while providing an input cover pattern to the element 1 and reading, writing, and erasing the pseudo EEPROM device 6. The internal configuration of the pseudo EEPROM device 6 is 1
10 is an input/output control section, and RAM is a random access memory section.These are the same as before, but a ROM (read only memory) is added to this.
Data necessary for testing the logic integrated circuit element 1 is set in advance in the OM part. Testing of the logic integrated circuit device 1 in this case is performed using a pseudo EEPROM 6, and is substantially the same as the test using the EEPROM 4 shown in FIG. The logic integrated circuit element 1 can be tested to see if it can be read, read, and erased, and furthermore, it can be combined with a pseudo EEPROM 6 to perform a functional test of the logic integrated circuit element 1 such as arithmetic operations.In this case, As can be seen by comparing with Figure 2, EEPR
The peripheral control section P for writing, erasing, etc. as an OM is unnecessary, and the test can be performed stably without destroying preset ROM data.

Effects of the Invention By using the testing device for logic integrated circuit devices according to the present invention, the contents of the EEPROM can be prevented from being damaged due to malfunction of the logic integrated circuit device to be measured (and stable data can be used), and automatic testing devices can be used. It is possible to operate the system stably and conduct high-precision tests.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a logic integrated circuit device testing device according to the present invention, and FIG. 2 is a block diagram of a conventional logic integrated circuit device testing device. l...Logic integrated circuit element, 2...
Input cover turn generator, 3...Controller that controls the entire test equipment, 4...EEPR
OM, 5...Logic integrated circuit element output pattern pass/fail judgment section, 6...Pseudo E E P
ROM device.

Claims (1)

[Claims] A pseudo electrically rewritable ROM is configured by combining an input/output interface, RAM, and ROM, and a test is performed by combining the logic integrated circuit element under test with the pseudo electrically rewritable ROM. Features: Logic integrated circuit device testing equipment.