JPS6298633A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide the electric connection between a semiconductor chip and outer lead with high reliability by a method wherein outer electrodes (terminals) of semiconductor chip are provided separately from probe inspecting electrodes. CONSTITUTION:Each chip is provided with six each of bonding pads 15 separately from probe inspecting pads 10P. Respective six each of bonding pads 15 are connected to specific six each of probe inspecting pads 10P out of 40 each of the probe inspecting pads 10P through conductive layers 10 or the other conductive layers 16. The conductive layers 16 are extended above a topmost insulating layer 13 mainly in active region; one ends of the conductive layers 16 are formed into one body of the bonding pads 15; and the other ends are connected to selected probe inspecting pads 10P through connecting holes 14. In such a constitution, the connecting holes 14 are made only on the upper parts of selected probe inspecting pads 10P since the probe inspecting pads 10P not selected are not connected to the bonding pads 15.

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to an electrode of a semiconductor device. [Background Art] It has been considered to directly mount a chip such as a microcomputer or memory on a printed circuit board or the like to form a module. The chip and the wiring on the substrate must be electrically connected by external leads such as leads or bonding wires. For this purpose, (bonding) pads are provided on the chip as external terminals. The inventor of the present invention discovered the first problem as a result of studying the connection between pads on a chip and wiring on a substrate. That is, for a chip, at the final stage of its wafer manufacturing process? ! ! Probe tests are performed to determine the dynamic and static properties of the gas. Probe testing is typically done using bonding pads placed around the chip. As a result, the conductive layer constituting the bonding pad may be significantly damaged, resulting in a defective connection with the lead or bonding wire. Furthermore, according to the inventor's study, in order to achieve high integration or increase the adhesion area between pads and leads or bonding wires, it is necessary to place pads on areas (active areas) where semiconductor elements such as MOSFETs are formed. It is effective to form the However, during the double probe test,
There is a problem in that it damages the semiconductor element underneath. An example of mounting a chip directly on a printed circuit board is 1, for example, published by Nikkei McGraw-Hill, 11 Kei Electronics, March 2, 1981 issue, p+, 38~
140. [Object of the Invention] An object of the present invention is to establish electrical connections between a semiconductor chip and external leads with high reliability. Another object of the present invention is to form external terminals of a semiconductor chip on a semiconductor element within the semiconductor chip. Another object of the present invention is to provide a technique that allows the external ffi% of a half-quad chip to be placed at any position on a semiconductor chip. Another object of the present invention is to provide a technique that allows the external ffi pole of a semiconductor chip to be formed after inspection. Another object of the present invention is to improve the electrical reliability of semiconductor devices.
The goal is to provide technology that will help achieve this goal. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows. That is, the structure of the present invention, in which the external electrode (terminal) of the semiconductor chip is provided separately from the electrode for probe testing, will be explained together with examples. [Embodiment I] FIG. 1 is a cross-sectional view of the vicinity of the bonding pad of the chip, and FIG. 2 is a plan view of the chip mainly showing the probe testing pad and the bonding pad. As shown in FIG. 1, the chip of this embodiment consists of a semiconductor substrate 1 made of P-type single crystal silicon. A field insulating film 2 made of a silicon oxide film as an element isolation region formed on the surface of a substrate l and a P-type channel stopper region 3 under this field insulating film 2 allow semiconductor devices such as MI S FETs to be An element region to be provided is defined. The MISFET consists of a gate electrode 4 made of a polycrystalline silicon film, a gate insulating film 5 made of a silicon oxide film, and an rl" type semiconductor region 6 that is a source and drain region. Note that the gate electrode 5 is made of a polycrystalline silicon film. For example, it may be a two-layer film in which a high melting point metal film such as Mo, W, Ta, Ti, etc. or a silicide film thereof is provided on top of a polycrystalline silicon film. The gate electrode 5 may be composed only of the film or its silicide film.The n3 type semiconductor region 6A is provided at the periphery of the chip.The wafer is provided outside the n3 type semiconductor region 6A along the side of the chip. There is a dicing area (scribe area) 7 for dividing into individual chips.
A °-type semiconductor region 6B is provided. An insulating film 8 made of a phosphosilicate glass (PSG) film is provided on the substrate 1 so as to cover the MISFET. M
I S FET source and drain regions, i.e. n°
The gate insulating film 5 and the insulating film 8 above the semiconductor region 6 are selectively removed to form a contact hole 9. Absolute 1#
On the film 8 is a conductive layer 1 made of a first aluminum layer.
0 is formed. A conductive layer IO is connected to the n-type semiconductor region 6, which is the source and drain region, through the connection hole 9. This conductive layer 10 connects the n° type semiconductor region 6 to a power supply potential Vc.
c (e.g. 5 [V]) or circuit ground potential ■ss (e.g. O [V]), or MIS FET
electrically connected between them. Further, the conductive layer 10 constitutes a probe testing pad IOP. In this embodiment, a probe testing pad 10P made of a first aluminum layer is arranged on the field insulating film 2 at the outer periphery of the chip, that is, the substrate 1. This probe test pad 10P is used as an electrode for a probe test performed at the final stage of the manufacturing process, that is, for testing the electrical characteristics of the chip. The film thickness of the probe testing pad IOP is approximately 1 [μml]. Further, the probe testing pad top is connected to, for example, the n' type semiconductor region 6, which is the drain region of the MISFET, through the connection hole 9A. In this embodiment, the probe test pad 10P is shown as the first aluminum layer 1O, but the probe test pad 10P is the memory, the output cover sofa, and the logic group 1-1 input/output amplifier. MI of the internal circuit such as
The aluminum connecting between S FETs is made of the same aluminum layer as the two-most layer of aluminum wiring among the RAM wiring. An insulating film 11 made of a silicon nitride film formed by plasma CVD covers the probe testing pad 10P and the conductive layer 1(). One film of the insulating film 11 is approximately I[μml]. The opening 12 is formed by selectively removing the hole portion of the probe testing pad 10F) of the insulating film 11. The probe of the tester is applied to the probe testing pad 10P through this opening 12. An insulating film 13 made of, for example, a silicon nitride film formed by plasma CVD is provided on the insulating film 11. The thickness of the insulating film 13 is approximately 1 [μml]. Insulating film 1
3 covers the upper surface of the probe testing pad IOP exposed from the insulating film 11 in the opening 12 . In this embodiment, the insulating film 13 is placed in the dicing area 7 of the substrate 1.
It is also installed above. Therefore, dicing area 7
is covered with an insulating film 13. That is, there is no exposed portion on at least the upper surface of the substrate l. Therefore, a conductive wire 18 (
(see FIG. 3) will not be short-circuited with the substrate 1. The connection hole 14 is formed by selectively removing the portions of the insulating film 11 and the insulating film 13 above the ends of the probe test pads IOP. Through this connection hole 14, a bonding pad 15 made of a second aluminum layer is connected to the probe testing pad IOP. That is, the bonding pad 15 consists of an aluminum layer above the probe testing pad LOP, that is, the uppermost aluminum layer on the substrate 1. The film thickness of the bonding pad 15 is approximately 1 [μm]. The bonding pad 15 is located in a region of the substrate 1 where a semiconductor element such as a MISFET is provided, that is, an element formation region (
It is provided on the ball in the active area). The bonding pad 15 is a probe testing pad IO.
It is connected to the drain 6 of the MI S FET through P or a conductive layer 10 extending continuously therefrom. That is, the probe testing pad 10P. Alternatively, the wiring for connecting this and the MISFET is used as a conductive layer for connecting the bonding pad 15 to the drain 6 of the MISFET. In addition, the bonding pad 15 is M r S F E
It may be connected to the gate electrode 4 of T. On the other hand, the entire surface of the bonding pad 15 is exposed. That is, no protective film is provided on the bonding pad 15. This is to facilitate the connection between the conductive lead 18 (see FIG. 3) and the bonding pad 15. As shown in FIG. 2, in this embodiment, a plurality of probe testing pads LOP are provided along the periphery of the chip, that is, the substrate 1. As shown in FIG. The length of one side of the probe testing pad IOP is approximately 100 [μm]. On the other hand, the length of one side of the bonding pad 15 is approximately 1 mm1. That is, the bonding pad 15 is made larger than the probe testing pad LOP. Therefore, since there is a large margin for fitting the conductive lead 18 (see FIG. 3) and the bonding pad 15, the connection between the conductive lead 18 and the bonding pad 15 can be easily made. Furthermore, since the bonding area between the conductive lead 1B and the bonding pad 15 is increased, the reliability of bonding between them is improved. Furthermore, bonding does not require high-precision technology or equipment. In FIG. 2, the area surrounded by a two-dot chain line and marked with the symbol A is a ROM (read only memory) area. Similarly, the part marked with a dashed double-dotted line and a mark B is the RAM (random access memory) area, and the part marked with a mark C is a CP area.
This is a logic area such as U (central processing unit) and timer. In this embodiment, six bonding pads 15 are provided for one chip in addition to the probe testing pads 10P. Each of these six bonding pads 15 is connected to a specific six probe testing pads LOP among the 40 probe testing pads LOP through the conductive layer 10 or the conductive WJ 16. The conductive layer 16 is an aluminum layer that is the same layer (second layer) as the bonding pad 15, that is, the uppermost aluminum 911 layer is
Become. The conductive layer 16 mainly extends on the uppermost insulating film 13 above the active region, and one end is formed integrally with the bonding pad 15, and the other end is formed integrally with the selected probe testing pad 10. P is connected through the connection hole 14. Note that the conductive layer 16 is not illustrated in FIG. No bonding pad 15 is connected to any probe testing pad IOP other than the selected probe testing pad IOP. Therefore, the connection hole 14 is also provided only above the selected probe testing pad IOP. Note that the number of bonding pads 15 is not limited to six. In addition, the six bonding pads 15
The arrangement on the substrate 1 is not limited to the above arrangement. That is, the six bonding pads 15 can be placed at arbitrary positions on the chip l. This is the bonding pad 1 in addition to the probe testing pad 10P.
This is due to the provision of 5. The layout of the conductive layer 16 should be such that it is easy to connect the bonding pad 15 and the selected probe testing pad IO.
Where to place P on chip l is arbitrary. FIG. 3 shows a cross section of a module incorporating the chip 1. In FIG. 3, numeral 17 is a printed circuit board made of, for example, epoxy resin containing glass fibers, and has a built-in chip (substrate 1). 18 is a conductive wire (external lead) made of, for example, a copper alloy. This conductive wire 18 connects the bonding pad 15 of the chip (substrate 1) to the electrode 19 of the printed circuit board Fi17. Conductive wires 18 are bonded to bonding pads 15 of chip 1. As explained in FIG.
By making it possible to arbitrarily change the position of the conductive wire 18, the planar layout of the conductive wire 18 can be easily changed. 20 is a surface material made of resin, and this surface material 20 seals the chip l. Next, the method of manufacturing the probe testing pad 10P and bonding pad 15 of this embodiment will be mainly explained. 4 to 11 are cross-sectional views of the vicinity of the probe testing pad LOP and bonding pad 15 of the chip 1 in the manufacturing process of this embodiment. As shown in FIG. 4, a field insulating film 2 and a p-type channel stopper region 3 are formed on an i-type semiconductor substrate 1 by a well-known technique. Furthermore, the gate insulating film 5. Gate electrode 4. n9 which is the source and drain region
A type semiconductor region 6.6A and a dicing area n' type semiconductor region 6B are formed. Next, an insulating film 8 made of a PSG film is formed over the entire surface of the substrate 1 by, for example, CVD. Insulating film 8 and insulating film 5 on n° type semiconductor region 6, which is the source and drain region, are selectively removed by etching to form connection holes 9 and 9A, as shown in FIG. At the same time, in this embodiment, in order to facilitate dicing, the insulating film 8 and the insulating film 5 in the dicing area 7 are selectively removed by etching using a resist film. but,
It is not necessarily necessary to remove the insulating film 8 and the insulating film 5 in the dicing area region 7. Next, a first aluminum layer is formed on the entire surface of the substrate 1 by sputtering, for example,
This aluminum layer is selectively removed by etching to form a conductive layer IO and a probe testing pad LOP. The thickness of the aluminum layer is approximately 1 [μm]. The probe testing pad 10P is formed on the field insulating film 2 at the periphery of the chip 1, as described above. Next, an insulating film 11 made of a silicon nitride film is formed over the entire surface of the substrate 1 by, for example, plasma CVD. The film thickness is l
It should be about [μm]. Next, the insulating film 11 on the probe testing pad LOP is selectively removed by, for example, plasma etching to form an opening 12. At this time, although not particularly limited, the insulating film 11 on the dicing area 7 is removed in the same way as the insulating film 8. The planar pattern of the opening 12 corresponds to the probe testing pad 10P shown in FIG.
Similarly, it has a square or rectangular shape. Next, as shown in FIG. 7, the probe testing pad 10
A probe P of a tester (not shown) is pressed against the surface exposed through the opening 12 of P to carry out a probe test. In this embodiment, as shown in FIG. 2, a total of 40 probe testing pads IOP are provided, 10 on each of the four sides of the substrate 1. A probe P is applied to all of these 40 probe testing pads 10P. The probe testing pad 10P is connected to the M I S FET around the chip 1.
Since the probe P is provided in a region where no semiconductor element such as the probe P is provided, that is, on the field insulating film 2, the semiconductor element such as the MISFET is not damaged by the probe P. That is, it is possible to improve the reliability of the semiconductor device. Next, as shown in FIG. 8, an insulating film 13 made of a silicon nitride film is formed over the entire surface of the substrate 1 by, for example, plasma CVD.
form. The probe testing pad IOP is an insulating film 13
covered by. The thickness of the insulating film 13 is approximately 1 μm. The insulating film 13 is also formed on the dicing area 7. This prevents the silicon surface from being exposed. Next, as shown in FIG. 9, the insulating films 11 and 13 of the ends of the probe testing pads IOP or part of the wiring 10 connected thereto are etched by, for example, plasma etching.
is selectively removed to form the connection hole 14. Connection hole 14
are not provided corresponding to all the probe test pads IOP as shown in FIG. 2, but are formed only for six selected probe test pads IOP. Next, as shown in FIG. 10, a second aluminum layer 15A is formed over the entire surface of the substrate l by, for example, sputtering. The thickness of the aluminum layer 15A is approximately 1 μm. Next, as shown in FIG. 11, unnecessary portions of the aluminum layer 15A are selectively removed by etching to form the bonding pad 15 and the conductive layer 16 shown in FIG. This bonding pad 15 corresponds to the connection hole 14 through the connection hole 14.

[Connected only to the probe testing pad IOP shown in [7]. That is, the bonding pad 15 as an external terminal of the IC is not connected to the probe testing pad 10P through the opening 12, but through an opening 14 formed separately from the opening 12. Ru. In addition, in the following cross-sectional views for explaining the manufacturing process of this example and other examples, the conductive layer 16
is not shown. By forming the bonding pad 15 on the second side of the area (active area) where semiconductor elements such as MISFETs are provided, a large bonding pad 15 with a negative side of about 1 mm 1 can be formed. I can do it. By forming the bonding pad 15 using the uppermost aluminum layer 15A of the chip 1 after the probe test, the bonding pad 15 can be placed at any position on the chip 1. That is, the degree of freedom in arranging the bonding pad 15 is improved. In addition, a large number of chips 1 that have been tested up to the probe test can be stored, and the connection holes 14 and 14 can be adjusted according to the user's wishes (as a master slice). The position and shape of the bonding pad 15 and conductive layer 16 can be determined and formed. [Example 1] Figures 12 to 16 are cross-sectional views of the chip (substrate 1) in the manufacturing process of Example H. Embodiment (2) is intended to reduce the level difference in the connection hole 14 for connecting the probe testing pad IOP and the bonding pad 15. As shown in FIG. 12, the insulating film 11 made of silicon nitride is formed in the same manner as in Example 2. Next, as shown in FIG. 13, the portion of the insulating film 11 above the probe testing good LOP is selectively removed by, for example, plasma etching to form a 1/2 opening. At the same time, a portion of the insulating film 11 that will become the connection hole 14 is selectively removed to form an opening 14A. The opening 12 is provided for all the probe testing pads IOP, but the opening 14A is formed only on the selected probe testing pad 10P in which the connection hole 14 is provided. That is, the opening 14A is not formed in the probe testing parallel plate 10P where the connection hole 14 is not provided. Next, as in Example I, a probe is applied to the test pad LOP through the opening 12 to perform a probe test. Next, as shown in FIG. 14, an insulating film 13 made of a silicon nitride film is formed over the entire surface of the substrate l. Next, as shown in FIG. 15, the insulating film 1 is etched in the portion where the opening 14A was previously formed, for example, by plasma etching.
3 is selectively removed to form a connection hole 14. That is, this etching selectively removes the insulating film 13 so that the connection hole 14 becomes smaller (or larger) than the opening 14A. In this way, since the two-layer insulating film is etched twice to form the contact hole 14, the step difference in the contact hole 14 can be reduced. Next, by the same method as in Example I, as shown in FIG. 16, a bonding pad 15 and a conductive layer 16 (see FIG. 2) made of an aluminum layer with a thickness of [μm] are formed. In order to reduce the level difference of the contact hole 14, the conductive layer 16
A good connection can be made between the probe test pad 10P and the probe test pad 10P. That is, the adhesion of the conductive MjJ 16 at the stepped portion in the connection hole 14 can be improved. [Example 1] Figures 17 to 21 are cross-sectional views of the chip (substrate 1) in the manufacturing process of Example 2. In Example 2, the flatness of the single-layer insulating films 11 and 13 is improved. As shown in FIG. 17, the conductive layer 10 consisting of the first aluminum layer and the probe testing pad 10P are formed in the same manner as in Example 2. ) Next, as shown in FIG. 17, an insulating film 11 is formed by coating the entire surface of the substrate 1 with an organic material such as polyimide resin. The thickness of the insulating film 11 is, for example, so formed that the portion of the field insulating film 2 where the probe test pad 10P is not provided has a thickness of about 2 [μm]. The insulating film 11 also covers the dicing area 7. That is, at least the upper surface of the chip (substrate 1) has no exposed portion.
The portion above 0P is selectively removed by etching to form openings 12 for all pads LOP6.Next, as shown in FIG. is applied to the probe testing pad LOP to perform a probe test. Next, as shown in FIG. 19, an insulating film 13 made of a silicon nitride film is formed over the entire surface of the substrate 1'' by, for example, plasma CVD. The thickness of the insulating film 13 is set to about l [μm]. The surface of the probe testing pad LOP exposed through the opening 12 is covered with an insulating film 13. Next, the bonding pad 15 is attached to the probe testing pad I.
In order to connect to the OP, a predetermined probe test pad I
A contact hole 14 is formed by selectively removing the insulating film 11.13 on the end of the OP or the conductive layer IO connected thereto by etching. Next, as shown in FIG. 20, a bonding pad 15 made of an aluminum layer with a thickness of 1 μm and a conductive layer 16 (see FIG. 2) are formed by the same method as in Example I. In this way, by forming the elastic organic film 1, for example, the insulating film 11 made of polyimide resin, under the bonding pad 15, the flatness of the insulating film 13 on the north side of the insulating film 11 can be improved. Did you do it?1. Thus, the upper surface of the bonding pad 15 can be made flat. Therefore, the bonding area between the bonding pad 15 and the conductive wire 18 (see FIG. 3) increases.
The reliability of the connection between the bonding pads 15 and the conductive leads 18 can be improved. On the other hand, since the insulating film 11 made of the polyimide film has elasticity, it can alleviate the mechanical stress applied to the chip (base [1)] during bonding. That is,
The reliability of the chip (base Fi1) can be improved. On the other hand, since the water-permeable borimid resin film 11 is covered with the dense inorganic film 13, the temperature resistance can be improved. Note that a silicon nitride film formed by plasma CVD may be used as the lower insulating film 11, and a polyimide film may be used as the two-layer insulating film 13. In this case, the lower insulating film (silicon nitride film) 11 is
The thickness of the upper insulating film (polyimide film) 13 is about 2 [μm]. On the other hand, the etching for forming the connection hole 14 may be divided into two steps as in Example (2). As a result, connection hole 1
4 can be alleviated. Therefore, even if the insulating film 11 is formed thick. Disconnection of the conductive layer 16 (see FIG. 2) at the stepped portion within the connection hole 14 can be prevented. [Example 2] Figures 21 to 23 are cross-sectional views of the chip (substrate 1) in the manufacturing process of Example 2. , "Example 2 removes the probe test pad LOP after the probe test is completed, and then removes the bonding pad 15.
It forms the First, in the same manner as in Example I, a first conductive layer 10 made of an aluminum layer and a probe testing pad 10P are formed. Next, after forming the insulating film 11 and the opening 12 according to the steps shown in FIG. 17 and FIG. Perform probe inspection. The probe P is pressed with a predetermined pressure to prevent poor contact between the probe P and the probe testing pad 101]. For this reason, although not taught, the portion of the probe testing pad 10P against which the probe P is pressed is depressed, while the surrounding area is greatly raised. After the probe test is completed, as shown in FIG. 21, the portions of all probe test pads 10P exposed from the opening DI 2 are removed by etching.Next, as shown in FIG. 22, For example, an insulating film 1 made of a silicon nitride film is formed on the entire surface of the substrate 1 by plasma CVD.
form 3. The thickness of the insulating film 13 is set to about 1 [μrn]. The exposed opening 12 of the probe testing pad 10P is covered with an insulating film 13. Next, insulating film 1
1 and 13 are selectively removed by etching to form a connection hole 14. The connection holes 14 are not connected to all the probe testing pads 1' 10P, but to six probe testing pads 10P selected from among the 40 probe testing pads LOP, as in Example 2. Form only for. Next, in the same manner as in Example i, as shown in FIG.
A bonding pad 15 made of an aluminum layer and a conductive layer 16 (see FIG. 2) having a thickness of 1 μm are formed. The plane of the chip (substrate 1) according to this embodiment has the same shape and layout of the bonding pad 15 and conductive layer 1G as in embodiment 2, while the probe testing pad IOP around the chip 1 has disappeared. There is. That is, the plane becomes the same as the example in which the pad 10P is removed in FIG. 2. After bonding pad 15 is formed, a conductive wire 18, shown in FIG. 3, is connected to bonding pad 15. At the time of this connection, since the conductive wire 1B is flexible, there is a possibility that a portion other than the portion resting on the bonding pad 15 may droop. On the other hand, as already mentioned, the probe testing pad LOP is the probe P that is applied during probe testing.
It is greatly deformed due to this, and it comes to have large irregularities. Therefore, the protruding portion of the probe pad IOP is
When forming the film 13 by CVD, the film adheres +! :1
'There is a risk of being exposed. Is the probe testing pad 10P exposed from this insulating film 13 iB '1''?
A short circuit with the raw wire 18 may cause contact with the bonding pad 15 which is not suitable for use. However, in this embodiment, the probe testing pad 1. Since the OP is removed, the probe testing para top is not exposed through the insulating film 13. Therefore, even if the conductive wire 18 hangs down, the conductive wire 18 will not cause the probe testing parallel I~1oP and the bonding pano I/15, which should not be connected, to be exposed by the conductive wire 18. . Note that in this example, the probe inspection pad 10F was selectively removed using the insulating film 11 as a mask, but even if the resist I is removed after the probe inspection band 10P is removed using the resist as a mask. good. [Effect] According to the new technology disclosed by the present application. You can obtain the following effects. (1) By providing a bonding pad separately from the probe test band, the bonding pad can be used as a JK board.
The layerer 1- of the conductive wire connected to the bonding pad can be placed in any position on the 2-
The degree of freedom can be increased. (2) By providing the probe testing pad on the 8-tweald insulating film around the chip, the tester's probe will not destroy the semiconductor element j''- such as MISFET. (3) Since the bonding pad is formed from a single layer of aluminum, the placement of the bonding pad is not limited, so the bonding pad (4) By making the bonding pad larger than the probe testing pad, the bonding area between the bonding pad and the conductive wire increases. It is possible to improve the reliability of the connection between the IL and the like. (5) Connect the bonding pad to the probe test pad I-
The larger size makes it easier to fit the bonding pad and conductive wire together, thereby reducing assembly costs. (6) A large bonding pad can be formed by providing the bonding butt above the active region where the semiconductor element, such as under M r S F E , is provided. (7) By forming an insulating film under the bonding bat over the entire area of the board (1) so that there is no exposed top surface of the board, the conductive wires will not be exposed to the board, so the semiconductor The electrical reliability of the device can be improved. (8) The insulating film under the bonding pad is composed of a polyimide coating film and a silicon nitride film, which improves the flatness of the coating film. (9) The above (8) makes it possible to improve the adhesion between the bonding pad and the conductive wire. (10) According to (8) above, since the polyimide film is soft, damage to the MIS'FET under the bonding bat can be prevented and the reliability of the semiconductor device can be improved. (11), Bonding bat By forming the bonding pad after the probe test is completed, the bonding pad can be placed at any position on the board according to the user's wishes.(+2) By removing the probe test pad after the probe test is completed By pressing the probe of the tester, the raised part of the probe testing pad is removed, so the raised part is not exposed from the insulating film, and therefore the bonding pad and this bonding pad are connected. Since the probe test pads other than the probe test pads that are connected to the probe test pads are not short-circuited by the conductive wire, it is possible to improve the electrical reliability of the semiconductor device. Although the present invention has been specifically described, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist of the invention.For example, conductive leads (fingers or The present invention can also be applied to the formation of a bonding pad when a method using a bonding wire, a method using a bump electrode, etc. are used in addition to the method using a bonding pad (ribbon).As the conductive layer 10 (LOP), 15.16, It is also possible to use a layer made of a material other than aluminum. The semiconductor regions 6A and 6B do not need to be formed in particular. Inspection using the probe test pad can be performed using other methods (electronic probes) rather than metal probes. The present invention is effective not only for MIS type integrated circuit devices but also for various semiconductor devices, and is particularly effective for devices that have a bonding pad and an inspection pad, and in which the bonding pad is This is effective for a semiconductor device having a configuration in which it is electrically connected to some selected pads among a plurality of test pads.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the chip of Example 2, and FIG. 2 is a plan view of the chip of Example I. 3 is a sectional view of the IC module; FIGS. 4 to 11 are sectional views of the chip in the manufacturing process of Example I; FIGS. 12 to 16 are sectional views of the chip in the manufacturing process of Example H; 17 to 20 are cross-sectional views of the chip in the manufacturing process of Example (2), and FIGS. 21 to 23 are cross-sectional views or plan views of the chip in the manufacturing process of Example (2). DESCRIPTION OF SYMBOLS 1...Substrate, 2...Field insulating film, 3...Channel stopper region, 4...Gate'+1! Extreme, 5・
・Gate insulating film, 6.6A, 6B...Semiconductor region, 7.
- Dicing area, 8.11.13... Insulating film, 9.
9A, 14... Connection hole, 10.16... Conductive layer, LO
P...Probe testing pad, 12.14A...Opening,
15... Bonding bat, 15A... Aluminum layer, 17... Printed circuit board, 18... Conductive wire,
19... Electrode of printed circuit board, 20... Surface material, A,
B, C...active area, P...probe. ! Figure 3 Figure 7 Figure 7 Figure 2 Figure 1θ Figure 71 Figure 12 Figure 73 Figure 74 Figure 1 ♂ Figure 76 Figure 20 Figure 22 Figure 23 t.

Claims (1)

[Scope of Claims] 1. A semiconductor device characterized in that a plurality of measurement electrodes are provided around a semiconductor substrate, and an external electrode different from these measurement electrodes is provided on the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the measurement electrode is a probe testing electrode, and the external electrode is a bonding pad. 3. Claims characterized in that the external electrode is connected to some of the plurality of measurement electrodes, and no external electrode is connected to the other measurement electrodes. The semiconductor device according to item 1. 4. A semiconductor device, characterized in that a plurality of measurement electrodes are provided on a semiconductor substrate, and an external electrode is provided in a layer above the measurement electrodes. 5. The semiconductor device according to claim 4, wherein the measurement electrode is a probe testing electrode, and the external electrode is a bonding pad. 6. The scope of claim 1, characterized in that the external electrode is connected to some of the plurality of measurement electrodes, and no external electrode is connected to the other measurement electrodes. 4. The semiconductor device according to item 4. 7. The semiconductor device according to claim 4, wherein the external electrode is located on a region of the semiconductor substrate where a semiconductor element such as a MISFET is provided. 8. The interlayer insulating film between the measurement electrode and the external electrode is
The semiconductor device according to claim 4 or 7, characterized in that it has a soft film such as an organic film. 9. The semiconductor device according to claim 4, wherein the external electrode has a larger area than the measurement electrode. 10. A semiconductor device in which an external electrode is provided separately from a measurement electrode on a region of a semiconductor substrate in which a semiconductor element is provided, and the semiconductor device is characterized in that an insulating film on the semiconductor substrate covers the surface of the semiconductor substrate. semiconductor devices. 11. The semiconductor device according to claim 10, wherein the external electrode is a bonding pad, and the measurement electrode is a probe testing electrode. 12. The semiconductor device according to claim 10, wherein the insulating film on the semiconductor substrate is an interlayer insulating film between the measurement electrode and the external electrode. 13. Claim 10, characterized in that the external electrode is connected to some of the plurality of measurement electrodes, and no external electrode is connected to the other measurement electrodes. 1. Semiconductor device described in Section 1.