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JP2004207556A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004207556A
JP2004207556A JP2002375927A JP2002375927A JP2004207556A JP 2004207556 A JP2004207556 A JP 2004207556A JP 2002375927 A JP2002375927 A JP 2002375927A JP 2002375927 A JP2002375927 A JP 2002375927A JP 2004207556 A JP2004207556 A JP 2004207556A
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Japan
Prior art keywords
pad electrode
bonding
semiconductor device
probe needle
region
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Pending
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JP2002375927A
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Japanese (ja)
Inventor
Shigeru Morita
茂 森田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2002375927A priority Critical patent/JP2004207556A/en
Publication of JP2004207556A publication Critical patent/JP2004207556A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing defects caused by separation or the like of bonding in a bonding process, and also to provide a method for manufacturing the semiconductor. <P>SOLUTION: A pad electrode 1 is formed on the principal plane of a semiconductor substrate 11 through an insulating film 12 so as to separately have a flat portion 21, a region for bonding a bonding wire 2, and a recessed portion 16 serving as a region for grounding a probe needle in measuring performances. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、ボンディング工程でのボンディング剥れ等による不良を低減させた半導体装置と、その製造方法に関する。
【０００２】
【従来の技術】
一般に、半導体装置では、半導体基板の上にトランジスタや抵抗などの素子を形成した後、これらを電気的に接続するためにアルミや銅などの金属材料を用いて素子間配線が形成されている。また、これら半導体基板に形成された半導体装置は、水分や熱、衝撃などの外部環境から半導体装置を保護するために、エポキシ樹脂やセラミックなどの材料で構成されたパッケージにより封止されている。このときパッケージの外部端子（リード）と半導体装置とを電気的に接続する必要がある。通常、半導体基板上に形成された素子間配線から引き出された入出力のパッド電極（ボンディングパッド）とパッケージの外部端子とをボンディング工程により、金線（ボンディングワイヤ）等を熱や超音波を用いて接合することにより電気的な接続をおこなっている。
【０００３】
図１１（ａ）に平面図、図１１（ｂ）にそのＡ−Ａ’位置での断面図を示す。パッド電極５１は、半導体基板５２の上に成膜された絶縁膜５３の上の形成され、さらに、その上に成膜されている保護膜（パッシベーション膜）５４を、フォトリソグラフィー技術及びエッチング技術を用いてを除去し、パッド電極５１としての開口部を形成している。なお、その際、保護膜５４がパッド電極５１の周囲部の上に残るようにマージンを持ってエッチング開口されている。
【０００４】
すなわち、ＬＳＩに電力を供給するか、ＬＳＩからの信号を読み出すために使用される電極であるパッド電極５１は、半導体基板５２の上に形成された、下層の配線層等との絶縁分離用のシリコン酸化膜からなる絶縁膜５３の上に、金属層（Ａｌ／膜厚＝０．４μｍ）により形成されている。このパッド電極５１は、パッド電極５１の表面が５０μｍ×７０μｍの領域にわたって露出部（開口部）を形成しており、その周囲は、外部からの水分、その他不純物の進入を防止する保護膜５４（パッシベーション膜）で被覆されて保護されている。
【０００５】
このパッド電極５１は、後述するボンディング工程でのボンディングワイヤの先端に形成されるボールとの接続領域として使用されるだけではなく、半導体装置の製造工程（検査工程も含めて）においては、ボンディング工程以前の半導体装置の性能評価時に際して、プローブ針の接地にも使用されている。
【０００６】
次に、半導体チップ（ＬＳＩ）の性能評価時の状態について図１２と図１３を用いて説明する。なお、図１１（ａ）、（ｂ）と同一個所に同一符号を付して個々の説明を省略する。
【０００７】
図１２は性能評価時のパッド電極の上部から見た平面図、図１３は、図１２のＡ−Ａ’位置での断面図である。
【０００８】
ＬＳＩの性能評価時には、まず、プローブ針５５の先端５５ａをパッド電極５１の接地始点（Ｘ）に接地させ、次いで接地した状態でプローブ針５５の先端５５ａがパッド電極５１に対して十分な接触抵抗を得る為に、上部より押し付けながら、矢印Ａ方向にプローブ針５５を接地終点（Ｙ）までスライドさせる（スライド長は最低１５μｍ必要）。このスライドさせる目的は、パッド電極５１の表面に形成された酸化膜（Ａｌ２０３）を削り落とし、低抵抗のＡｌ表面を得ることと、プローブ針５５の先端５５ａをＡｌ内部に埋没させ接触面積を広げることである。
【０００９】
このスライドの際に、プローブ針５５の移動によりパッド電極５１の表面には裂傷６０が生じる。裂傷６０の深さはプローブ針５５の針圧、形状などにより異なるが、通常の事例（針圧＝４ｇ、針先端半球形／径＝２０μｍ）では、深さ＝０．３μｍ〜０．６μｍ、幅＝６．６μｍ、長さ＝２９μｍに達する。その際のプローブ針５５とパッド電極５１の接触抵抗は１Ω〜２Ω程度である。
【００１０】
【発明が解決しようとする課題】
上述のように、半導体装置の製造工程では、パッド電極にプローブ針の接地をおこなって性能評価した後に、ボンディング工程でパッド電極を、ボンディングワイヤの先端に形成されるボール（ボールボンディングの場合）との接続領域として使用されている。
【００１１】
ボンディング工程にについて、図１４および図１５を用いて説明する。図１４はパッド電極を上部から見た平面図であり、図１５は、図１４のＡ−Ａ’位置での断面図である。なお、図１１（ａ）および（ｂ）と同一個所に同一符号を付して個々の説明を省略する。
【００１２】
ボンディングの際には、ボンダーによりボンディングワイヤ（Ａｕ）５７の先端に形成されたボール（Ａｕ）５８を、上部よりパッド電極５１の表面に圧着して接合するが、パッド電極５１の表面にボンディング工程の前の性能評価時の際に生じた裂傷６０が存在している。この場合、この裂傷６０の凹凸によりボール５８とパッド電極５１との圧着力が小さくなる部分が生じる。その為、接合強度が低下しボンディングの不良率（ボンディング剥れの発生度合い）が増加する問題が発生する。
【００１３】
これを回避するには裂傷６０を、ボンディングの際にボール５８の下に生じさせないことが必要であるが、生産性向上（ＬＳＩの縮小化）から、パッド電極５１の面積は広げることは好ましくない。また、ＬＳＩ性能評価時のプローブ針５５の接触抵抗を十分に下げるため、プローブ針５５のパッド電極５１の表面でのスライド長は最低１５μｍ必要とされるが、これを特別の付帯機能なしに現状のテスター装置では、制御することは殆ど不可能で、裂傷は必要以上に大きくなりがちである。
【００１４】
そのため、一例を挙げれば、圧着後のボール５８の潰れ径（直径）がφ４０μｍの場合、ボンディング工程の際に、パッド電極５１の上で、パッド電極５１の表面に生じた裂傷６０とボール５８との重なりは避けられない。
【００１５】
本発明はこれらの事情にもとづいてなされたもので、ボンディング工程でのボンディング剥れ等による不良を低減させた半導体装置と、その製造方法を提供することを目的としている。
【００１６】
【課題を解決するための手段】
本発明の手段によれば、主表面を有する半導体基板と、この主表面上に形成された絶縁膜を介してパッド電極が形成されている半導体装置であって、
前記パッド電極は、ボンディングワイヤを接合する接合領域と、性能測定の際のプローブ針の接地領域とに分離されていることを特徴とする半導体装置である。
【００１７】
また本発明の手段によれば、前記パッド電極の接合領域は平坦部で形成され、前記設置領域は窪みが形成されていることを特徴とする半導体装置である。
【００１８】
また本発明によれば、前記絶縁膜は、前記パッド電極に接する面が、平坦部とこの平坦部から窪んだ凹部により形成されていることを特徴とする半導体装置である。
【００１９】
また本発明によれば、前記凹部は、前記プローブ針がスライドする距離よりも大きく形成されていることを特徴とする半導体装置である。
【００２０】
また本発明によれば、前記パッド電極に形成されている前記窪みは、前記絶縁膜に形成された前記凹部に倣って形成されていることを特徴とする半導体装置である。
【００２１】
また本発明によれば、半導体基板の主表面に配置された半導体チップの性能を評価する性能評価工程の後にボンディング工程が設けられた半導体装置の製造方法において、
前記性能評価工程では、測定用のプローブ針をパッド電極の予め定められた領域内でスライドさせ、前記ボンディング工程では前記パッド電極の予め定められたボンディング用の領域にボンディングワイヤを接合することを特徴とする半導体装置の製造方法である。
【００２２】
【発明の実施の形態】
以下、本発明の実施の形態を図面を参照して説明する。
【００２３】
本発明は、パッド電極の表面形状等に関し、パッド電極の開口部の表面で、プローブ針により裂傷が発生している領域を、特定の範囲に限定することで、後のボンディング工程での、ボンディングワイヤの先端のボールとパッド電極との接合の際の、ボンディングの不良率を改善できる。
【００２４】
つまり、パッド電極の開口部の表面において、プローブ針の接地領域とボンディング領域を分離して設けるもので、パッド電極でのプローブ針の接地領域の一部、又は全領域について、パッド電極の下部の絶縁膜に凹部を形成することにより、プローブ針の滑り領域を制限する。それにより、パッド電極に傷つけられたプローブ針による裂傷が、パッド電極のボンディング領域に達しないようにしている。
【００２５】
図１は半導体装置のパッド電極の構造の一例の概要を説明するための模式平面図である。なお、このパッド電極の構造では、パッド電極１を形成しているパッドメタルからビア（不図示）を経由して下層のメタル配線層（不図示）へ電流が流れる。
【００２６】
図１に示す半導体装置１０は、パッド電極１と、ボンディングワイヤ２と、リードフレーム３と、外部ピン４と、内部回路５と、半導体チップ（ＬＳＩ）６等から構成されている。なお、図示されてはいないが、内部回路５はメタル配線層によりパッド電極１に接続される。
【００２７】
このように、半導体チップ（ＬＳＩ）６の内部回路５に対する入出力信号や電源は、通常は半導体チップ６の外周部に配置されたパッド電極１を介して外部ピン４に接続されている。
【００２８】
パッド電極１はその周辺部との関連を、図２に平面図、図３に、図２のＡ−Ａ’位置での断面図を示す。パッド電極１は、半導体基板１１の上に成膜された下層の配線層等との絶縁分離用のためのシリコン酸化膜からなる絶縁膜１２の上に形成されている。なお、パッド電極１は、例えば膜厚が０．４μｍ程度のＡｌを用いた金属層で形成されている。また、パッド電極１の周囲等には、外部からの水分やその他の不純物の進入を防止するための保護膜（パッシベーション膜）１４が形成されている。
【００２９】
なお、図３に示すように、絶縁膜１２はパッド電極１の下方部に該当する部分の半分程度が凹部１５として形成されている。
【００３０】
また、パッド電極１は、上部の保護膜１４がＬＳＩの性能評価時の、後述するテスターのプローブ針の接地や、ボンディングワイヤ２との接続を目的として、５０μｍ×７０μｍ領域に渡って露出して形成されている。このパッド電極１には、下地の絶縁膜１２の凹部１５の形状に倣って凹部状の窪み１６が形成されている。つまり、パッド電極１は、下地層である絶縁膜１２に倣って平坦部と凹部１５に隣接した窪み１６とが形成されている。この平坦部は、ボンディングの際にボールが接合される領域になり、また、窪み１６は、後述するＬＳＩの性能評価時のプローブ針の接地およびスライド領域になる。
【００３１】
なお、ＬＳＩの性能評価時にプローブ針を確実に凹部１５が形成された絶縁膜１２の側壁１２ａに接触させるためには、一旦、プローブ針先を凹部１５の内部まで潜り込ませる必要がある。そのため、プローブ針の接地点の設定は、凹部１５の上方から始まるようにすることが効果的である。また、凹部１５はプローブ針の合せ精度を考慮して、プローブ針の設置領域の全領域を覆うように大きく形成することが望ましい。
【００３２】
次に、これらのパッド電極１によるＬＳＩの性能評価工程とボンディング工程について説明する。
【００３３】
まず、ＬＳＩの性能評価工程について説明する。図４はＬＳＩの性能評価工程の際の平面図で、図５は、図４のＡ−Ａ’位置での断面図である。なお、図２および図３と同一箇所にな同一符号を付して個々の説明を省略する。
【００３４】
ＬＳＩの性能評価の際には、まず、プローブ針１８の先端１８ａをパッド電極１の表面の接地始点（Ｘ）に落として接地させる。次いで、プローブ針１８に対して上方より所定の圧力で押し付けながら、矢印Ｓに沿ってプローブ針１８をスライドさせる。このスライドにより、パッド電極１の表面に形成された酸化膜（Ａｌ２０３）を削り落とし、低抵抗のＡｌ表面を得ることと、プローブ針１８の先端１８ａを、パッド電極１を形成しているＡｌ層の内部に埋没させて接触面積が広げて、良好な電気的な接触を得ている。
【００３５】
スライドしているプローブ針１８の先端１８ａは、パッド電極１の表面に裂傷２０を形成しながら進行し、絶縁膜１２の側壁１２ａに衝突すると停止する。この場合、プローブ針１８の接地点（Ｘ）と絶縁膜の側壁１２ａとのスライド距離Ｓは、例えば１５μｍ程度に設定してある。したがって、パッド電極１の表面に形成された裂傷２０は、パッド電極１の平坦部２１に達することはない。
【００３６】
ＬＳＩの性能評価後におこなわれるボンディング工程については、図６に示すボンディング工程の際の平面図と、図７に示す、図６のＡ−Ａ’位置での断面図で説明する。なお、図６および図７において、図４および図５と同一個所については、同一符号を付して個々の説明を省略する。
【００３７】
ボンダー（不図示）によるボンディングは、パッド電極１のボンディング領域である平坦部２１を用いておこなわれる。つまり、ボンディングワイヤ２（Ａｕ）の先端部に形成されたボール２ａを、ボンダーのキャピラリで所定圧力で押圧してパッド電極１の表面に圧着して接合する。
【００３８】
この場合、平坦部２１に関しては、ＬＳＩの性能評価の際にプローブ針１８のスライド領域の外側であるため、プローブ針１８による裂傷２０が全く発生しておらず、平面度の高い平坦なパッド電極１の表面であるので良好なボンディングをおこなうことができる。
【００３９】
図８は、ボンディング不良率（ボンディング剥がれ数／ボンディング回数）について、上述の実施の形態と、従来の場合とを比較したグラフである。従来の場合は、５．５％程度の不良率であったが、上述の実施の形態の場合は、１．２％程度に低下している。
【００４０】
また、図９は、ボンディング（引っ張り）強度について、本発明の実施の形態と、従来の場合とを比較した数値表である。平均値および最低値の両方共、本発明の実施の形態の場合は強化されている。
【００４１】
これらのことから、本発明の実施の形態では、ボンディングの不良率が改善され、また、接合強度が向上しており、良好なボンディングがおこなわれていることと確認することができた。
【００４２】
次に、上述のパッド電極１の製造方法について説明する。なお、半導体装置１０の構造については、図２および図３を援用している。
【００４３】
まず、半導体基板１１の上に絶縁膜１２を全面に堆積する。その後、リソグラフィ法により絶縁膜１２に凹部１５を形成するためのレジストパターンを形成する。これをエッチングマスクとして反応性イオンエッチングにより加工することにより凹部１５を形成する。この凹部１５が形成された絶縁膜１２の表面にスパッタ法で成膜する。
【００４４】
次に、密着層の上にＡｌ膜をスパッタ法により成膜する。Ａｌ膜は下地の凹部１５に倣って窪み１６が形成される。次に、Ａｌ膜をレジストパターンをマスクにして反応性イオンエッチング（ドライエッチング）によって除去加工し、所定の形状に形成する。
【００４５】
次に、例えばシラン（ＳｉＨ４）ガス及びアンモニア（ＮＨ４）ガスを用い３５０℃程度の成膜温度でプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法により保護膜（パッシベーション膜）１４としてシリコン窒化膜を成膜する。その後、リソグラフィ法及び反応性イオンエッチングを用いてボンディングワイヤ２を接合したり、プローブ針１８を接触させるための開口部（露出部）を保護膜１４に開口してパッド電極１を形成する。なお、その際、保護膜１４がパッド電極１の上に残るようにマージンを持ってエッチングにより開口されている。
【００４６】
図１０は上述の実施の形態の変形例を示す模式構成図である。図１０において図３と同機能の部分には同一符号にａを付してその個々の説明を省略する。この場合は、パッド電極１ａに窪みは形成されていない。ただし、絶縁層１２の凹部１５内に、ビア１５ａとしてＷが埋め込まれている。パッド電極１ａの平面は平坦に形成されている。ただし、ビア１５ａの上方の領域がプローブ針の接地領域であり、ビア１５ａの上方から外れた領域がボンディングワイヤの接合領域である。この構造の場合、プローブ針はパッド電極１ａを突き破ってビア１５ａに接地して移動する。
【００４７】
以上に説明したように、本発明の実施の形態によれば、ＬＳＩの性能評価の際に用いられるプローブ針のスライド運動が、自己整合的にボンディング領域側の凹部の絶縁膜側壁で停止し、パッド電極１の表面に形成されたの裂傷がボンディング領域へ達することを防止できる。また、プローブ針の接地点と絶縁膜の側壁の距離は１５μｍ確保されているため、プローブ針の接触抵抗は従来技術の場合と変わらず１〜２Ωで実験することができる。
【００４８】
それらにより、上述の実施の形態によれば、プローブ針の接触抵抗を損なうことなく、パッド電極の表面の裂傷とボンディングワイヤの先端のボールの接触を防止できるので、ボンディングの接合強度を向上させ、また、ボンディングの不良率を改善できる。
【００４９】
【発明の効果】
本発明によれば、ボンディング工程でのボンディング剥れ等による不良を低減させた半導体装置が実現できる。
【００５０】
また、ボンディング工程でのボンディング剥れ等による不良を低減させた半導体装置の製造方法が可能になる。
【図面の簡単な説明】
【図１】半導体装置のパッド電極の構造の一例の概要の模式平面図。
【図２】本発明のパッド電極の周辺部との関連の平面図、図３に、図２のＡ−Ａ’位置での断面図を示す。
【図３】図２のＡ−Ａ’位置での断面図。
【図４】ＬＳＩの性能評価工程の際の平面図。
【図５】図４のＡ−Ａ’位置での断面図。
【図６】ボンディング工程の際の平面図。
【図７】図６のＡ−Ａ’位置での断面図。
【図８】ボンディング不良率の従来と比較したグラフ。
【図９】ボンディング（引っ張り）強度の従来と比較した数値表。
【図１０】本発明の変形例を示す模式構成図。
【図１１】（ａ）従来の半導体装置の平面図、（ｂ）そのＡ−Ａ’位置での断面図。
【図１２】性能評価時のパッド電極の上部から見た平面図。
【図１３】図１２のＡ−Ａ’位置での断面図。
【図１４】ボンディング時のパッド電極を上部から見た平面図。
【図１５】図１４のＡ−Ａ’位置での断面図である。
【符号の説明】
１、１ａ…パッド電極、２…ボンディングワイヤ、２ａ…ボール、６…半導体チップ、１０…半導体装置、１１…半導体基板、１２、１２ａ…絶縁膜、１４…保護膜、１５…凹部、１５ａ…ビア、凹部１６…窪み、１８…プローブ針、２０…裂傷、２１…平坦部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which defects due to bonding peeling or the like in a bonding step are reduced, and a method for manufacturing the same.
[0002]
[Prior art]
In general, in a semiconductor device, after elements such as a transistor and a resistor are formed on a semiconductor substrate, interelement wiring is formed using a metal material such as aluminum or copper in order to electrically connect these elements. The semiconductor devices formed on these semiconductor substrates are sealed with a package made of a material such as an epoxy resin or a ceramic in order to protect the semiconductor devices from an external environment such as moisture, heat and impact. At this time, it is necessary to electrically connect the external terminals (leads) of the package to the semiconductor device. Normally, an input / output pad electrode (bonding pad) drawn out from a wiring between elements formed on a semiconductor substrate and an external terminal of a package are subjected to a bonding step, and a gold wire (bonding wire) or the like is subjected to heat or ultrasonic waves. The electrical connection is made by joining.
[0003]
FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view taken along the line AA ′. The pad electrode 51 is formed on an insulating film 53 formed on a semiconductor substrate 52, and further, a protective film (passivation film) 54 formed on the insulating film 53 is formed by photolithography and etching. To form an opening as the pad electrode 51. At this time, the protective film 54 is etched and opened with a margin so as to remain on the periphery of the pad electrode 51.
[0004]
That is, the pad electrode 51, which is an electrode used for supplying power to the LSI or reading a signal from the LSI, is formed on the semiconductor substrate 52 for insulation separation from a lower wiring layer and the like. A metal layer (Al / film thickness = 0.4 μm) is formed on the insulating film 53 made of a silicon oxide film. The pad electrode 51 has an exposed portion (opening) formed over a region of 50 μm × 70 μm on the surface of the pad electrode 51, and the periphery thereof is surrounded by a protective film 54 (for preventing moisture and other impurities from entering from the outside). (A passivation film).
[0005]
The pad electrode 51 is used not only as a connection region with a ball formed at the tip of a bonding wire in a bonding process described later, but also in a bonding process in a semiconductor device manufacturing process (including an inspection process). It is also used for grounding probe needles at the time of performance evaluation of previous semiconductor devices.
[0006]
Next, a state at the time of performance evaluation of a semiconductor chip (LSI) will be described with reference to FIGS. 11 (a) and 11 (b) are denoted by the same reference numerals and their description is omitted.
[0007]
FIG. 12 is a plan view seen from above the pad electrode at the time of performance evaluation, and FIG. 13 is a cross-sectional view taken along the line AA ′ in FIG.
[0008]
When evaluating the performance of the LSI, first, the tip 55a of the probe needle 55 is grounded to the ground start point (X) of the pad electrode 51, and then the tip 55a of the probe needle 55 has sufficient contact resistance with the pad electrode 51 in the grounded state. The probe needle 55 is slid in the direction of arrow A to the ground end point (Y) while pressing from above in order to obtain (the slide length must be at least 15 μm). The purpose of this sliding is to remove the oxide film (Al 2 O 3 ) formed on the surface of the pad electrode 51 to obtain a low-resistance Al surface, and to bury the tip 55 a of the probe needle 55 inside the Al to make contact. It is to expand the area.
[0009]
At the time of this sliding, a laceration 60 is generated on the surface of the pad electrode 51 due to the movement of the probe needle 55. The depth of the laceration 60 varies depending on the needle pressure, the shape, and the like of the probe needle 55. In a normal case (needle pressure = 4 g, needle tip hemisphere / diameter = 20 μm), the depth = 0.3 μm to 0.6 μm. Width = 6.6 μm, length = 29 μm. At this time, the contact resistance between the probe needle 55 and the pad electrode 51 is about 1Ω to 2Ω.
[0010]
[Problems to be solved by the invention]
As described above, in the semiconductor device manufacturing process, the pad electrode is grounded to the pad electrode to evaluate the performance, and then, in the bonding process, the pad electrode is connected to a ball formed at the tip of the bonding wire (in the case of ball bonding). Is used as a connection area.
[0011]
The bonding step will be described with reference to FIGS. FIG. 14 is a plan view of the pad electrode as viewed from above, and FIG. 15 is a cross-sectional view taken along the line AA ′ in FIG. 11 (a) and 11 (b) are denoted by the same reference numerals, and their description is omitted.
[0012]
At the time of bonding, a ball (Au) 58 formed at the tip of a bonding wire (Au) 57 by a bonder is pressed from above onto the surface of the pad electrode 51 and joined. Is present at the time of the performance evaluation before the test. In this case, due to the unevenness of the tear 60, a portion where the pressing force between the ball 58 and the pad electrode 51 becomes small occurs. Therefore, there arises a problem that the bonding strength is reduced and the defective rate of bonding (the degree of occurrence of bonding peeling) is increased.
[0013]
In order to avoid this, it is necessary to prevent the tear 60 from being formed below the ball 58 during bonding, but it is not preferable to increase the area of the pad electrode 51 in order to improve productivity (reducing the size of the LSI). . In addition, in order to sufficiently reduce the contact resistance of the probe needle 55 at the time of evaluating the LSI performance, the slide length of the probe needle 55 on the surface of the pad electrode 51 is required to be at least 15 μm. With this tester device, control is almost impossible and tears tend to be unnecessarily large.
[0014]
Therefore, as an example, when the crushing diameter (diameter) of the ball 58 after the pressure bonding is φ40 μm, a crack 60 generated on the surface of the pad electrode 51 and the ball 58 on the pad electrode 51 during the bonding step are formed. Overlap is inevitable.
[0015]
The present invention has been made based on these circumstances, and an object of the present invention is to provide a semiconductor device in which defects due to bonding peeling or the like in a bonding step are reduced, and a method of manufacturing the same.
[0016]
[Means for Solving the Problems]
According to the means of the present invention, there is provided a semiconductor device having a semiconductor substrate having a main surface and a pad electrode formed through an insulating film formed on the main surface,
The semiconductor device is characterized in that the pad electrode is separated into a bonding area for bonding a bonding wire and a ground area of a probe needle for measuring performance.
[0017]
Further, according to the means of the present invention, the semiconductor device is characterized in that the bonding region of the pad electrode is formed with a flat portion, and the installation region is formed with a depression.
[0018]
Further, according to the present invention, in the semiconductor device, the insulating film has a surface in contact with the pad electrode formed by a flat portion and a concave portion recessed from the flat portion.
[0019]
Further, according to the present invention, in the semiconductor device, the concave portion is formed to be longer than a distance by which the probe needle slides.
[0020]
Further, according to the present invention, the semiconductor device is characterized in that the depression formed in the pad electrode is formed following the depression formed in the insulating film.
[0021]
Further, according to the present invention, in a method of manufacturing a semiconductor device in which a bonding step is provided after a performance evaluation step of evaluating the performance of a semiconductor chip disposed on a main surface of a semiconductor substrate,
In the performance evaluation step, a probe needle for measurement is slid within a predetermined area of the pad electrode, and in the bonding step, a bonding wire is bonded to a predetermined bonding area of the pad electrode. Is a method of manufacturing a semiconductor device.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
The present invention relates to the surface shape of a pad electrode and the like, by limiting a region where a tear is caused by a probe needle on a surface of an opening portion of a pad electrode to a specific range, thereby enabling bonding in a subsequent bonding step. The defective rate of bonding at the time of joining the ball at the tip of the wire and the pad electrode can be improved.
[0024]
In other words, on the surface of the opening of the pad electrode, the grounding region of the probe needle and the bonding region are provided separately, and a part or the whole of the grounding region of the probe needle at the pad electrode is provided below the pad electrode. By forming a concave portion in the insulating film, the sliding region of the probe needle is limited. As a result, the tear caused by the probe needle damaged by the pad electrode is prevented from reaching the bonding region of the pad electrode.
[0025]
FIG. 1 is a schematic plan view for explaining an outline of an example of the structure of a pad electrode of a semiconductor device. In this pad electrode structure, a current flows from a pad metal forming the pad electrode 1 to a lower metal wiring layer (not shown) via a via (not shown).
[0026]
A semiconductor device 10 shown in FIG. 1 includes a pad electrode 1, a bonding wire 2, a lead frame 3, an external pin 4, an internal circuit 5, a semiconductor chip (LSI) 6, and the like. Although not shown, the internal circuit 5 is connected to the pad electrode 1 by a metal wiring layer.
[0027]
As described above, the input / output signals and the power supply to the internal circuit 5 of the semiconductor chip (LSI) 6 are normally connected to the external pins 4 via the pad electrodes 1 arranged on the outer periphery of the semiconductor chip 6.
[0028]
FIG. 2 is a plan view, and FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2, showing the relationship between the pad electrode 1 and its peripheral portion. The pad electrode 1 is formed on an insulating film 12 made of a silicon oxide film for insulating isolation from a lower wiring layer and the like formed on the semiconductor substrate 11. The pad electrode 1 is formed of, for example, a metal layer using Al having a thickness of about 0.4 μm. A protective film (passivation film) 14 for preventing moisture and other impurities from entering from outside is formed around the pad electrode 1 and the like.
[0029]
As shown in FIG. 3, the insulating film 12 is formed as a recess 15 in about half of a portion corresponding to a lower portion of the pad electrode 1.
[0030]
The pad electrode 1 is exposed over the 50 μm × 70 μm area for the purpose of grounding a probe needle of a tester, which will be described later, and connecting with the bonding wire 2 at the time of evaluation of the performance of the LSI. Is formed. The pad electrode 1 is formed with a concave-shaped depression 16 following the shape of the concave portion 15 of the underlying insulating film 12. That is, the pad electrode 1 has a flat portion and a dent 16 adjacent to the concave portion 15 formed following the insulating film 12 which is a base layer. The flat portion serves as a region where a ball is bonded at the time of bonding, and the depression 16 serves as a grounding and sliding region of a probe needle at the time of LSI performance evaluation described later.
[0031]
In order to surely bring the probe needle into contact with the side wall 12a of the insulating film 12 in which the concave portion 15 is formed at the time of evaluating the performance of the LSI, it is necessary to temporarily sink the probe needle tip into the concave portion 15. Therefore, it is effective to set the contact point of the probe needle from above the concave portion 15. Further, it is desirable that the concave portion 15 be formed large so as to cover the entire area of the installation area of the probe needle in consideration of the accuracy of alignment of the probe needle.
[0032]
Next, an LSI performance evaluation process and a bonding process using these pad electrodes 1 will be described.
[0033]
First, an LSI performance evaluation process will be described. FIG. 4 is a plan view at the time of an LSI performance evaluation step, and FIG. 5 is a cross-sectional view taken along the line AA ′ in FIG. 2 and 3 are denoted by the same reference numerals, and the description thereof will not be repeated.
[0034]
When evaluating the performance of the LSI, first, the tip 18a of the probe needle 18 is dropped to the ground start point (X) on the surface of the pad electrode 1 and grounded. Next, the probe needle 18 is slid along the arrow S while being pressed against the probe needle 18 from above by a predetermined pressure. By this slide, an oxide film (Al 2 O 3 ) formed on the surface of the pad electrode 1 is scraped off to obtain a low-resistance Al surface, and the tip 18 a of the probe needle 18 is formed by forming the pad electrode 1. The contact area is widened by being buried in the inside of the Al layer, and good electrical contact is obtained.
[0035]
The tip 18 a of the sliding probe needle 18 advances while forming a tear 20 on the surface of the pad electrode 1, and stops when it collides with the side wall 12 a of the insulating film 12. In this case, the slide distance S between the ground point (X) of the probe needle 18 and the side wall 12a of the insulating film is set to, for example, about 15 μm. Therefore, the laceration 20 formed on the surface of the pad electrode 1 does not reach the flat portion 21 of the pad electrode 1.
[0036]
The bonding step performed after the performance evaluation of the LSI will be described with reference to a plan view of the bonding step shown in FIG. 6 and a cross-sectional view taken along the line AA 'of FIG. 6 shown in FIG. 6 and 7, the same portions as those in FIGS. 4 and 5 are denoted by the same reference numerals, and the description thereof is omitted.
[0037]
Bonding by a bonder (not shown) is performed using a flat portion 21 which is a bonding region of the pad electrode 1. In other words, the ball 2a formed at the tip of the bonding wire 2 (Au) is pressed with a predetermined pressure by the capillary of the bonder and is bonded to the surface of the pad electrode 1 by pressing.
[0038]
In this case, since the flat portion 21 is outside the sliding area of the probe needle 18 at the time of evaluating the performance of the LSI, no nick 20 is generated by the probe needle 18 and the flat pad electrode having high flatness is obtained. Since the first surface is used, good bonding can be performed.
[0039]
FIG. 8 is a graph comparing the above-described embodiment and the conventional case with respect to the bonding failure rate (the number of bonding peelings / the number of bonding times). In the conventional case, the defect rate was about 5.5%, but in the above-described embodiment, it was reduced to about 1.2%.
[0040]
FIG. 9 is a numerical table comparing the bonding (tensile) strength of the embodiment of the present invention with the conventional case. Both the average and the minimum are enhanced in the embodiment of the present invention.
[0041]
From these facts, it was confirmed that in the embodiment of the present invention, the defective rate of bonding was improved, the bonding strength was improved, and good bonding was performed.
[0042]
Next, a method for manufacturing the above-described pad electrode 1 will be described. 2 and 3 are referred to for the structure of the semiconductor device 10.
[0043]
First, an insulating film 12 is deposited on the entire surface of a semiconductor substrate 11. Thereafter, a resist pattern for forming the recess 15 in the insulating film 12 is formed by lithography. Using this as an etching mask, the recess 15 is formed by processing by reactive ion etching. A film is formed by a sputtering method on the surface of the insulating film 12 in which the concave portions 15 are formed.
[0044]
Next, an Al film is formed on the adhesion layer by a sputtering method. In the Al film, a depression 16 is formed following the concave portion 15 of the base. Next, the Al film is removed by reactive ion etching (dry etching) using the resist pattern as a mask to form a predetermined shape.
[0045]
Next, a silicon nitride film is formed as a protective film (passivation film) 14 by a plasma CVD (Chemical Vapor Deposition) method at a film forming temperature of about 350 ° C. using, for example, a silane (SiH 4 ) gas and an ammonia (NH 4 ) gas. I do. Thereafter, the pad electrode 1 is formed by bonding the bonding wire 2 using lithography and reactive ion etching, and opening an opening (exposed portion) for contacting the probe needle 18 in the protective film 14. At this time, an opening is formed by etching with a margin so that the protective film 14 remains on the pad electrode 1.
[0046]
FIG. 10 is a schematic configuration diagram showing a modification of the above embodiment. In FIG. 10, portions having the same functions as those in FIG. In this case, no depression is formed in the pad electrode 1a. However, W is buried as a via 15 a in the recess 15 of the insulating layer 12. The plane of the pad electrode 1a is formed flat. However, a region above the via 15a is a ground region of the probe needle, and a region deviated from above the via 15a is a bonding region of the bonding wire. In the case of this structure, the probe needle penetrates the pad electrode 1a and moves while being grounded to the via 15a.
[0047]
As described above, according to the embodiment of the present invention, the sliding movement of the probe needle used in evaluating the performance of the LSI stops on the insulating film side wall of the concave portion on the bonding region side in a self-aligned manner, The tear formed on the surface of the pad electrode 1 can be prevented from reaching the bonding region. Further, since the distance between the ground point of the probe needle and the side wall of the insulating film is 15 μm, the contact resistance of the probe needle can be experimented with 1 to 2Ω as in the case of the prior art.
[0048]
According to them, according to the above-described embodiment, it is possible to prevent the laceration of the surface of the pad electrode and the contact of the ball at the tip of the bonding wire without impairing the contact resistance of the probe needle. In addition, the bonding failure rate can be improved.
[0049]
【The invention's effect】
According to the present invention, a semiconductor device in which defects due to bonding peeling or the like in a bonding step are reduced can be realized.
[0050]
Further, a method of manufacturing a semiconductor device in which defects due to bonding peeling or the like in a bonding step are reduced is enabled.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing an outline of an example of the structure of a pad electrode of a semiconductor device.
FIG. 2 is a plan view relating to a peripheral portion of a pad electrode according to the present invention, and FIG. 3 is a cross-sectional view taken along a line AA ′ in FIG.
FIG. 3 is a sectional view taken along a line AA ′ in FIG. 2;
FIG. 4 is a plan view at the time of an LSI performance evaluation step.
FIG. 5 is a sectional view taken along a line AA ′ in FIG. 4;
FIG. 6 is a plan view at the time of a bonding step.
FIG. 7 is a sectional view taken along the line AA ′ in FIG. 6;
FIG. 8 is a graph showing a bonding failure rate in comparison with the related art.
FIG. 9 is a numerical table of bonding (tensile) strength in comparison with the related art.
FIG. 10 is a schematic configuration diagram showing a modified example of the present invention.
11A is a plan view of a conventional semiconductor device, and FIG. 11B is a cross-sectional view taken along the line AA ′.
FIG. 12 is a plan view seen from above a pad electrode during performance evaluation.
FIG. 13 is a sectional view taken along the line AA ′ in FIG. 12;
FIG. 14 is a plan view of a pad electrode during bonding as viewed from above.
FIG. 15 is a cross-sectional view taken along a line AA ′ in FIG.
[Explanation of symbols]
1, 1a pad electrode, 2 bonding wire, 2a ball, 6 semiconductor chip, 10 semiconductor device, 11 semiconductor substrate, 12 and 12a insulating film, 14 protective film, 15 recess, 15a via , Recess 16: depression, 18: probe needle, 20: tear, 21: flat part

Claims (6)

主表面を有する半導体基板と、この主表面上に形成された絶縁膜を介してパッド電極が形成されている半導体装置であって、
前記パッド電極は、ボンディングワイヤを接合する接合領域と、性能測定の際のプローブ針の接地領域とに分離されていることを特徴とする半導体装置。A semiconductor device having a semiconductor substrate having a main surface and a pad electrode formed via an insulating film formed on the main surface,
The semiconductor device according to claim 1, wherein the pad electrode is separated into a bonding region for bonding a bonding wire and a ground region of a probe needle for measuring performance. 前記パッド電極の接合領域は平坦部で形成され、前記設置領域は窪みが形成されていることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a bonding region of said pad electrode is formed with a flat portion, and said installation region is formed with a depression. 前記絶縁膜は、前記パッド電極に接する面が、平坦部とこの平坦部から窪んだ凹部により形成されていることを特徴とする請求項２に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the insulating film has a surface in contact with the pad electrode formed by a flat portion and a concave portion recessed from the flat portion. 4. 前記凹部は、前記プローブ針がスライドする距離よりも大きく形成されていることを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the recess is formed to be longer than a distance over which the probe needle slides. 5. 前記パッド電極に形成されている前記窪みは、前記絶縁膜に形成された前記凹部に倣って形成されていることを特徴とする請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the depression formed in the pad electrode is formed following the depression formed in the insulating film. 5. 半導体基板の主表面に配置された半導体チップの性能を評価する性能評価工程の後にボンディング工程が設けられた半導体装置の製造方法において、
前記性能評価工程では、測定用のプローブ針をパッド電極の予め定められた領域内でスライドさせ、前記ボンディング工程では前記パッド電極の予め定められたボンディング用の領域にボンディングワイヤを接合することを特徴とする半導体装置の製造方法。In a method of manufacturing a semiconductor device provided with a bonding step after a performance evaluation step of evaluating the performance of a semiconductor chip disposed on a main surface of a semiconductor substrate,
In the performance evaluation step, a probe needle for measurement is slid within a predetermined area of the pad electrode, and in the bonding step, a bonding wire is bonded to a predetermined bonding area of the pad electrode. Manufacturing method of a semiconductor device.
JP2002375927A 2002-12-26 2002-12-26 Semiconductor device and its manufacturing method Pending JP2004207556A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008015499A1 (en) * 2006-08-01 2008-02-07 Freescale Semiconductor, Inc. Method and apparatus for improving probing of devices
JP2008205293A (en) * 2007-02-21 2008-09-04 Seiko Epson Corp Semiconductor device and manufacturing method thereof
JP2013229634A (en) * 2013-07-29 2013-11-07 Renesas Electronics Corp Semiconductor device
JP2016152299A (en) * 2015-02-17 2016-08-22 三菱電機株式会社 Semiconductor device and semiconductor module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008015499A1 (en) * 2006-08-01 2008-02-07 Freescale Semiconductor, Inc. Method and apparatus for improving probing of devices
JP2008205293A (en) * 2007-02-21 2008-09-04 Seiko Epson Corp Semiconductor device and manufacturing method thereof
JP4636283B2 (en) * 2007-02-21 2011-02-23 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP2013229634A (en) * 2013-07-29 2013-11-07 Renesas Electronics Corp Semiconductor device
JP2016152299A (en) * 2015-02-17 2016-08-22 三菱電機株式会社 Semiconductor device and semiconductor module

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