JPS6292474A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accurately specify a gate length and a shallow impurity region length by properly selecting the thickness of a third film and isotropically etching condition. CONSTITUTION:A resist layer is attached to the fourth film 7, and patterned to allow a pattern 8 for specifying a deep impurity region in an element region 2 to remain. With the pattern 8 as a mask the film 7 is removed by etching to form the fourth film portion 7a. The pattern 8 on the portion 7a is removed, with the portion 7a as a mask the third film 6 is wet etched with a thermal phosphoric acid, undercut until desired gate length is obtained, and the third film portion 6a is formed. Then, with the portion 7a as a mask the second film 5 is removed by etching, with the portion 7a as a mask As ions 10 are deeply implanted into the substrate 1 to form the first impurity region 11. Thereafter, the portion 7a is removed with BHF solution, with the portion 6a as a mask the second film 5 is etched to the gate length.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and is applied to a so-called LDD structure M08FgT.

tp■ Conventional technology The manufacturing method of a conventional M08 transistor having an LDD structure is as follows: ■ 81) Using a film made of N4 or 8102 as an etching mask, the polysilicon film that is the gate material is undercut to form a shallow impurity in the semiconductor substrate. How to form a region (8,0GURA @t al TW
RTI Trans, ED-27, 819801) 4
1) p. 60) and ■ After forming a shallow impurity region, a sidewall is formed around the I-N gate F electrode, and a deep impurity region is formed using these as a mask (Mitsuhashi et al., Semiconductor Integrated Circuit Technology W & 28th Symposium In 1985,
Although the 5th degree is formed, in order to make an undercut, it is necessary to perform a strongly isotropic etching.

As a result, as shown in Figure @2, the shape of the polysilicon film (Pi) is not suitable for microfabrication.
It is difficult to form the DD structure with high precision. In addition, in the method (2), as shown in FIG. It has the disadvantage of poor reproducibility.

(c) Problems to be solved by the invention The present invention was created in view of the drawbacks of both of the above methods.
Forming a DD Structure I: An object of the present invention is to provide a method for manufacturing a semiconductor device that has a suitable external shape of a gate electrode and can improve the reproducibility of the length of a shallow impurity region.

B) Means for solving the problems The present invention line C2 on the first film which becomes the gate insulating film on the semiconductor substrate, the second film which becomes the gate electrode, and the fifth film which becomes the etching mask for this second film. , a method for manufacturing a semiconductor device in which a fourth film serving as an isotropic etching mask for the third film is sequentially provided, and the gate length and the shallow impurity region length are precisely defined by the undercut length of the above-mentioned '@3 film. This is what we are trying to provide.

Function of the present invention The gate length of a channel region in a semiconductor substrate and the length of a shallow impurity region adjacent to the channel region to define this gate length are provided on a second film constituting a gate electrode. The third film can be defined by isotropically etching the gJ14M on the third armpit as an etching mask.

That is,! By appropriately selecting the KM thickness and the isotropic etching conditions, the arbitrariness and reproducibility of each of the above members can be better controlled.

(f) Example One example of the method of the present invention will be described with reference to the process diagram shown in FIG.

First, a hexagonal area (21) and an agglomerated isolation area (3) are formed on a semiconductor substrate (1) using a well-known method such as the LOOO8 method. In the figure, only one direction cross section of one element area is shown for simplicity. However, in reality, E shows that a large number of element regions are formed within the plane of the semiconductor substrate (1).

On the surface (1.) of the semiconductor substrate (1), a 5102 film (first film) (4), which will serve as an insulating gland, is formed to a thickness of about 5Q nm (-zl) by thermal oxidation or the like.

After that, OVD method I: Therefore, a polysilicon film (second film) (5) for forming the gate electrode was formed to a thickness of 400 nm.
(x = t 2), and further 1:, nitride (
81) N4) film (third film) (61) and P2O film (fourth film) (7) each have a thickness of 7 Q nm (- is black).

100 nm (100 nm) are deposited one after another by a well-known method (FIG. 1A). In this example, the fourth film (7) has a phosphorus concentration of 8 wt.

Next, buttering is performed on the fourth film (7) (an Nire rest layer is attached) and a pattern (8) defining the element region (21 circles deep impurity region (described later)) is left.

Then, as a mask to this pattern (81), RIE
The fourth film (7) is etched away using a technique to form a fourth film portion (71Li) (first etching step, Fig. 1B).
).

Next 4: Resist pattern (8) on the fourth film portion (71)
) and then heat phosphor using this $44 film (7a) as a mask (wet-etch the fifth layer (6) at 180°C twice a month, undercutting until the desired gate length is obtained). - Perform the third film portion (6B) to form a tube (second etching step), region (9) shows the undercut portion and corresponds to the length of the shallow impurity region to be formed in a later step. (Figure 1 O).

Next (2) Etch and remove the *2 film (5) using the RIπ technique using the 4th vA portion (7a) as a mask (IJ
3 etching step), then this fourth film portion (71)
As a mask, All of about 1×10 cilI
Ions a (1) are deeply implanted into the semiconductor substrate (1) to form a deep impurity region (first impurity region) aυ (i
t ion implantation process, 1st) JD). Then the fourth membrane part (
71L) is removed using a BHF solution (membrane removal step, FIG. 1E). At this time, in order to obtain an etching rate of the fourth film such that the 's1 film (4) on the impurity region av remains, the phosphorus concentration in the fourth region is selected as described in -F.

Next, using the third film portion (6&) as a mask, the $2 film (5) is etched by the gate length by RIE technology. RIP at this time is 10PA, RF O, 16
If etching is carried out using 81074 gas under W/- conditions, the selectivity ratio between the @3 film and the second film will be 1:30, and the above film thickness ratio will be sufficient.

After this, All ions a of lX1Q (m
3 into the semiconductor substrate (1) to form a shallow impurity region (
$2 impurity region) (13 is formed between the channel region a4 and the first impurity region (1) 1 (FIG. 1F). After that.

The third film portion (61L) on the second film portion (date electrode) (51L) is removed using hot phosphoric acid to manufacture a semiconductor device having the LDD structure shown in the first factor G.

(g) Effects of the Invention In the method of the present invention, as mentioned above, the thickness of the third film portion is sufficiently thin, so even in isotropic etching, it is possible to form a sharp cross-sectional shape as shown in the figure. This has the effect of making it easy to specify the length. Furthermore, since the second film can be etched by RIll, W
The cross-sectional shape of the I2 film portion can be sharpened, making microfabrication possible.

Further 1: Since the length of the shallow impurity region is defined by the undercut part of the vI3 waist region, this length can be arbitrarily adjusted because the controllability of this length is good, and the reproducibility is also good. .

[Brief explanation of drawings]

1A-Ck are process explanatory diagrams of the method of the present invention, and FIGS. 2 and 3 are partial sectional views of intermediate products obtained by different conventional methods. (1)...Semiconductor substrate, (4)...First film, (5)
...Second film, (6)...Third film, (7)...9A
4 membrane, (71)...4th membrane part. aυ...W1) 1 impurity region, (61L)...3rd
Film portion, (+31... second impurity region.

Claims (1)

[Claims] (1) A first film serving as a gate insulating film, a second film serving as a gate electrode, a third film made of a material exhibiting isotropic etching characteristics during etching, and a fourth film on the surface of the semiconductor substrate.
a first etching step of etching away the fourth film so as to selectively leave a portion of the fourth film in the vicinity of the gate electrode;
a second etching step in which the third film is etched away using the fourth film portion left by the etching step as a mask, and during this etching, the third film immediately below the outer peripheral portion of the fourth film portion is also removed at the same time; a third etching step of etching away the second film using the fourth film portion as a mask; and a first etching step of deeply implanting impurity ions into the semiconductor substrate using the fourth film portion as a mask to form a first impurity region.
an ion implantation step, a film removal step of removing the fourth film portion, and a third step of etching away the exposed portion of the second film using the third film portion left by the second etching step as a mask. A method of manufacturing a semiconductor device comprising: an etching step; and a second ion implantation step of shallowly implanting impurity ions into the semiconductor substrate using the third film portion as a mask to form a second impurity region.