JPS61180448A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To protect a gate electrode from disconnection by a method wherein a silica film is provided by application on the entire surface of a semiconductor substrate for filling recesses produced in an etching process. CONSTITUTION:On a semiconductor substrate 1, an oxide film 2, nitride film 3, and a channel stopper 4 are formed. An insulating film 5 and a photoresist film 6 are formed and then the insulating film 5 is subjected to etching. A process follows wherein the nitride film 3 is removed and the entire surface is covered with a silicon film 9 provided by application for the flattening of the substrate surface. The film 9 is then subjected to baking, which is followed by an etching process wherein the oxide film 2 is removed from the substrate 1. A gate oxide film 7 is formed, whereinto impurity ions 10 are implanted for the control of the FET threshold value. A process is accomplished for the formation of a gate electrode 11 and a source.drain 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a field-effect semiconductor device including a method of forming an insulating isolation region between individual diffusion layers.

(Prior art) Conventionally, LOC (J8 method) and trench type separation method have been used to separate individual diffusion layers of field effect semiconductor devices. In this case,
Since there is a disadvantage that the oxide film for insulation isolation digs into the diffusion layer region, effectively reducing the width of the diffusion layer, the latter trench type isolation method is currently being developed. Currently known trench isolation methods (separation methods in which an insulating material is buried in the trenches)
There are two methods.

FIGS. 2a) to 2(d) are cross-sectional views showing a detailed process order for explaining a first method of trench type insulation isolation of a conventional field effect semiconductor device.

First, as shown in FIG. 2(a), a thin oxide film 2 and a thin nitride film 3 are sequentially grown on a semiconductor substrate, and the nitride film 3. Oxide film 2. Semiconductor substrate 1t is vertically etched using anisotropic etching to form #l. Next, after oxidizing the bottom and side surfaces of the groove, ions of impurities having the same conductivity type as the semiconductor substrate 1 are implanted into the bottom of the groove to form a channel stopper 4.

Next, as shown in FIG. 2(b), the semiconductor substrate 1 is etched to a thickness equal to the depth of the insulating film 5't-113 using the CVD method.
grow on ゛.

Next, as shown in FIG. 2(C), a photoresist 6 is formed on the groove.

Next, as shown in FIG. 2Fdl, etching is performed using a buffered hydrofluoric acid solution by the thickness of the insulating film grown by the CVD method. The photoresist 6 is removed, the nitride film 3 and the oxide film 2t are removed, and a gate oxide film 7 is formed on the diffusion layer.
Fully formed.

FIGS. 3A and 3B are cross-sectional views illustrating a second method of trench isolation of a conventional field-effect semiconductor device in the order of steps.

Follow the same procedure as the first method up to the step shown in FIG. 2(b).

Next, as shown in FIG. 3(a), a photoresist 8 is thinly applied over the entire surface of the insulating film 5. Then, as shown in FIG.

Next, as shown in FIG. 3(b), the entire surface is etched using a parallel plate type dry etching device, and the insulating film 5 on the diffusion layer region is etched. After that, the nitride film 3 and the oxide film 2 are etched. Then, a gate oxide film (6) is formed on the diffusion layer.

(Problems to be Solved and Eliminated by the Invention) When groove separation between diffusion layers is performed by the above two methods, the following problems occur.

(1) In the first method of etching using a buffered hydrofluoric acid solution, it is difficult to set the end point of etching, and due to the etching conditions, unevenness occurs at the edge of the separation region, and when forming the gate electrode,
The gate electrode material present in the recess remains unetched, which not only causes a short circuit 2 between the gate electrodes, but also may cause disconnection of the gate electrode wiring if the recess is deep.

Furthermore, if misalignment occurs in the formation of the photoresist left on the groove, the insulating film remains on the diffusion layer, and one end of the groove may be etched to the bottom of the groove.

(2) Method @2 When etching the entire surface using a parallel plate type dry etching apparatus, it is difficult to detect the end point of etching. Furthermore, is it wide? The insulating film 5 in the wide isolation region (flC) becomes thin, and in some places, it does not exist at all. Therefore, in the second method, there is a limit to the width of the isolation region, and the usable width of the isolation region (width of the groove) is limited.

As described above, the conventional trench type isolation method, whichever is used, can stably perform the entire insulation isolation between the diffusion layers, and can create a flat insulation region without being limited by the isolation width. The problem is that it is impossible to form.

For the purpose of the present invention, it is possible to form a trench-type insulation isolation region between diffusion layers of a field effect semiconductor device without being limited by the width of the insulation isolation region between D1 diffusion layers, and to stably and flatten the insulation isolation region between diffusion layers of a field effect semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to form an insulating isolation region.

(Means for Solving the Problems) A method for manufacturing a semiconductor device of the present invention includes the steps of sequentially depositing an oxide film and a nitride film on the surface of a semiconductor substrate, and selectively etching the nitride film and the oxide film. Next, forming a groove in the isolation region of the semiconductor substrate by anisotropic etching;
a step of stubbornly depositing an F insulating film on the semiconductor substrate; a step of forming a mask of 7 photoresist having the same pattern as the groove on the insulating film; and a step of forming a diffusion layer using the photoresist as a mask. A step of removing the insulating film on the target area by isotropic etching, a step of removing the photoresist and the nitride film, and a step of applying a silica film on the entire surface of the semiconductor substrate and by the isotropic etching. a step of filling the concave portion at the end of the groove, a step of baking the silica film, a step of etching the oxide film on the region to become the diffusion layer with buffered hydrofluoric acid, and a step of etching the region to become the diffusion layer. The bottom of the tank is formed by forming a gate oxide film thereon.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIGS. 1(a) to 1(gl) are cross-sectional views of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1, a thin oxide film 2t is grown on a semiconductor substrate 1, and then a nitride film 3 is deposited thereon. The nitride film 3 in the region to become the insulation isolation region is removed, and then the semiconductor substrate if is vertically etched to a predetermined depth by anisotropic etching to form Ist'', and an oxide film is formed on the bottom and side surfaces thereof. Then, all ions of impurities having the same conductivity type as that of the semiconductor substrate are implanted to form a channel stopper 4.

Next, as shown in FIG. 1, an insulating film 51&: is grown on the semiconductor substrate to a thickness equal to the depth of the groove using the CVD method.

Next, as shown in FIG. 1C, a photoresist 6 is formed on the groove using a photomask having a pattern in which the bright and dark areas of the photomask used to form the groove are reversed.

Next, as shown in FIG. 1(d), the insulating film grown by the CVD method is etched in buffered hydrofluoric acid. At this time, in the present invention, when leaving the photoresist 6 on the groove, which does not cause any problem even if excessively etched,
Even if misalignment occurs, it is possible to perform excessive etching so that no insulating material film remains on the diffusion layer.

Next, as shown in FIG. 1 t6), the nitride film 3 is removed,
A silica film 9t is applied over the entire surface of the semiconductor substrate, filling in the recesses at the ends of the grooves caused by etching with buffered hydrofluoric acid, and flattening the surface of the semiconductor substrate. At this time, even if the insulating film 5 is not fully etched, the silica film 9Vc can be used to fill the recess.

After that, the silica film 9 is baked in a steam atmosphere.

The 90 sets of silica films g are set to be the same as the insulating film 5 (for example, an oxide film, a phosphorus glass film, or a boron phosphorus glass film) after baking.

First, as shown in FIG. 1(f), the entire surface of the semiconductor substrate 1t is etched using buffered hydrofluoric acid to remove the thin oxide film 2t on the diffusion layer. Thereafter, a gate oxide film 7 is formed, and impurity 10 is ion-implanted to fully control the threshold voltage of the field effect transistor.

Next, as shown in FIG. 1(g), a material to be a gate electrode is placed on the semiconductor substrate to a length tE, and then patterned to form a gate electrode 11. Next, the source/drain 12 is formed by ion-implanting an impurity having a conductivity type opposite to that of the semiconductor substrate. Thereafter, an interlayer insulating film 13 is grown, a contact hole is opened at a predetermined position, and a gold layer 14 is formed.

In this way, the semiconductor device according to the present invention is manufactured.

(Effects of the Invention) As explained above, the present invention has the following effects when forming a groove-type insulating isolation region between diffusion layers of a field effect semiconductor device.

(1) Since there is no limit to the width of the isolation region4, the degree of freedom in designing the diffusion layer pattern increases.

(2) There is no step difference at the edge of the insulation isolation region, there is no remaining gate electrode forming material during gate electrode formation, or there is no disconnection of the gate electrode.

(3) When removing an insulating film grown by the CVD method on the diffusion layer using buffered hydrofluoric acid, even if excessive etching is performed, steps may be removed by applying the silica film later. Because the process is scaled up, the process margin increases.

(For patterning the photoresist left on the 41 grooves.

By forming grooves and reversing the bright and dark areas of the companion photomask, a photomask with the next pattern is used, which not only simplifies mask pattern design, but also allows the photoresist left on the grooves to extend outward from the groove area. Since it is not necessary to do so, it is possible to shorten the distance between the diffusion layers.

[Brief explanation of drawings]

FIGS. 1(a) to 1(g) are cross-sectional views of a semiconductor device shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
- (d) are cross-sectional views of a semiconductor device shown in the order of steps to explain the first method of trench type insulation isolation of a conventional semiconductor device, and Figures 3 (a) and 3 (b) are cross-sectional views of a conventional semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining a second trench-type insulation isolation method. 1...Semiconductor substrate, 2...Thin oxide film, 3...Nitride film, 4...Channel stopper, 5...Me film (oxide film, phosphorus glass film, or boron phosphorus glass film grown using the CVi method), 6... photo-coated nodist, 7...-
Gate oxide film, 8... Photoresist, 9...
...Silica film, 10...Ion-implanted impurity for threshold control, 11...Cate electrode, 12...Source/drain, 13...
...Interlayer insulating film, 14...Metal wiring. Bud II! I $/WJ Ear 2 Figure

Claims (1)

[Claims] a step of sequentially depositing an oxide film and a nitride film on a surface of a semiconductor substrate; a step of selectively etching the oxide film and the nitride film, and then forming a groove in an insulating isolation region of the semiconductor substrate by anisotropic etching; , a step of depositing an insulating film on the semiconductor substrate by a CVD method, a step of forming a photoresist mask with the same pattern as the groove on the insulating film, and a step of forming a diffusion layer using the photoresist as a mask. a step of removing the insulating film on the target area by isotropic etching, a step of removing the photoresist and the nitride film, and a step of applying a silica film on the entire surface of the semiconductor substrate and removing the insulating film formed by the isotropic etching. a step of baking the silica film, a step of etching the oxide film on the region to become the diffusion layer with buffered hydrofluoric acid, and forming a gate on the region to become the diffusion layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming an oxide film.