JPS6261323A - Formation of ohmic contact - Google Patents

Abstract

PURPOSE:To form fine ohmic contact with high reliability by a method wherein a semiconductor substrate on hole bottoms of an insulating film is selectively processed to form a roughened surface while an external electrode material is brought into contact with a diffused layer through the intermediary of holes. CONSTITUTION:Overall surface of a substrate is coated with a CVD film 15 as an interlayer insulating film; holes 17 for making contact are made; overall surface is thinly coated with photoresist; interference stripe exposure is performed by ultraviolet ray laser using diffraction grating for development to form striped photoresist 19 on the bottom of openings 17 and the surface of CVD films. Next irregularities 20 are formed on the surface of openings 17 by selective reaction etching silicon on the bottom of contact holes 17 using etchant gas with large selection ratio for CVD films 19 and silicon. Successively overall surface is coated with an aluminium film 16 as an external electrode material to form a wiring pattern by specified patterning process finally coating overall surface with a passivation film 21.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for forming an ohmic contact, and in particular to an ohmic contact formation method that can increase the effective contact area between an outer F'jI electrode material and a diffusion layer. The present invention relates to a method of forming a contact.

[Technical background of the invention]

In the manufacturing process of a semiconductor integrated circuit, there is a process of forming an ohmic contact 1- between an expanded RL1 layer formed in a semiconductor substrate and an external electrode material.

Hereinafter, a conventional method of forming an ohmic contact 1- will be described using a silicon gate n-V channel MOS transistor as an example.

FIG. 2 is a dimensional diagram showing the cross-sectional structure of a silicon gate n-channel MOS transistor completed using the conventional A-mic contact formation method. In order to realize such a structure, first, the entire surface of the p-type half-half board 1 is oxidized by about 900 ml.

Next, a nitride film is deposited only on the region where the MO8τ (transistor) is to be formed, and selective oxidation is performed using this nitride film as a mask to form a field oxide film 2 with a thickness of about 1 μm.

Next, the nitride film is removed, and a gate oxide film 7 is formed in the region where a transistor is to be formed. Next, polycrystalline silicon 4 that functions as a gate electrode and wiring is formed on this gate oxide film 7, and phosphorus (P) is dissolved in polycrystalline silicon 4 by leaving it in a phosphorous oxychloride (POCl3) atmosphere for several minutes. to lower the resistance and obtain the desired resistance value.The tU M
Only the polycrystalline silicon that will become the polycrystalline silicon gate and polycrystalline silicon wiring of the OS type transistor is left, and the rest is removed by etching.

Next, the surface of the polycrystalline silicon 4 is oxidized to form a thin oxide film 5, and then arsenic ions are implanted into the intended source/drain regions to form the source/train layer 3. Next, a CVD film 6 is deposited on the entire surface as an insulating interlayer film, and this C
A contact hole is made in the VD film 6, aluminum 8 is deposited as an external electrode material, and a predetermined patterning is performed to form a wiring pattern.

Finally, a passivation film 9 made of phosphosilicate glass (PSG) or the like is deposited on the surface to complete the device. In this way, a silicon gate n-channel MOS transistor as shown in FIG. 2 is completed.

In this way, the aluminum film 8 is brought into contact with the semiconductor substrate surface within the contact hole in the source/drain diffusion layer 3 to form an ohmic contact.

[Problems with background technology]

However, in such an ohmic contact, the following problems arise when high integration is attempted such that the gate length is on the order of submicrons.

The first problem is that the contact area becomes smaller with miniaturization. For example, when the area becomes 1 μm, the contact resistance suddenly increases, making it difficult to downsize.

The second problem is that as the contact area becomes smaller, the current flow in the contact portion becomes higher and chromatography becomes more likely to occur, making it difficult to downsize the device due to reliability issues.

[Purpose of the invention]

The present invention was made in order to eliminate the above-mentioned drawbacks of the prior art, and therefore, it is an object of the present invention to provide a method for forming an ohmic contact that can reduce the contact area and improve reliability at the same time. .

[Summary of the invention]

In order to achieve the above object, the method for forming an ohmic contact according to the present invention includes a first step of forming a hole for contact extraction in an insulating film on an impurity diffusion layer formed in a semiconductor substrate, and a step of forming a hole for taking out the contact. The method includes a second step of selectively processing the bottom surface of the semiconductor substrate to roughen the bottom surface, and a third step of bringing the external electrode material into ohmic contact with the diffusion layer through the hole. This makes it possible to form minute and highly reliable ohmic contacts 1 to 1.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to FIG.

FIGS. 1(a) to 1(e) show cross-sectional views of elements by step when the method of forming an ohmic contact according to the present invention is applied to a method of manufacturing a silicon gate n-channel MOS transistor.

First, the surface of the p-type semiconductor substrate 10 is reduced to about 900 people,
Next, a nitride film is deposited only on the region where the MO8 type transistor is to be formed, and selective oxidation is performed using this nitride film as a mask to form a field oxide film 11 with a thickness of about 1 μm.

Next, the nitride film was removed, and about 500 α0 goo 1 to oxide I
I! 118 is formed. Next, polycrystalline silicon, which is to become a gate electrode and wiring, is deposited on the entire surface and left in a phosphorus oxychloride atmosphere for several minutes to diffuse phosphorus into the polycrystalline silicon and obtain the desired resistance.

Next, polycrystalline silicon gate 1 of MO3 type transistor
3 and polycrystalline silicon, leaving only the polycrystalline silicon that will become the wiring, and removing the rest by etching. By the above step (2), a structure as shown in FIG. 1 (a>) is obtained.

Next, the surface of the polycrystalline silicon gate 13 is oxidized to form a thin oxide film 14, and then arsenic ions are implanted into the intended source/drain regions and heat treatment is performed to form the source/drain regions 12.

Furthermore, a CVD film 15 is formed as an interlayer insulating film over the entire surface of the substrate. As a result, the structure shown in FIG. 1(b) is obtained.

Next, a hole 17 is formed in the CvD film 15 above the source/drain region tfi12 to form a hole 17 for taking out the contact, and then a thin layer of photoresist is applied to the entire surface, and a diffraction grating is formed using an ultraviolet laser (He-Cd). By performing interference fringe exposure (holographic exposure) using the photoresist and developing it, a striped photoresist 19 is formed on the bottom of the opening 17 and on the surface of the CVD film 15, as shown in FIG. 1(C). do.

Next, reactive ion etching (RI) is performed using etching gas having a high selectivity between the CVD film 19 and silicon.
E) selectively etches the silicon on the bottom of the contact hole 17.

At this time, the resist 19 remaining on the bottom surface due to bolographic exposure functions as an etching mask, so
The silicon in the remaining portions of this regimen 1-19 is selectively etched away by RIE.

As a result, as shown in FIG. 1(d), unevenness 20 is formed on the surface of the opening in the source/drain region 12.

Next, an aluminum film 1G was deposited as an external electrode material,
Predetermined patterning is performed to form a wiring pattern.

Finally, apply Badge Beige 3-inch film 21 on the entire surface? ! l! As shown in FIG. 1(e), the silicon gate n-channel M
Complete the OS transformer.

In the ohmic contact formed in this way,
The unevenness 20 on the bottom surface of the opening increases the contact area between the aluminum film and the substrate, reducing the contact resistance. Therefore, the contact hole can be made smaller with the same contact resistance value.

In the above description, an n-channel MOS transistor is used as an example, but a p-channel MOS transistor, 0
The present invention can be applied to semiconductor integrated circuit devices such as MO8 and bipolar.

Furthermore, in the above-mentioned embodiment, in order to form irregularities on the bottom surface of the hole and roughen the surface, holographic exposure using an ultraviolet laser is used to leave the resist. The unevenness can also be formed on the bottom surface of the opening by etching the bottom surface of the opening using the anisotropic wet etching method.

In addition, in order to lower the contact resistance of the contact area and to suppress the precipitation of silicon in the contact area, barrier metal such as chiun nitride is formed into a two-layer structure by sputtering, and metal such as tungsten is applied to the contact opening. Techniques such as embedding are known, but by combining them with the method of forming an ohmic contact according to the present invention, further improvements in characteristics can be realized.

〔Effect of the invention〕

As described above in detail based on the embodiments, according to the present invention, by processing the semiconductor part and providing unevenness on the surface at the contact part between the external electrode material and the semiconductor, effective contact with the external electrode material can be achieved. By enlarging the contact area, the planar contact area is reduced and the contact resistance is lowered, so it is possible to reduce the planar contact area.

Therefore, it is possible to increase the degree of integration of the semiconductor integrated circuit device and to reduce the size of the chip.

Furthermore, since it has the effect of reducing current density while avoiding concentration of current at the contact surface, it is resistant to electromigration and can improve reliability.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device using the method for forming an ohmic contact 1 according to the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device constructed using a conventional method. be. 12... Source-drain diffusion layer, 15... Insulating film,
16... Aluminum layer, 17... Opening, 19...
- Resist remaining in stripes, 20... unevenness on the bottom surface. Applicant's representative FL Fuji -Female-

Claims (1)

[Claims] 1. A first step of forming a hole for contact extraction in an insulating film on an impurity diffusion layer formed in a semiconductor substrate, and selectively processing the semiconductor substrate at the bottom of the hole. A method for forming an ohmic contact, comprising: a second step of roughening the bottom surface by roughening the bottom surface; and a third step of bringing an external electrode material into ohmic contact with the diffusion layer through the hole. 2. The method for forming an ohmic contact according to claim 1, wherein the second step includes selective etching using holographic exposure. 3. The method of forming an ohmic contact according to claim 1, wherein the second step includes anisotropic etching using potassium hydroxide.