JPS61296737A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance element isolation capability through the shield effect (a line of electric force is terminated to a conductive film and is not easily terminated to a semiconductor substrate at the bottom part of groove) by providing a conductive film grounded to the substrate within the groove provided for element isolation. CONSTITUTION:A groove, for example, in the depth of 0.6mum is formed to an element isolating region of a silicon substrate 31 and as a first insulation film, a plasma CVD SiO2 film 32, for example, is deposited in the thickness of 0.2mum. Next, the plasma CVD SiO2 film 32 is patterned in order to expose the substrate 31 at the specified part. Next, as the conductive film, a phosphorus-doped polycrystalline silicon film 33, for example, is left within the groove by the etch back. In this case, the ohmic contact between the substrate 31 and polycrystalline silicon film 33 can be attained at the area where the substrate 31 is exposed, and the polycrystalline silicon film 33 is grounded to the substrate 31. Next, as a second insulation film, the CVD SiO2 film 34, for example, is deposited in the thickness of 2mum on the entire part of it and the surface is flattened. Next, such film is etched by the RIE until the silicon substrate surface of element forming region is exposed, and the entire part of substrate is flattened.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, in which an insulating film is formed in an element isolation region in order to electrically isolate each element on a special semiconductor substrate. The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor device is embedded.

[Technical background of the invention and its problems]

Semiconductor devices using silicon as a semiconductor, especially MO8
In semiconductor devices, a thick oxide film is formed in so-called field regions (element isolation regions) between elements in order to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance.

Conventionally, as an element isolation method using such an oxide film, a method has been used in which a part of the silicon substrate in the field region is etched to form a groove, and a field oxide film is buried in the groove so as to be flat using CVD technology. ing.

The prior art will be briefly explained using FIG. 2. Figure 2 (a
), PM (10
0) A silicon substrate 21 is prepared, and a groove with a depth of, for example, about 0.6 μm is formed in the element isolation region.

Next, as shown in (b)K, an insulating film 22 is uniformly deposited on the surface of the substrate by, for example, an OVD method to a depth comparable to that of the groove. Next, as shown in (C), a surface flattening film 24 capable of flattening the surface is formed.

As the leveling film, for example, a silicon nitride film produced by plasma OVD is used.

Thereafter, as shown in (d), the flattening film 24 and the insulating film 22 are etched from the surface under etching conditions in which the etching speed for both is approximately equal to expose the substrate surface above the element region. The groove in the area is insulating film 2
Embedded in 2.

However, in the above-mentioned conventional method, when the element isolation region is made finer and the width of the groove is narrowed in order to increase the degree of integration, there is a problem that the element isolation ability decreases.

[Purpose of the invention]

The present invention improves the above-mentioned drawbacks of the conventional method, and manufactures a semiconductor device in which a conductive film is provided in a groove for element isolation, and the element isolation ability can be increased by the shielding effect of the conductive film. The purpose is to provide a method.

[Summary of the invention]

According to the present invention, when an insulating film is buried in a groove provided for element isolation, a conductive film is provided at a predetermined position and the conductive film and a semiconductor substrate are electrically connected. After this, an insulating film is further deposited in the same manner as in the conventional method, and the surface is flattened.

〔Effect of the invention〕

According to the present invention, since there is a conductive film grounded to the substrate in the groove provided for element isolation, a shielding effect (electric lines of force terminate at the conductive film and terminate at the semiconductor substrate at the bottom of the groove) ), which improves device isolation capability. Therefore,
The reliability of integrated circuits can be improved.

[Embodiments of the invention]

FIG. 1(a) is a plan view showing one example of a generating conductor device manufactured according to the present invention, and FIG. 1(b) and (C) are
They are sectional views taken along lines X-X' and Y-Y', respectively. A conductive film 3 is embedded in the trench for element isolation.

An embodiment of the present invention will be described below with reference to FIG.

In the figure, (a) to (e) show the xx' cross section in FIG. 1, and [a'] to (e') show the YY' cross section in FIG. 1.

As shown in FIG. 3(a), a P-type (100) silicon substrate 31 with a resistivity of about 5 to 50 Ωα is prepared, a resist is patterned to use it as a mask for etching the element isolation region, and reactive ion etching is performed. A trench with a depth of, for example, 0.6 μm is formed in the element isolation region.

Next, as shown in FIG.
2 to a thickness of 0.2 μm.

Next, the plasma 0VDSiO film 32 is patterned to expose the substrate 31 at a predetermined portion, as shown in FIG. 3(b').

Next, as shown in FIG. 3C, a polycrystalline silicon film 33 doped with phosphorus, for example, as a conductive film is left in the groove using an etch pack. A polycrystalline silicon film 33 is deposited on the entire surface, for example, with a thickness of 0.3 μm, then a resist is deposited to flatten the surface, and then the polycrystalline silicon film 3
3 and the resist are etched from the surface by RIE under etching conditions in which the etching rates for both are substantially equal, leaving the polycrystalline silicon film 33, for example, 0.3 .mu.m thick only in the groove. At this time, as shown in (0-Y), ohmic contact is obtained between the substrate 31 and the polycrystalline silicon film 33 in the part where the substrate 31 was exposed in the step 1 above, and the polycrystalline silicon group 33 is attached to the substrate 31. Grounded.

Next, as shown in FIG. 3(d), as a second insulating film, for example, a 0VDSiOt film 34 is deposited to a thickness of 2 μm over the entire surface.
Flatten the surface.

Next, by etching with RIB until the surface of the silicon substrate in the υ element formation region is exposed, the entire substrate can be flattened as shown in FIG. 3(e). Thereafter, a gate oxide film, source and drain diffusion layers are formed in the element formation region to form a transistor in the same manner as in a normal MO8 type semiconductor device manufacturing process.

According to this embodiment, since the conductive polycrystalline silicon film 33 grounded to the substrate is present in the groove provided for element isolation, the shielding effect and element isolation ability can be improved.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining the element isolation method of the present invention, and FIG.
The figure is a cross-sectional view of a process for explaining a conventional element isolation method, and FIG. 3 is a cross-sectional view of a process for explaining an embodiment of the present invention. In the figure, 1,...21.31...Silicon substrate, 2,22.3
2...OVD 8i0. g, 4.24.34 =-
OVD Sing film. Representative Patent Attorney Noriyuki Chika (and 1 other person) @ 1
Figure 2 Figure 3

Claims (1)

[Claims] A step of etching an element isolation region of a semiconductor substrate to form a groove, a step of forming a first insulating film by leaving a narrow groove in the center of the groove, and a step of patterning the first insulating film to form a groove in the semiconductor substrate. a step of exposing the substrate; a step of embedding a conductive film in the narrow groove at the center of the groove; and a step of making the exposed semiconductor substrate and the conductive film conductive; and a second insulating film in the groove. 1. A method of manufacturing a semiconductor device, comprising the steps of: making the surface substantially flat over the entire substrate buried in the center; and forming an element on the substrate outside the element isolation region.