JPS6257337A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To send an object transmission data to an object district without notifying a faulty communication destination from a sender by transferring a reception data to a standby processor until the fault is released when a data transmission equipment detects a fault of the own processor. CONSTITUTION:When signal lines 504, 510 of a processor fault display register 503 show processor fault, a selection circuit 514 connects signal lines 513, 511 and a selection circuit 508 connects signal lines 507, and 518. Thus, the data on the signal line 513 is outputted to the signal line 511 through the selection circuit 514, a transmission destination address in the reception data is replaced by an address of the standby processor address register 505 and outputted to the signal line 507. The data addressed to the standby processor is inputted to a data transmission line transmission circuit 509 through a signal line 518 and outputted to a signal line 901 from the circuit 509. If the processor 1 is failed, the reception data is transferred to the standby processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data transmission planning in a data transmission system.

(Prior Art) Conventionally, in a data transmission system, for example, an inter-processor network system, when a processor connected via a data transmission path fails, other processors have no means of knowing that the other processor is out of order. When data is generated and sent to the communication partner, there is no response due to the communication partner being out of order. It recognized that there was a processor on the other end of the communication and transferred the data to the backup processor at the other end of the communication.

(Problems to be Solved by the Invention) The conventional inter-processor network system described above has the following problems:
Since communication with the communication partner does not operate until the retry specified in the communication procedure fails, there is a drawback that it takes a long time until the data transfer function to the spare processor is activated. This method has the disadvantage that the sender must have a data transfer function to the backup processor, which complicates communication control at the sender.

[Means for solving problems]

The data transmission device of the present invention has normality/failure information that holds information on the normality/failure of the processing device (processor, terminal device, etc.) connected to the own data transmission device and the bus between the own data transmission device and the processing device. holding means; and preprocessing device address information holding means for holding address information of a preprocessing device to which received data of the data transmission path receiving circuit is transferred when the normality/failure information holding means holds failure information. , when the normality/failure information holding means holds failure information, inputting received data from the data transmission path and address information of the preprocessing device address information holding means to generate data addressed to the preprocessor; The present invention is characterized by comprising means for generating data addressed to the preprocessing device that is output to the data transmission path transmission circuit.

In this way, when the data transmission device detects a failure in its own processing device, it transfers the received data to the preprocessing device until the failure is cleared, thereby ensuring that the sender has no knowledge that the communication partner is out of order. You can send the desired data to the destination without being aware of it.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data transmission device of the present invention, and FIG. 2 is a block diagram of an embodiment of an inter-processor network system configured with the data transmission device of FIG. 1.

This inter-processor network system includes data transmission devices 5 to 8, processors 1 to 4 connected to the data transmission devices 5 to 8, respectively, and data transmission devices 5 to 8.
The transmission line 9 that connects the .

The data transmission device of this embodiment (referring to the data transmission device 15 in FIG. 2, and the others have the same configuration) transmits data sent through the transmission path 9 from other data transmission devices 16 to 8. is received by the signal line 902, and the signal line 513
The data transmission path receiving circuit 512 that sends the data to the top and other data transmission bags M6~ received by the data transmission path receiving circuit 512
Input data from 8 through signal lines 513 and 515,
A processor transmitting circuit 516 transmits data to the processor 1, which is the own processor, through a signal line 517, and a processor receiving circuit 5, which receives data from the processor 1, which is the own processor, through the signal line 501, and transmits it onto the signal line 502.
18 and the data from the processor 1 received by the processor receiving circuit 518 are inputted through signal lines 502 and 519, and transmitted to other data transmission bags M through the signal line 901 and the transmission path 9.
6 to 8, the processor 1 connected to the own data transmission device, and the bus between the own data transmission device and the processor 1 are “0”;
In the case of abnormality (late III), it holds “1” and the signal line 504
．． Processor failure indication register 503 output to 510
and the signal line 510 of the processor failure indication register 503.
A selection circuit 51 that switches the connection of the signal line 513 to the signal line 515 when it is "o" and to the signal line 511 when it is "1".
4, a spare processor address register 505 that holds the address of the spare processor to which data received by the data transmission path receiving circuit 512 is transferred when the processor failure indication register 503 indicates m% failure; When the failure indication register 503 indicates a failure, the data received by the data transmission line receiving circuit 512 is input through the signal line 511, and the destination address in the data is sent to the spare processor held in the spare processor address register 505. When the data generation circuit 506 for the backup processor replaces the address with the address, generates data addressed to the backup processor, and outputs it via the signal line 507, and the signal line 504 of the processor failure indication register 503 is "0", the signal line 502 In the case of “1”, the signal line 51 is connected to the signal line 507.
It is composed of a selection circuit 508 that switches the connections of 8.

Next, the operation of this embodiment will be explained.

Signal line 510°5 of processor failure indication register 503
If 04 is "0" indicating that the processor is normal, the selection circuit 514 connects the signal line 513 and the signal line 515,
The selection circuit 508 connects the signal line 502 and the signal line 519. Therefore, when data is received by the data transmission line receiving circuit 512 through the signal line 902, the data transmission line receiving circuit 512 outputs the data to the signal line 513 if the data is addressed to its own address.

This data is outputted to a signal line 515 through a selection circuit 514, inputted to a processor transmission circuit 516, roughly outputted to a signal line 517, and transferred to the processor 1. On the other hand, when the processor receiving circuit 518 receives data from the processor 1 through the signal line 501, the processor receiving circuit 518 outputs the data to the signal line 502. This data is outputted to the signal line 519 through the selection circuit 508, inputted to the data transmission line transmission circuit 509, and transmitted to the other data transmission devices 6 to 8 via the signal line 901.

Next, the signal line 50 of the processor failure indication register 503
4. If 510 is “1” indicating processor failure,
The selection circuit 514 connects the signal line 513 and the signal line 511, and the selection circuit 508 connects the signal line 507 and the signal line 5.
18 are connected. Therefore, the data on the signal line 513 is output to the signal line 511 through the selection circuit 514,
The backup processor address data generation circuit 506 replaces the destination address in the received data with the address of the backup processor address register 505 and outputs it to the signal line 507. The data addressed to this spare processor is sent to the signal line 51
8 to the data transmission line transmitting circuit 509, and further output from the data transmission line transmitting circuit 509 to the signal line 901. If the processor is out of order, the received data is transferred to the backup processor. be done.

The present invention can also be applied to a data transmission system in which a terminal device or the like other than a processor is used as a processing device.

〔Effect of the invention〕

As explained above, in the present invention, when the data transmission device detects a failure in its own processor, the received data is transferred to the standby processor until the failure is cleared.
This has the effect that the sender can send the intended transmission data to the destination without being aware that the communication partner is out of order.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a data transmission device of the present invention, and FIG. 2 is a configuration diagram of an inter-processor network system. 501, 502.504.507.510.511.5
13.515°517, 519.901.902...
Signal line, 503--Processor failure indication register, 5
05--Spare processor address register, 506
...data generation circuit for backup processor, 508, 51
4... Selection circuit, 509-- Data transmission line transmitting circuit, 512... Data transmission line receiving circuit, 516-... Processor transmitting circuit, 518... Processor receiving circuit, 1.2, 3.4 ... Processor, 5.6, 7.8... Data transmission device, 9... Data transmission path.

Claims (1)

[Scope of Claims] A plurality of data transmission devices that can serve as a transmitter or a receiver, a processing device connected to each of these data transmitters, and a data transmission path for coupling these data transmitters. A data transmission system comprising: a normality/failure information holding means for holding information on normality/failure of a processing device connected to the own data transmission device and a path between the own data transmission device and the processing device; and a normality/failure information holding means. If the means holds failure information, the preprocessor address information holding means holds the address information of the preprocessor to which the received data of the data transmission path receiving circuit is transferred, and the normal/failure information holding means malfunctions. , the received data from the data transmission path and the address information of the preprocessing device address information holding means are input to generate data addressed to the preprocessing device, and the data is output to the data transmission path transmitting circuit. A data transmission device characterized by comprising a data generation means for a preprocessing device.