JPS625643A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an erroneous operation by interposing a cavity in part of a separating range between adjacent wirings to reduce a mutual capacity between the adjacent wirings. CONSTITUTION:A cavity 6 is formed between wirings 3 and 4, and a cavity 7 is formed between wirings 4 and 5. Silicon dioxide film is normally used as a film of insulating substance 2. When the cavity is provided, the capacity between adjacent wirings can be regarded as being series connection of three capacities of capacity between the wiring and the cavity, a capacity of the cavity, and capacity between the cavity and another wirings. Since the capacity of the cavity is approx. 1/4 as compared with the specific dielectric constant of the silicon dioxide film of insulating substance of other portion so that the insulating substance is air of low specific dielectric constant, the capacity between the adjacent wirings is reduced by providing the cavity. Thus, the rate of occupying the mutual capacity between the adjacent wirings in the entire wiring capacity can be suppressed to small value, and an erroneous operation hardly occurs to obtain an integrated circuit having wide operating margin.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits such as semiconductor memories.

[Conventional technology]

Semiconductor integrated circuits have achieved increased capacity and improved performance by reducing their geometric dimensions, and it is expected that this will continue to progress.

If the geometric dimensions are reduced at the same rate in the horizontal and vertical directions, problems such as increased wiring resistance and reduced wiring life due to electromigration will occur. Therefore, a method is generally adopted in which the image is reduced only in the horizontal direction, with almost no reduction in the vertical direction. In the conventional semiconductor integrated circuit wiring shown in FIG. 3, if such reduction continues and the vertical and horizontal dimensions of the wiring cross section become approximately the same, a big problem will arise. This is because the ratio of the mutual capacitance between adjacent wirings to the total wiring capacitance increases at an accelerating rate. Focusing on the central wiring 14 in FIG. 3, the wiring capacitance of the central wiring 14 is the capacitance between it and the semiconductor substrate 11, and
This is the sum of the mutual capacitance between the adjacent wiring 13 and the adjacent wiring 15. In the conventional example, since the wiring and the substrate and the wiring and the wiring are separated by the same insulating material 12, the capacitance ratio is determined approximately by the area of the wiring and the distance between the wirings.

[Problem that the invention seeks to solve]

Therefore, in the method of reducing only the horizontal direction described above, the capacitance between adjacent wirings per unit length increases, but the capacitance per unit length between the wiring and the board decreases. Therefore, the ratio of the capacitance between adjacent light wires to the total wire capacitance increases rapidly.

An increase in the ratio of the mutual capacitance between adjacent wirings to the total wiring capacitance means that they are greatly affected by changes in the potential of adjacent wirings, which reduces operating margins and causes malfunctions, which is detrimental to semiconductor integrated circuits. The condition becomes fatal.

As described above, in conventional semiconductor integrated circuits, when the dimensions are reduced only in the horizontal direction, a problem arises in that information errors are likely to occur due to the dominant mutual capacitance between adjacent wirings.

An object of the present invention is to alleviate the problems of the conventional semiconductor integrated circuit described above, and to provide a semiconductor integrated circuit that can reduce the mutual capacitance between adjacent wirings compared to the conventional example even when the size is reduced only in the horizontal direction. [Means for solving the problem] The present invention is a semiconductor integrated circuit characterized in that a cavity is interposed in a part of the separation region between adjacent wirings.

[For production]

Air with a low dielectric constant in a cavity provided in an insulating material between adjacent wirings is used as an insulating material to prevent an increase in mutual capacitance between adjacent wirings.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to FIG. 1, which shows a typical embodiment of the present invention.

FIG. 1 is a schematic sectional view showing an example in which the present invention is applied to the conventional example shown in FIG. In FIG. 1, a cavity 6 is provided between the wiring 3 and the wiring 4, and a cavity 7 is provided between the wiring 4 and the wiring 5.

Furthermore, as the film made of the insulating material 2, a silicon dioxide film is usually used. If there is a cavity, the capacitance between adjacent wires is the capacitance between the wire and the cavity, and the capacitance of the cavity.

It can be considered that three capacitances, that is, the capacitance between the cavity and the other wiring, are connected in series. The capacitance of the cavity is that the insulating material is air, which has a low dielectric constant, and is approximately 1/4 of the dielectric constant of the silicon dioxide film, which is the insulating material in other parts.
Therefore, by providing a cavity as in the present invention, the capacitance between adjacent wirings is reduced. For example, when the width of the cavity is 173 times the distance between adjacent wirings, the capacitance between adjacent wirings is 1/2 of that without a cavity. The larger the cavity, the smaller the capacitance between adjacent wires. Furthermore, since the capacitance between the wiring and the substrate is approximately constant regardless of the presence or absence of a cavity, the ratio of the capacitance between adjacent wirings to the total wiring capacitance is reduced compared to the conventional configuration. Therefore, potential fluctuations due to mutual capacitance between adjacent wirings are also reduced, and malfunctions are less likely to occur than in the conventional example.
The operating margin becomes wider.

It is easy to form cavities in the insulating material 2 between adjacent wires. In a situation where the mutual capacitance between adjacent wirings is a problem, that is, when the distance between adjacent wirings is small and the wiring film thickness is thick, an insulating material 2 is deposited by the commonly used CVD method after the wiring is formed. As a result, cavities are easily formed. However, in this case, the cavity is formed at a position slightly lifted from the bottom surface of the wiring. As shown in Fig. 1, the cavity 6,
In order to form 7 at a sufficiently deep position, it is necessary to
4. Then, only the insulating material 2 at the bottom between the wirings 3 and 4.5 is slightly etched to form the shape shown in FIG. Just wear it.

〔Effect of the invention〕

As described above, according to the present invention, the proportion of the mutual capacitance between adjacent wirings in the overall wiring capacitance can be suppressed to a small value, and therefore it is possible to obtain a semiconductor integrated circuit that is less likely to malfunction and has a wide operating margin. It has the effect that it can.

[Brief explanation of drawings]

1-4 are schematic cross-sectional views of an embodiment of the present invention, FIG. 2 is an explanatory view of the procedure for forming a cavity, and FIG. 3 is a schematic cross-sectional view of a conventional semiconductor integrated circuit. 1... Semiconductor substrate, 2... Silicon dioxide film (insulating material), 3, 4.5... Wiring, 6, 7... Cavity. Figure 1 Figure 2

Claims (1)

[Claims] (1) A semiconductor integrated circuit characterized in that a cavity is interposed in a part of a separation region between adjacent wirings.