JPS6245129A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6245129A JPS6245129A JP18518085A JP18518085A JPS6245129A JP S6245129 A JPS6245129 A JP S6245129A JP 18518085 A JP18518085 A JP 18518085A JP 18518085 A JP18518085 A JP 18518085A JP S6245129 A JPS6245129 A JP S6245129A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- halogen lamp
- core tube
- substrate
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に半導体基
板表面に薄く緻密な酸化膜を形成する半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a thin and dense oxide film is formed on the surface of a semiconductor substrate.
この発明は、半導体装置を形成する半導体基板の表面に
酸化膜を形成する方法において、酸化性雰囲気中でハロ
ゲンランプ光線を照射することにより、緻密で制御性の
優れた酸化膜を形成するものである。This invention is a method for forming an oxide film on the surface of a semiconductor substrate forming a semiconductor device, in which a dense oxide film with excellent controllability is formed by irradiating halogen lamp light in an oxidizing atmosphere. be.
一般に、MOSメモリー等の半導体装置器こおいては、
ゲート酸化膜等の形成の為、酸化処理が、施されている
。Generally, in semiconductor devices such as MOS memory,
Oxidation treatment is performed to form a gate oxide film and the like.
ここで、従来の酸化膜形成工程について説明すると、第
6図に示すように、酸化処理を施すべき半導体基板11
を石英等の材質のか芯管12因に収納し、所定のガスを
雰囲気としてコイル13の加熱等により加熱する。この
酸化工程の際の加熱時間は、10分間〜20分間程度で
ある。Here, to explain the conventional oxide film forming process, as shown in FIG. 6, a semiconductor substrate 11 to be oxidized is
is housed in a core tube 12 made of a material such as quartz, and heated by a coil 13 or the like in a predetermined gas atmosphere. The heating time during this oxidation step is about 10 minutes to 20 minutes.
最近のMOSメモリーは微細化が進め、スケーリング則
に従ってゲート酸化膜等は薄くなってきている。例えば
、256にビットのDRAMでの酸化膜の膜厚は100
人〜120人であり、IMヒ゛ノドのDRAMでは80
人〜100人が必要になる。また、SRAMについても
同様に200Å以下が要求され、1MビットのSRAM
では150A以下が要求されている。Recent MOS memories are becoming increasingly finer, and gate oxide films and the like are becoming thinner in accordance with the scaling law. For example, the thickness of the oxide film in a DRAM with 256 bits is 100 mm.
~120 people, and 80 for IM Hinode DRAM
~100 people will be required. Similarly, 200 Å or less is required for SRAM, and 1M bit SRAM
150A or less is required.
更に、このような薄膜化の要求に加えて、酸化膜に良質
さが求められている。即ち、不純物等の悪影響のない酸
化膜を形成することが、トランジスタ等の素子の高性能
化につながる。Furthermore, in addition to the demand for thinner films, there is also a demand for higher quality oxide films. That is, forming an oxide film free from the adverse effects of impurities and the like leads to higher performance of elements such as transistors.
しかしながら、従来の酸化膜形成方法では、上記要求に
必ずしも対応できない。従来の酸化方法では、厚い酸化
膜を形成することは容易であるが、上述のような薄膜の
酸化膜を形成するには制御性に困難が伴う。すなわち、
酸化処理には、制御性を得るために10分間〜20分間
程度の時間が必要であり、薄い酸化膜を形成するために
酸化時間を短くした場合には、酸化膜厚にばらつきが生
ずる等の問題を生ずる。これに対して、酸化速度を低く
して酸化を行う方法も知られているが、例えば酸化速度
をIO人/min程度以下の酸化速度を実現するため、
実効的な酸素分圧をさげた低圧酸化法や低温の酸化法等
を用いた場合にも、同様に酸化膜厚の制御性に問題が有
り、更に、工程も複雑である。また、時間もなるべく短
時間である方が、プロセス上メリットが大きい。However, conventional oxide film forming methods cannot necessarily meet the above requirements. With conventional oxidation methods, it is easy to form a thick oxide film, but it is difficult to control the formation of a thin oxide film as described above. That is,
The oxidation process requires about 10 to 20 minutes to obtain controllability, and if the oxidation time is shortened to form a thin oxide film, there may be problems such as variations in the oxide film thickness. cause problems. On the other hand, there are also known methods of performing oxidation at a lower oxidation rate.
Even when a low-pressure oxidation method or a low-temperature oxidation method that lowers the effective oxygen partial pressure is used, there are similar problems in controllability of the oxide film thickness, and furthermore, the process is complicated. Further, the shorter the time possible, the greater the advantage in terms of the process.
更に、この従来の酸化膜形成の方法の場合には、緻密性
の問題から界面準位、耐圧等の低下が懸念される。Furthermore, in the case of this conventional method of forming an oxide film, there is a concern that the interface state, breakdown voltage, etc. may decrease due to the problem of density.
例えば従来の酸化膜形成方法は、コイル加熱等により加
熱して行われるが、同時に炉芯管も加熱される。このた
め外部より或いは内壁からの不純物(例えば、H20,
Na、に等)が、該炉芯管内の雰囲気中に混入し、酸化
膜の形成の際には、この不純物が酸化膜に取り込まれて
、膜質に悪影響を及ぼすことになる。For example, in the conventional oxide film forming method, heating is performed using coil heating or the like, and the furnace core tube is also heated at the same time. Therefore, impurities from the outside or from the inner wall (for example, H20,
(Na, etc.) are mixed into the atmosphere inside the furnace core tube, and when an oxide film is formed, these impurities are taken into the oxide film and have an adverse effect on the film quality.
そこで、本発明は上述の問題点に鑑み、短時間で熱処理
を行い、しかも、半導体装置の微細化に対応して、薄膜
の酸化膜を制御性良く形成し、かつ不純物の炉内雰囲気
への拡散等の弊害の生じない半導体装置の製造方法を提
供することを目的とする。In view of the above-mentioned problems, the present invention performs heat treatment in a short time, forms a thin oxide film with good controllability in response to the miniaturization of semiconductor devices, and prevents impurities from entering the furnace atmosphere. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not cause harmful effects such as diffusion.
本発明は、酸化性雰囲気中で半導体基板にハロゲンラン
プ光線を照射して、上記半導体基板表面に酸化膜を形成
する半導体装置の製造方法により上述の問題点を解決す
る。The present invention solves the above-mentioned problems by using a method for manufacturing a semiconductor device in which a semiconductor substrate is irradiated with halogen lamp light in an oxidizing atmosphere to form an oxide film on the surface of the semiconductor substrate.
酸化性雰囲気中で半ぶ体裁板に、ハロゲンランプ光線を
照射する。このためハロゲンランプ光線の加熱性能から
、約10〜20秒程度の短時間で熱処理をすることがで
きる。酸化性雰囲気は、例えばドライ02. ウェッ
ト02.スチーム02゜03 (オゾン)、N2±0
2.ドライエアー等によって行われる。高温短時間のた
め、膜質の優れた酸化シリコン膜を膜厚の制御性良く形
成することができる。A halogen lamp beam is irradiated onto the half-shaped display board in an oxidizing atmosphere. Therefore, due to the heating performance of the halogen lamp beam, the heat treatment can be carried out in a short time of about 10 to 20 seconds. The oxidizing atmosphere is, for example, Dry 02. Wet 02. Steam 02゜03 (ozone), N2±0
2. This is done using dry air, etc. Because of the high temperature and short time, a silicon oxide film with excellent film quality can be formed with good controllability of film thickness.
また、第1図の模式図に示すように、このハロゲンラン
プ光線の波長の分布D1は、0.4μm〜4.0μmの
範囲に存る。ここで、炉芯管は石英等の材料で造られて
おり、光吸収係数αの波長依存性から0.4μm〜4.
0μmの範囲では、石英すなわち酸化シリコンの光吸収
係数α0の値は小さい。従って、ハロゲンランプ光線で
照射した場合には、炉芯管の加熱を抑えることができ、
炉芯管の温度を低くすることが可能なため、外部より或
いは内壁からの不純物(例えば、H2O。Further, as shown in the schematic diagram of FIG. 1, the wavelength distribution D1 of the halogen lamp light is in the range of 0.4 μm to 4.0 μm. Here, the furnace core tube is made of a material such as quartz, and from the wavelength dependence of the light absorption coefficient α, it is 0.4 μm to 4.0 μm.
In the range of 0 μm, the value of the light absorption coefficient α0 of quartz, that is, silicon oxide is small. Therefore, when irradiated with halogen lamp light, heating of the furnace core tube can be suppressed.
Since it is possible to lower the temperature of the furnace core tube, impurities (such as H2O) from the outside or from the inner wall.
Na、に、 A*等)の炉内への混入を抑えて悪影響を
防止することができる。更に、光の波長が2゜5μm以
下の範囲では、炉芯管の材料である酸化シリコンへの吸
収は少なくなる。このため波長を0.25μm以下の範
囲で照射するような光源を用いて照射することにより、
不純物の炉芯管内への混入を抑えることができる。It is possible to suppress the incorporation of Na, A*, etc.) into the furnace and prevent adverse effects. Furthermore, when the wavelength of light is in the range of 2.5 μm or less, absorption by silicon oxide, which is the material of the furnace core tube, decreases. Therefore, by irradiating with a light source that emits wavelengths in the range of 0.25 μm or less,
It is possible to prevent impurities from entering the furnace core tube.
一方、半導体基板として例えばシリコン基板を用イた場
合には、シリコンの0.4μm〜4.0μmの範囲での
光吸収係数α1が大きくシリコン基板は効率良く加熱さ
れる。このように酸化シリコンとシリコンとの光吸収係
数αの波長依存性から、ハロゲンランプ光線を用いた場
合には、炉芯管に吸収されず半導体基板にのみ有効に吸
収されることになる。従って、短時間で効率良く熱処理
され、しかも、不純物の混入等の悪影響を防止すること
ができる。On the other hand, when a silicon substrate, for example, is used as the semiconductor substrate, the silicon substrate has a large light absorption coefficient α1 in the range of 0.4 μm to 4.0 μm, and the silicon substrate is efficiently heated. As described above, due to the wavelength dependence of the light absorption coefficient α of silicon oxide and silicon, when a halogen lamp light beam is used, the light is not absorbed by the furnace core tube but is effectively absorbed only by the semiconductor substrate. Therefore, heat treatment can be carried out efficiently in a short time, and moreover, adverse effects such as contamination with impurities can be prevented.
本発明の好適な実施例を実験例に基づき説明する。 Preferred embodiments of the present invention will be described based on experimental examples.
先ず、照射を行う装置について、第5図を参照しながら
説明すると、ハロゲンランプ装置3は、半導体素子を形
成するシリコン基板lを内部に載置してなる石英で形成
された炉芯管2の外側上下に配されている。このハロゲ
ンランプ装置1には、波長0.4〜4.0μmの連続的
インコヒーレン)・光を射出する複数本のハロゲンラン
プ4が取り付けられ、各ハロゲンランプ4には、放物線
反射鏡5がそれぞれ取り付けられている。上記シリコン
基板1は、枠状のサスペンダ6によって中空に支持され
、シリコン基板1の両生面には、各ハロゲンランプ4か
らの連続的インコヒーレント光が照射されるようになっ
ている。First, the irradiation device will be explained with reference to FIG. 5. The halogen lamp device 3 consists of a furnace core tube 2 made of quartz, in which a silicon substrate l forming a semiconductor element is placed. They are placed on the top and bottom of the outside. This halogen lamp device 1 is equipped with a plurality of halogen lamps 4 that emit continuous incoherent light with a wavelength of 0.4 to 4.0 μm, and each halogen lamp 4 is equipped with a parabolic reflecting mirror 5. installed. The silicon substrate 1 is supported in the air by frame-shaped suspenders 6, and the bidirectional surfaces of the silicon substrate 1 are irradiated with continuous incoherent light from each halogen lamp 4.
このハロゲンランプ装置3を用いて酸化膜形成を行った
場合は、第1図に示すシリコン基板1と炉芯管2の光吸
収率αの相違から、炉芯管2は加熱されず所謂コールド
ウオールに保たれ、一方、シリコン基板1は高温で短時
間に加熱されることになる。そして、炉芯管2が低温に
維持されるため、該炉芯管2内への不純物の混入を抑え
て、良質な酸化膜を形成することができる。When forming an oxide film using this halogen lamp device 3, the furnace core tube 2 is not heated due to the difference in light absorption rate α between the silicon substrate 1 and the furnace core tube 2 shown in FIG. 1, resulting in a so-called cold wall. On the other hand, the silicon substrate 1 is heated at a high temperature in a short time. Since the furnace core tube 2 is maintained at a low temperature, it is possible to prevent impurities from entering the furnace core tube 2 and form a high-quality oxide film.
本発明者らは、このような装置を用いて、薄い酸化膜の
形成の実験を行った。即ち、シリコン基板(CZ (1
00) ;n−type、 2〜3ohm−cm)を使
用し、酸化性雰囲気としてドライ02雰囲気中でハロゲ
ンランプ4による赤外線照射加熱を行った。この実験の
実験データを第1表に示す。The present inventors conducted an experiment on forming a thin oxide film using such an apparatus. That is, silicon substrate (CZ (1
00) ; n-type, 2 to 3 ohm-cm), and infrared irradiation heating was performed with a halogen lamp 4 in a dry 02 atmosphere as an oxidizing atmosphere. The experimental data for this experiment is shown in Table 1.
(以下、余白)
第1表
この実験データに基づきグラフ化したのが第2図〜第3
図である。第2図に示すように、従来の酸化方法による
データ(第2回中、右」二がりの4本の直線で示してい
る。)と比較して、本実施例による酸化膜の形成(第2
図中、○で示す。)は、従来の酸化膜形成の直線上にあ
り、このことから短時間に同様の酸化膜が形成されてい
ることが判り、ハロゲンランプ光による酸化膜形成の妥
当性が示される。尚、第2図では縦軸に酸化膜厚(人)
をとり、横軸に酸化時間(秒および分)をとっている。(Hereinafter in the margin) Table 1 Figures 2 to 3 are graphs based on this experimental data.
It is a diagram. As shown in FIG. 2, compared with the data obtained by the conventional oxidation method (indicated by four straight lines on the right side in the second section), the formation of the oxide film according to this example 2
Indicated by ○ in the figure. ) is on the straight line of conventional oxide film formation, and this shows that a similar oxide film was formed in a short time, demonstrating the validity of oxide film formation using halogen lamp light. In Figure 2, the vertical axis represents the oxide film thickness (person).
The horizontal axis shows the oxidation time (seconds and minutes).
また、第3図に示すように、酸化温度と酸化膜厚の関係
は、直線型な関係になる。このため酸化温度の上昇と共
に酸化膜厚も厚くなり、所定の温度を酸化処理を行えば
、所定の膜厚の酸化膜を形成することができる。Further, as shown in FIG. 3, the relationship between the oxidation temperature and the oxide film thickness is a linear relationship. Therefore, as the oxidation temperature increases, the oxide film thickness also increases, and by performing oxidation treatment at a predetermined temperature, an oxide film with a predetermined thickness can be formed.
このように、ハロゲンランプ光線(0,4〜(1゜0μ
m、ピーク波長1.15.+1m)を使用し、酸化性雰
囲気中で酸化を行った場合には、1o人オーダーでの膜
厚の制御が可能であり、50〜150人の薄い酸化膜を
制御性良く容易に形成することができる。そして、上述
したように、炉芯管2が加熱されずコールドウオール状
態であるため、不純物の拡散を抑えることができ、しか
も高温であるため緻密で良質の酸化膜を容易に形成す゛
ることができる。In this way, the halogen lamp light (0.4~(1°0μ
m, peak wavelength 1.15. +1m) and oxidation is performed in an oxidizing atmosphere, it is possible to control the film thickness on the order of 10 people, and it is possible to easily form a thin oxide film of 50 to 150 people with good controllability. I can do it. As mentioned above, since the furnace core tube 2 is not heated and is in a cold wall state, diffusion of impurities can be suppressed, and since the temperature is high, a dense and high-quality oxide film can be easily formed. .
ところで、一般に、シリコン基板等の半導体基板に高温
度の不純物が導入されると、形成する酸化膜の膜厚が大
きくなる所謂増速酸化効果が知られている。Incidentally, it is generally known that when high-temperature impurities are introduced into a semiconductor substrate such as a silicon substrate, the so-called accelerated oxidation effect increases the thickness of the formed oxide film.
そこで、本実施例の半導体装置の製造方法による増速酸
化効果について、上述した実施例と同様に本発明者が行
った実験(50keVでBF2+をイオン注入したシリ
コン基板に1000℃、20分でアニールを施した後、
1150℃、10秒。Therefore, in order to determine the accelerated oxidation effect of the semiconductor device manufacturing method of this example, the present inventor conducted an experiment similar to the above-mentioned example (annealing a silicon substrate into which BF2+ was ion-implanted at 50 keV at 1000°C for 20 minutes). After applying
1150℃, 10 seconds.
ドライo2 ;4β/分の条件で酸化し、酸化膜厚を測
定する。)に基づき説明すると、第4図に示すように、
本実施例の半導体装置の製造方法を用いた場合には、少
なくともlX1013〜2×1015/cIAの範囲で
は一定の酸化膜厚が得られ、酸化膜が再現性、制御性良
く形成されることを示している。Oxidize under the conditions of dry O2: 4β/min and measure the oxide film thickness. ), as shown in Figure 4,
When the semiconductor device manufacturing method of this example is used, a constant oxide film thickness can be obtained at least in the range of lX1013 to 2x1015/cIA, and the oxide film can be formed with good reproducibility and controllability. It shows.
従って、本実施例の半導体装置の製造方法は、不純物が
導入されたシリコン基板等の半導体基板に対しても有効
であり、制御性よく薄い酸化膜を短時間に形成すること
ができる。Therefore, the method for manufacturing a semiconductor device of this embodiment is also effective for semiconductor substrates such as silicon substrates into which impurities are introduced, and a thin oxide film can be formed with good controllability in a short time.
本発明の半導体装置の製造方法は、半導体装置の高集積
化、微細化に対応して、薄い酸化膜を容易に形成するこ
とができるものである。即ち、本発明の半導体装置の製
造方法は、酸化性雰囲気中でハロゲンランプ光線で照射
するため、短時間で高温の加熱をすることができる。ま
た、半導体基板と炉芯管との光吸収の差から、半導体基
板のみを加熱することができ、炉芯管内への不純物の混
入を抑えることができる。従って、薄膜の酸化膜を短時
間に制御性よく形成することができ、また、不純物の拡
散等が防止されてなるため、界面特性等の優れた良質な
酸化膜を容易に形成することが可能である。The method for manufacturing a semiconductor device of the present invention can easily form a thin oxide film in response to higher integration and miniaturization of semiconductor devices. That is, in the method for manufacturing a semiconductor device of the present invention, since the semiconductor device is irradiated with halogen lamp light in an oxidizing atmosphere, it is possible to heat the semiconductor device to a high temperature in a short time. Further, due to the difference in light absorption between the semiconductor substrate and the furnace core tube, only the semiconductor substrate can be heated, and it is possible to prevent impurities from entering the furnace core tube. Therefore, a thin oxide film can be formed in a short time with good control, and since diffusion of impurities is prevented, it is possible to easily form a high-quality oxide film with excellent interfacial properties. It is.
第1図はハロゲンランプ光線の波長の分布とSi及び5
i02の光吸収の波長依存性を示す模式図であり、第2
図は従来の酸化膜厚の時間依存性と本発明の半導体基板
の製造方法を用いた場合の酸化膜厚の時間依存性を示す
特性図であり、第3図は本発明に係る酸化温度と酸化膜
厚の関係を示す特性図であり、第4図は本発明に係るシ
リコン基板に不純物を導入した場合の酸化膜厚の変化を
示す特性図であり、第5図は本発明の半導体装置の製造
方法に用いられるハロゲンランプ装置の一例を示す概略
断面図であり、第6図は従来の酸化膜形成方法に用いら
れる装置の一例を示す概略断面図である。
1・・・半導体基板
2・・・炉芯管
3・・・ハロゲンランプ装置
4・・・ハロゲンランプ
特 許 出 願 人 ソニー株式会社代理人 弁
理士 小泡 見間 田村榮−
″ 謡かド←
一一埠寥鯖
一一斗婆受Figure 1 shows the wavelength distribution of halogen lamp light and Si and 5
FIG. 2 is a schematic diagram showing the wavelength dependence of optical absorption of i02;
The figure is a characteristic diagram showing the time dependence of the oxide film thickness in the conventional method and the time dependence of the oxide film thickness in the case of using the method of manufacturing a semiconductor substrate of the present invention. FIG. 4 is a characteristic diagram showing the relationship between oxide film thickness, FIG. 4 is a characteristic diagram showing the change in oxide film thickness when impurities are introduced into the silicon substrate according to the present invention, and FIG. FIG. 6 is a schematic cross-sectional view showing an example of a halogen lamp device used in the manufacturing method of FIG. 1...Semiconductor substrate 2...Furnace core tube 3...Halogen lamp device 4...Halogen lamp patent applicant Sony Corporation representative Patent attorney Koba Mima Tamura Sakae - `` Utaka Do← Ichitoba-saba Ichitoba-uke
Claims (1)
射して、上記半導体基板表面に酸化膜を形成する半導体
装置の製造方法。A method of manufacturing a semiconductor device, which comprises irradiating a semiconductor substrate with halogen lamp light in an oxidizing atmosphere to form an oxide film on the surface of the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18518085A JPS6245129A (en) | 1985-08-23 | 1985-08-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18518085A JPS6245129A (en) | 1985-08-23 | 1985-08-23 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6245129A true JPS6245129A (en) | 1987-02-27 |
Family
ID=16166238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18518085A Pending JPS6245129A (en) | 1985-08-23 | 1985-08-23 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6245129A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6288328A (en) * | 1985-10-15 | 1987-04-22 | Nec Corp | Manufacture of semiconductor device |
JPS63224234A (en) * | 1987-03-13 | 1988-09-19 | Nippon Denso Co Ltd | Production of insulator thin film |
US5017979A (en) * | 1989-04-28 | 1991-05-21 | Nippondenso Co., Ltd. | EEPROM semiconductor memory device |
JPH0766426A (en) * | 1993-08-27 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its forming method |
JPH0794756A (en) * | 1993-07-27 | 1995-04-07 | Semiconductor Energy Lab Co Ltd | Method of fabricating semiconductor device |
US5966594A (en) * | 1993-07-27 | 1999-10-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6373093B2 (en) | 1989-04-28 | 2002-04-16 | Nippondenso Corporation | Semiconductor memory device and method of manufacturing the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59147434A (en) * | 1983-02-10 | 1984-08-23 | Mitsui Toatsu Chem Inc | Formation of silicon oxide film |
JPS59147435A (en) * | 1983-02-10 | 1984-08-23 | Mitsui Toatsu Chem Inc | Formation of silicon oxide film |
JPS6031230A (en) * | 1983-08-01 | 1985-02-18 | Nec Corp | Forming method for thin film |
-
1985
- 1985-08-23 JP JP18518085A patent/JPS6245129A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59147434A (en) * | 1983-02-10 | 1984-08-23 | Mitsui Toatsu Chem Inc | Formation of silicon oxide film |
JPS59147435A (en) * | 1983-02-10 | 1984-08-23 | Mitsui Toatsu Chem Inc | Formation of silicon oxide film |
JPS6031230A (en) * | 1983-08-01 | 1985-02-18 | Nec Corp | Forming method for thin film |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6288328A (en) * | 1985-10-15 | 1987-04-22 | Nec Corp | Manufacture of semiconductor device |
JPS63224234A (en) * | 1987-03-13 | 1988-09-19 | Nippon Denso Co Ltd | Production of insulator thin film |
US5017979A (en) * | 1989-04-28 | 1991-05-21 | Nippondenso Co., Ltd. | EEPROM semiconductor memory device |
US6365458B1 (en) | 1989-04-28 | 2002-04-02 | Nippondenso Co., Ltd. | Semiconductor memory device and method of manufacturing the same |
US6373093B2 (en) | 1989-04-28 | 2002-04-16 | Nippondenso Corporation | Semiconductor memory device and method of manufacturing the same |
US6525400B2 (en) | 1989-04-28 | 2003-02-25 | Denso Corporation | Semiconductor memory device and method of manufacturing the same |
JPH0794756A (en) * | 1993-07-27 | 1995-04-07 | Semiconductor Energy Lab Co Ltd | Method of fabricating semiconductor device |
US5966594A (en) * | 1993-07-27 | 1999-10-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6210997B1 (en) | 1993-07-27 | 2001-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6465284B2 (en) | 1993-07-27 | 2002-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JPH0766426A (en) * | 1993-08-27 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its forming method |
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