JPS624030B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In a data transmission system, a failure may occur in a part of the system, such as a terminal device, a modem, or a line. In such a case, it is necessary to investigate where in the system the failure occurred. This invention configures a loop circuit in the modem of a remote terminal (hereinafter referred to as the terminal under test) so that one terminal (hereinafter referred to as the test terminal) can search for such failures in the system. The present invention relates to a method for performing tests by returning signals, and particularly to a loop configuration circuit of a data transmission system that configures the loop.

As a method to configure a loop on the terminal under test,
A method in which a test terminal transmits a carrier wave intermittently and the terminal under test detects the number of intermittent waves to form a loop; and a method in which the test terminal transmits a code and the terminal under test identifies the code to form a loop. There is. The present invention belongs to the latter category.

The code that a test terminal sends to a terminal under test to configure a loop is generally a loop configuration code that notifies the terminal under test to configure a loop, and a code that sends a code to a terminal under test when there are many terminals under test, such as in a multi-drop system. There is an address code that specifies the test terminal, and a mode code that indicates the type of loop that the tested terminal forms, and depending on the system, all codes may be used, or two types of codes may be used. There are cases. Types of loops include loops that loop the input signal of the device under test to the output without passing through its internal functions, loops that loop the output signal back to the input, and loops that loop the signal after passing through some functions of the device under test. Loops that wrap internally to other function inputs are known. Conventionally, the following codes were used.

The loop constituent code is 0 or 1 of a certain generator polynomial.
The scramble signal a _{was 1} bit, the address code was a code of about 1 to 8 bits depending on the number of addresses specified, and the mode code was also a code created in the same way as the address code.

The terminal under test constituted a loop by continuously detecting a ₂ bits (a ₁ ≧a ₂ ≧2), an address code, and a mode code.

Generally, when a test terminal performs a test by making a loop configuration with the terminal under test, it is a case where data transmission is not normal and a failure has occurred in the system, so there is no guarantee that all codes will be transmitted and received.

With the conventional method, for example, the following errors occur due to the above reasons. For example, the number of terminals under test is 4,
If the type of loop is 2, the address code will be 2 bits (4 addresses 00, 01, 11, 10) and the mode code will be 1 bit (2 digits 0, 1), and the loop configuration code a ₁ as shown in Figure 1A. Suppose that these signals are transmitted after the bits are transmitted. Assume that a _1- bit error occurs after the terminal under test detects A2 bits out of _A1 bits, as shown in FIG. 1B. In this case, the address code or mode code will be detected incorrectly and the device will not operate normally. If a ₂ is small, the signal during data transmission is erroneous as a loop configuration code, and if a ₁ = a ₂ , if there are many errors, loop configuration will not be possible.

The present invention provides a new loop configuration circuit for a data transmission system that eliminates the above drawbacks.

The present invention adopts a method of independently detecting a loop configuration code, an address code, and a mode code, and will be described below with reference to the drawings.

FIG. 2 is a time chart showing the circuit operation of the present invention. Figure 2A shows the code transmitted from the test terminal, where _a1 is the number of bits of the loop constituent code, a scramble signal of 0 or 1 of a certain generator polynomial, and _b1 is the number of bits of the address code, which is the same as that of other codes. A 0 or 1 scramble signal of the generator polynomial, _c1 is the number of bits of the mode code, which is a 0 or 1 scramble signal of another generator polynomial. Figure 2 (b) shows the code that the terminal under test detected from the transmission code in (a), and a ₃ , b ₃ , and c ₃ are the numbers of bits that were correctly detected consecutively among a ₁ , b ₁ , and c ₁ .

Assuming that a loop is formed when the terminal under test correctly detects the loop configuration code ₍ a), address code (b), mode code ( _b ), mode code (c), _{2 or more bits (c), and more than 2} bits consecutively, then a ₃ ≧a ₂ , b ₃ ≧b ₂ , c ₃ ≧ c ₂ , the terminal under test can correctly configure the loop. Furthermore, if each signal correctly detects 3 bits a ₃ , b ₃ , and _c of each signal, a loop can be formed.

FIG. 3 shows an embodiment of the transmitting section of the present invention, and FIG. 4 is a time chart thereof. In FIG. 3, 301 is a transmission data input terminal, 302 is a timing signal input terminal, 303 is a control signal input terminal for configuring a loop, 304 is a transmission data output terminal, 305 and 306 are control circuits, and 3050
1, 30502, 30601 to 3060n-2 are switches, 307 is a selector circuit, 30701,
30702 is a selector, 308 is a selector circuit,
30801 is a selector, 309 is a scrambler circuit, 30901 and 30902 are exclusive OR circuits, 30903 to 3090n are shift registers, 310 is a gate circuit, 310101 to 3
1010n-3, 310201 to 310205 are NOR circuits, and 311 is a control signal generation circuit.

The embodiment of the present invention uses 1 as the loop constituent code.
+X ^-m +X ^-n 0 scramble signal, 1+X ^-1 +X ^-n 0 scramble signal as address code (1 excluding 1+X ^-m +X ^-n and 1+X ^-l +X ^-n)
+X ^-1 +X ^-n , ..., ^{1 +} The address is 0 scramble of ^-1 +X ^-n . ) ^, 1 scramble of 1 ⁺ X ^{-l +} It is set at 30501 of 305. It is obvious that if other codes are added, the address side will be reduced by that number.)
This is an example where it is set to .

In addition, if many systems use one test terminal, the address code can be further reduced by increasing the loop constituent code, for example, by using 506 and 1 scramble of 1 + X ^{- m} + X ^{- n} , and further using the generator polynomial. However, here, a case is shown in which the receiving section, which will be described later, uses 0 scrambling of 1+X ^-m +X ^-n . With it set like this,
First, go to 303 by means of a switch or the like as shown in Fig. 4 1.
By applying a signal such as , a loop configuration code, an address code, and a code indicating the type of loop are outputted to 304 via 308 as described below.

This signal reaches the receiver in some form.
(For example, if a modem is used, modulation and demodulation are performed.) As will be described in detail later, this signal is input to the receiving section 501. The address of the receiving section is set at 508 to 0 scramble of 1+X ^-1 +X ^-n . A signal indicating the type of one scramble loop of 1+X ^-l +X ^-n is output to 504 .

When not transmitting the loop configuration signal, the control signal generation circuit 311 controls the selector circuit 308 and causes the selector circuit 308 to output the input signal from the input terminal 301 to the output terminal 304. In order to form a loop, a signal is applied to the input terminal 303 as shown in FIG. 4. The control signal generation circuit 311 is 310
204 and 30702, 3102
4 on 03, 310202 and 3070
A signal shown in FIG. 4 is given to 1 and 30801 is given a signal shown in FIG. In this case, the signal from 305 passes through 30702 and enters 309 as shown in FIG.
The gate of 04 opens, the 0 scramble signal of the loop constituent code generating polynomial 1+X ^-m +X ^-n is a ₁ bit, then the signal from 306 is
Enter 309 via 0702 and enter 310207
gate opens, and the address code generator polynomial 1+
1 scramble signal of X ^-1 +X ^-n is b ₁ bit, then the signal indicated by 30501 from 305 is 307
Enter 309 via 01,30702 and enter 31
The gate of 0203 is opened and the scrambler signal c ₁ bit of the signal mode code generator polynomial 1+X ^-l +X ^-n set in 305 is passed through 308 to 304.
output to the output terminal.

Therefore, it is possible to transmit a ₁ , b ₁ , and c ₁ bits of the loop configuration code, address code, and mote code, respectively.

FIG. 5 shows an embodiment of the receiving section of the present invention, and FIG. 6 is a time chart thereof.

In FIG. 5, 501 is a received data input terminal, 502 is a timing signal input terminal, 503 is a loop clear signal input terminal, 504 and 505 are output terminals for signals for loop configuration types 1 and 2, and 506 is a descrambler circuit. ,5060
1,50602 is an exclusive OR circuit,
50603 to 5060n+1 are shift registers,
507 is a clear signal generation circuit, 50701, 50
704-50706 are shift registers, 5070
2 is an exclusive OR circuit, 50703 is an OR circuit, 50707 to 50710 are NAND circuits, 508 is a control circuit, 50801 to 5080n
-2 is the switch, 509 is the gate circuit, 5091
01~50910n-3, 509201~509
205 is a NOR circuit, 510 is a gate signal generation circuit, 51001 is an AND circuit, 51002, 51
003 is a NAND circuit, 51004 is a NOR circuit, 5
1005 and 51006 are inverting circuits; 511 is a timer composed of a shift register, a counter, and a logic circuit; 512 is a loop configuration signal generation circuit; 51
201, 51202 are NAND circuits, 51203,
51204 is an inverting circuit, 51205 to 51207
is a Noah circuit, 51208-51211, 5121
6 is an OR circuit, 51212 to 51215 are shift registers, 513 is a loop configuration release signal generation circuit, 51301 is an inversion circuit, 51302 is a NAND circuit, 51303 is a shift register, a counter,
A timer 51304 composed of a logic circuit is an OR circuit.

The loop configuration release signal generation circuit 513 receives the loop configuration code and sends 1 from 51212 to 51302.
If a signal is given and no loop type signal is received, 51303 counts for a certain period of time,
The loop is released by applying one signal pulse (FIG. 6) to 51304. Also, when a loop type signal is received, a 512161 signal is input, and a 513
A signal is given to 51304 to clear the above-mentioned counter, and after a certain period of time has elapsed, the counter starts counting again. 503 releases the loop by applying the signal shown in FIG. 6 from the outside when the loop is desired to be released. Loop configuration signal generation circuit 5
12 receives the loop configuration code, address code, and code indicating the type of loop from 506 and 511;
51212, 51213 and 51214 or 51215 output respective signals.

The timer 511 receives the loop configuration code 0 from 50703 and counts a ₂ bits to 51202.
1 signal is output to 51001, and the polarities of the signal shown in FIG. Next 5070
Get address code 0 (or 1, 0 in this circuit) from 3, count b ₂ , output to 512,
Reverse the polarity of 1003 and 51002 (6th
Figures 5 and 6) Set the state to receive a code indicating the type of loop. Similarly, count c ₂ bits and 5
Reverse the polarity of 1002. That is, 511 is
This is a timer for a ₂ , b ₂ , and c ₂ . 510 is a gate signal generation circuit that causes the timer 511 to count the loop configuration code, address code, and code indicating the type of loop;
Drives a circuit that creates a generator polynomial of 9. The clear signal generating circuit 507 receives a continuous 1 or 0 signal from the signal 506, drives the timer 511 with a 0 code, and clears the timer 511 with a 1 code. In other words, if 0 or 1 from 506 is not consecutive,
and loop configuration code, address code, and loop type signal a ₂ bits, b ₂ bits, c ₂ bits 511
51212, 51213, 5 every time it counts
This circuit receives one signal from 1216, creates one signal of one pulse, and clears 511.

A signal like 1 in FIG. 6 is input to 501. 5
10 gives the signal shown in FIG. 6 to 509204 and 511. 506 is the generator polynomial 1+X ^-m +X
^-n , and when the loop configuration code inputs _a1 bit, _a2 bits are detected as shown in FIG. a Before detecting ₂ bits, it is 50702, 5 as shown in Figure 6 3.
Cleared 511 after passing 0703. a When _2- bit detection starts, 507 becomes 5 as shown in Figure 6.
Open gate 11 and count a ₂ bits. a Give a signal to 512 after counting ₂ bits. 512 becomes 51 after passing through 51202, 51208, 51212
0 and gives the control signal shown in FIG. 6 to 509202 and 511. Similarly, 506 forms a generating polynomial of 1+X ^-1 +X ^-n , and 511 counts _b2 bits. Then give a signal to 512 and 51213
510 is activated, and 510 gives a signal shown in FIG. 6 to 509203 and 511. 516 constructs a generator polynomial 1+X ^-l +X ^-n and detects c ₂ bits of 0. Similarly, a signal such as 7 indicating the type of loop configuration is output to 505. 50707-5
0709 is 507 every time a ₂ , b ₂ , c ₂ bits are detected
Cleared 511 after passing through 03. When the signal shown in FIG. 6 and 8 is input from 503, the loop configuration is canceled and the initial state is established. If 512 detects a loop configuration code but does not detect a code indicating the type of loop configuration, 51303 returns 512 to its initial state via 51304 at a certain period of time.

The present invention is characterized by a method of forming a loop with a remote terminal under test under the control of the test terminal to test the terminal under test or between the test terminal and the terminal under test. Once the TA loop is configured, tests such as sending and receiving arbitrary test signals from the test terminal become possible. Once the test is finished, the loop is somehow broken. For example, when a loop is configured for a certain period of time and the time ends, a signal as shown in FIG. 6 and 8 may be input to 503 in FIG. 5, but the present invention refers only to the method of configuring the loop.

As explained above, according to the present invention, by using the loop configuration code, address code, and code indicating the type of loop as scramble signals, the transmitting circuit or the receiving circuit is created as one circuit without separating each code. This will result in significant economicalization.

[Brief explanation of the drawing]

1A and 1B are time charts showing the operation of the transmitter and receiver of the conventional system, respectively; FIGS. 2A and 2B are time charts showing the operation of the transmitter and receiver of the method of the present invention, respectively; FIG. 3 is a circuit diagram showing an embodiment of the transmitting section of the present invention;
FIG. 4 is a time chart of signals of each part in FIG. 3, FIG. 5 is a circuit diagram showing an embodiment of the receiving section of the present invention, and FIG. 6 is a time chart of signals of each part of FIG. be. In FIG. 3, 301 is a transmission data input terminal, 302 is a timing signal input terminal, 303 is a control signal input terminal, 304 is a transmission data output terminal, 305, 306 are control circuits, 30501, 3
0502, 30601 to 3060n-2 are switches, 307 is a selector circuit, 30701, 307
02 is a selector, 308 is a selector circuit, 308
01 is a selector, 309 is a scrambler circuit, 3
0901, 30902 are exclusive OR circuits, 30903 to 3090n are shift registers, 310 is a gate circuit, 310101 to 310
10n-3, 310201 to 310205 are NOR circuits, and 311 is a control signal generation circuit. In FIG. 5, 501 to 503 are input terminals, 504,
505 is a signal output terminal, 506 is a descrambler circuit, 50601 and 50602 are exclusive OR circuits, 50603 to 5060n+1 are shift registers, 507 is a clear signal generation circuit,
50701, 50704 to 50706 are shift registers, 50702 is an exclusive OR circuit, 50703 is an OR circuit, 50707 to 507
10 is a NAND circuit, 508 is a control circuit, 5080
1 to 5080n-2 are switches, 509 is a gate circuit, 509101 to 50910n-3, 509
201 to 50925 are NOR circuits, 510 is a gate signal generation circuit, 51001 is an AND circuit, 510
02, 51003 are NAND circuits, 51004 are NOR circuits, 51005, 51006 are inverting circuits, 5
11 is a timer, 512 is a loop configuration signal generation circuit, 51201 and 51202 are NAND circuits, 51
203, 51204 are inverting circuits, 51205 to 5
1207 is a NOR circuit, 51208 to 51211,
51216 is an OR circuit, 51212 to 51215
is a shift register, 513 is a loop configuration release signal generation circuit, 51301 is an inversion circuit, 51302 is a NAND circuit, 51303 is a timer, 51304
is an OR circuit.

Claims (1)

[Claims] 1. In the loop configuration method of a data transmission system test method that tests the terminal under test or between a test terminal and a terminal under test by configuring a loop with a remote terminal under test under the control of the test terminal, A code that is a combination of at least two of a loop configuration code that notifies to configure a loop, an address code that specifies one terminal under test, and a mode code that specifies the type of loop configuration is transmitted, and the terminal under test A loop configuration method for a data transmission system that detects combined codes and configures a loop, the method comprising means for creating a control signal for transmitting the combined codes in a time division manner, and a scramble signal for the combined codes using a generator polynomial. A code generating circuit having means for generating a predetermined generating polynomial by sequentially changing the generating polynomial of the scrambled signal, and means for sequentially transmitting the scrambled signal using the control signal is installed in a test terminal. means for descrambling the scrambled signal using a generating polynomial, means for detecting that the descrambled code is a predetermined series of 0 or 1, and using the detection signal. A code detection circuit is installed in a terminal under test, and includes means for sequentially changing a generating polynomial to descramble the scrambled signal to create a predetermined polynomial, and further means for setting the detection signal to detect the next scrambled signal. A loop configuration method for a data transmission system, characterized in that it is provided in a data transmission system.