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JPS62274683A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62274683A
JPS62274683A JP11951986A JP11951986A JPS62274683A JP S62274683 A JPS62274683 A JP S62274683A JP 11951986 A JP11951986 A JP 11951986A JP 11951986 A JP11951986 A JP 11951986A JP S62274683 A JPS62274683 A JP S62274683A
Authority
JP
Japan
Prior art keywords
mount
semiconductor
semiconductor laser
chip
laser chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11951986A
Other languages
Japanese (ja)
Inventor
Tomoko Kadowaki
朋子 門脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11951986A priority Critical patent/JPS62274683A/en
Publication of JPS62274683A publication Critical patent/JPS62274683A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To assure easy alignment with high accuracy while improving the reliability and workability in case of assembling process by a method wherein bonding alignment step difference is provided to make the end of a mount and the end of a semiconductor chip constantly flush with each other. CONSTITUTION:A mount 6 is provided with the depth equivalent to the resonance length L of a semiconductor chip 1 e.g. a semiconductor laser chip 1 and an alignment step difference 6B slightly lower than the height of a plated electrode 4. The semiconductor laser chip 1 is loaded upon the step difference base 6C of mount 6 through the intermediary of a solder member 5 to be heated up to the melting point of the solder member 2. The plated electrode 4 can be bonded closely to the alignment step difference 6B of mount 6 so that the oscillating end 1A of semiconductor laser chip 1 may be aligned with the end 6A of mount 6 to be in parallel therewith not to be retracted or protruded therefrom. Through these procedures, the semiconductor chip 1 and the mount 6 can be aligned with excellent accuracy without fail while improving the reliability, workability and yield in case of assembling a semiconductor device.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 この発明は、半導体チップが半田材によってマウントに
接着されて構成される半導体装置に関するものである。
Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor chip is bonded to a mount using a solder material.

以下、接合を下にして接着されるジャンクショウンダウ
ン型の半導体装置を例にとって説明する。〔従来の技術
〕 第2図は従来のジャンクションダウン型の半導体チップ
、例えば半導体レーザチップをマウントに装着した状態
を示す斜視図である。この図において、1は半導体レー
ザチップ、2は前記半導体レーザチップ1の裏面電極、
3は同じく表面電極で、両電極2と3の間には順次、半
導体基板、下クラッド層、接合を有する活性層、上クラ
ッド層、コンタクト層等が形成されているが図示は省。
Hereinafter, a description will be given by taking as an example a junction-down type semiconductor device that is bonded with the bonding side facing down. [Prior Art] FIG. 2 is a perspective view showing a state in which a conventional junction-down type semiconductor chip, such as a semiconductor laser chip, is mounted on a mount. In this figure, 1 is a semiconductor laser chip, 2 is a back electrode of the semiconductor laser chip 1,
3 is also a surface electrode, and between both electrodes 2 and 3, a semiconductor substrate, a lower cladding layer, an active layer with a junction, an upper cladding layer, a contact layer, etc. are successively formed, but these are not shown.

略しである。また表面電極3の上にはメッキ電極4が設
けられている。メッキ電極4は、半田材5を介してマウ
ント6に接着される。接着の際、半導体レーザチップ1
の発振端面1Aは、マウント6の端面(発振端面1Aと
合せるべき面)6Aと同一平面となるように位置するこ
とが望ましい。
This is an abbreviation. Furthermore, a plating electrode 4 is provided on the surface electrode 3. Plating electrode 4 is bonded to mount 6 via solder material 5. When bonding, the semiconductor laser chip 1
It is desirable that the oscillation end surface 1A is located on the same plane as the end surface 6A of the mount 6 (the surface to be aligned with the oscillation end surface 1A).

もし、半導体レーザチップ1の発振端面1Aがマウント
6の端面6Aよりも後退して接着されると、特にジャン
クションダウンに組み立てられている場合、レーザ光が
マウント6によりけられるという問題点がある。また逆
に、半導体レーザチップ1の発振端面1Aがマウント6
の端面6Aよりも突出して接着されると、熱放出効果が
悪くなるという問題点があった。
If the oscillation end face 1A of the semiconductor laser chip 1 is bonded at a position further back than the end face 6A of the mount 6, there is a problem that the laser light will be rejected by the mount 6, especially when assembled in a junction-down manner. Conversely, the oscillation end face 1A of the semiconductor laser chip 1 is connected to the mount 6.
There was a problem that if the adhesive was bonded so as to protrude beyond the end surface 6A, the heat dissipation effect would deteriorate.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のように平坦なマウント6の平面に半導体レーザチ
ップ1を接着する従来の半導体装置では、半導体レーザ
チップ1の発振端面1Aとマウント6の端面6Aとの位
置合せは目視で行っていたので、両端面1 A 、 6
Aが一致した位置に半導体レーザチップ1を接着するこ
とが非常に難しく、例えば第3図に示すように、半導体
レーザチップ1がマウント6に平行に接着されなかった
り、第4図に示すように半導体レーザチップ1がマウン
ト6より後退して接着されたり、逆に第5図に示すよう
に、半導体レーザチップ1がマウント6より突出して接
着される等、組立時の信頼性および作業性に問題点があ
った。
In the conventional semiconductor device in which the semiconductor laser chip 1 is bonded to the flat surface of the mount 6 as described above, the alignment between the oscillation end face 1A of the semiconductor laser chip 1 and the end face 6A of the mount 6 is performed visually. Both end faces 1A, 6
It is very difficult to bond the semiconductor laser chip 1 in the position where A matches, and for example, as shown in FIG. 3, the semiconductor laser chip 1 may not be bonded parallel to the mount 6, or as shown in FIG. There are problems with reliability and workability during assembly, such as the semiconductor laser chip 1 being glued backwards from the mount 6, or conversely, the semiconductor laser chip 1 being glued protruding from the mount 6 as shown in FIG. There was a point.

この発明は、上記のような問題点を解決するためになさ
れたもので、半導体チップの端面とマウントの端面とが
常に一致して接着でき、容易に、かつ精度よく位置合わ
せすることができる半導体装置を得ることを目的とする
This invention was made in order to solve the above-mentioned problems, and provides a semiconductor chip that can be bonded so that the end face of the semiconductor chip and the end face of the mount always match and can be easily and precisely aligned. The purpose is to obtain equipment.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、マウントの端面と半導体
チップの端面とが常に同一平面となるように接着される
位置決め用段差部をマウントに形成したものである。
In the semiconductor device according to the present invention, the mount is provided with a positioning step portion that is bonded so that the end face of the mount and the end face of the semiconductor chip are always on the same plane.

〔作用〕[Effect]

この発明においては、半導体チップをマウントに接着す
る際に、半導体チップのメ゛ツキ電極をマウントに形成
された位置決め用段差部と密着させることにより、半導
体チップの端面がマウントの端面に対して平行で、かつ
後退したり突出したりしないように接着される。
In this invention, when the semiconductor chip is bonded to the mount, the plating electrode of the semiconductor chip is brought into close contact with the positioning step formed on the mount, so that the end surface of the semiconductor chip is parallel to the end surface of the mount. and is glued so that it does not recede or protrude.

〔実施例〕〔Example〕

以下、この発明の一実施例を図面について説明する。な
お、この実施例の説明において、従来の技術の説明と重
複する部分については、適宜その説明を省略する。
An embodiment of the present invention will be described below with reference to the drawings. In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

第1図はこの発明の一実施例を示す半導体装置の斜視図
である。マウント6には半導体チップ、例えば半導体レ
ーザチップ1の共振長りと等しい奥行と、半導体レーザ
チップ1のメッキ電極4の高さよりもわずかに低い位置
決め用段差部6Bが設けられている。半導体レーザチッ
プ1を半田材5を介してマウント6の段差底部6C上に
載せ、半田材5の融点まで加熱すると、半田材5は溶融
する。この時、半導体レーザチップ1のメッキ電極4を
マウント6の位置決め用段差部6Bと密着させることに
より、半導体レーザチップ1の発振端面1Aが、この発
振端面1Aと同一平面になるように合わせるべき面であ
るマウント6の端面6Aに対して平行で、かつ後退した
り突出したりしないように位置合せすることができる。
FIG. 1 is a perspective view of a semiconductor device showing an embodiment of the present invention. The mount 6 is provided with a positioning step 6B having a depth equal to the resonance length of the semiconductor chip, for example, the semiconductor laser chip 1, and slightly lower than the height of the plated electrode 4 of the semiconductor laser chip 1. When the semiconductor laser chip 1 is placed on the step bottom 6C of the mount 6 via the solder material 5 and heated to the melting point of the solder material 5, the solder material 5 is melted. At this time, by bringing the plated electrode 4 of the semiconductor laser chip 1 into close contact with the positioning step portion 6B of the mount 6, the oscillation end surface 1A of the semiconductor laser chip 1 is aligned with the oscillation end surface 1A so that the surface to be aligned is aligned with the oscillation end surface 1A. It can be aligned so that it is parallel to the end surface 6A of the mount 6 and does not recede or protrude.

なお、上記実施例では、半導体レーザチップ1の接合を
下にして接着する場合について示したが、接合を上にし
て接着する場合でも裏面電極2の上にメッキ電極4を設
けることにより、同様の半導体装置を形成できることは
いうまでもない。
In the above embodiment, the case where the semiconductor laser chip 1 is bonded with the bond side down is shown, but even if the semiconductor laser chip 1 is bonded with the bond side up, the same effect can be achieved by providing the plating electrode 4 on the back electrode 2. Needless to say, semiconductor devices can be formed.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、マウントの端面と半導
体チップの端面とが常に一致して同一平面となるように
接着される位置決め用段差部をマウントに形成したので
、この位置決め用段差部に半導体チップのメッキ電極を
密着させることにより、半導体チップとマウントとの位
置合わせを精度よく、かつ確実に行うことができる。し
たがって、半導体装置の組立ての信頼性および作業性。
As explained above, in this invention, a positioning step is formed on the mount to which the end surface of the mount and the end surface of the semiconductor chip are bonded so that they always match and are on the same plane. By bringing the plated electrodes into close contact with each other, it is possible to accurately and reliably align the semiconductor chip and the mount. Therefore, the reliability and workability of semiconductor device assembly.

強いては歩留りを著しく向上させることができる利点が
ある。
It has the advantage that the yield can be significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す半導体装置の斜視図
、第2図〜第5図は従来の半導体装置をそれぞれ示すも
ので、第2図は従来のジャンフシボンダラン型の半導体
レーザチップをマウントに装着した状態を示す斜視図、
第3図は半導体レーザチップがマウントに平行に装着さ
れていない状態を示す斜視図、第4図は半導体レーザチ
ップがマウントより後退して接着された状態を示す斜視
図、第5図は半導体レーザチップがマウントより突出し
て接着された状態を示す斜視図である。 図において、1は半導体レーザチップ、1Aは発振端面
、2は表面電極、3は表面電極、4はメッキ電極、5は
半田材、6はマウント、6Aはマウントの端面、6Bは
位置決め用段差部、6Cは段差底部である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人  大 岩 増 雄   (外2名)第1図 第2図 第4図 手続補正書(自発) I−11
FIG. 1 is a perspective view of a semiconductor device showing an embodiment of the present invention, FIGS. 2 to 5 show conventional semiconductor devices, and FIG. 2 shows a conventional Janfushi Bondarun type semiconductor laser. A perspective view showing the state where the chip is attached to the mount,
Figure 3 is a perspective view showing a state in which the semiconductor laser chip is not mounted parallel to the mount, Figure 4 is a perspective view showing the state in which the semiconductor laser chip is set back from the mount and bonded, and Figure 5 is a perspective view showing the semiconductor laser chip FIG. 3 is a perspective view showing a state in which the chip protrudes from the mount and is bonded. In the figure, 1 is a semiconductor laser chip, 1A is an oscillation end face, 2 is a surface electrode, 3 is a surface electrode, 4 is a plating electrode, 5 is a solder material, 6 is a mount, 6A is an end face of the mount, and 6B is a positioning step. , 6C is the bottom of the step. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 4 Procedural amendment (voluntary) I-11

Claims (1)

【特許請求の範囲】[Claims] 半導体チップの表面電極上または裏面電極上に形成され
るメッキ電極を半田材を介してマウント上に接着した半
導体装置において、前記マウントの端面と前記半導体チ
ップの端面とが常に同一平面となるように接着される位
置決め用段差部を前記マウントに形成したことを特徴と
する半導体装置。
In a semiconductor device in which a plating electrode formed on a front surface electrode or a back surface electrode of a semiconductor chip is bonded to a mount via a solder material, the end surface of the mount and the end surface of the semiconductor chip are always on the same plane. A semiconductor device characterized in that a positioning step portion to be bonded is formed on the mount.
JP11951986A 1986-05-22 1986-05-22 Semiconductor device Pending JPS62274683A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11951986A JPS62274683A (en) 1986-05-22 1986-05-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11951986A JPS62274683A (en) 1986-05-22 1986-05-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62274683A true JPS62274683A (en) 1987-11-28

Family

ID=14763281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11951986A Pending JPS62274683A (en) 1986-05-22 1986-05-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62274683A (en)

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