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JPS62264661A - Optical-electronic integrated circuit and manufacture thereof - Google Patents

Optical-electronic integrated circuit and manufacture thereof

Info

Publication number
JPS62264661A
JPS62264661A JP10776286A JP10776286A JPS62264661A JP S62264661 A JPS62264661 A JP S62264661A JP 10776286 A JP10776286 A JP 10776286A JP 10776286 A JP10776286 A JP 10776286A JP S62264661 A JPS62264661 A JP S62264661A
Authority
JP
Japan
Prior art keywords
semiconductor layer
conductivity type
layer
semiconductor
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10776286A
Other languages
Japanese (ja)
Inventor
Yuji Hasumi
蓮見 裕二
Jiro Tenmiyo
天明 二郎
Hajime Asahi
一 朝日
Atsuo Koumae
篤郎 幸前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10776286A priority Critical patent/JPS62264661A/en
Publication of JPS62264661A publication Critical patent/JPS62264661A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261Non-optical elements, e.g. laser driver components, heaters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Lasers (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain optical-electronic IC of high performance by a method wherein an nnnn<+> multilayer epitaxial film of AlX Ga1-xAs is provided with a composition ratio (x) varied on a semi-insulative GaAs substrate, further npnn<+> multilayer epitaxial film of AlzGal-zAs is superposed thereon with a composition ratio (z) varied, and a p+ layer is provided selectively. CONSTITUTION:n-AlxGa1-xAs 2, n-CaAs 3 and n-A$1xGa1-xAs 4 are superposed on semi-insulative GaAs 1 to construct a horizontal fringe laser, and n+-GaAs 5 is superposed thereon. Moreover, n-GaAs 6, p-AlzGa1-zAs 7, n-AlzGa1-zAs 8 and n<+>-GaAs 9 are superposed. A p<+> layer 10 is diffused to prepare a hetero junction element of an n<+> collector 5, a p<+> base 10 and an n<+> emitter 9. Next, a p<+> ion implanted layer 11 extending from the n<+> layer 5 to the substrate 1 is prepared, diffusion is conducted again to provide a p layer 12, electrodes P and N to form a laser diode, and H ions are implanted for element isolation 13 and 13 '. According to this construction, the concentration of a laser active layer and the concentration of a base layer of a transistor can be set separately, and the horizontal laser of a low threshold current and the trsnsiator of a cut-off frequency of 1 GHz or above are obtained on the same substrate.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、先進信用送信器に使用される高速かつ高信頼
な光・電子集積回路及びその製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-speed and highly reliable optical/electronic integrated circuit used in an advanced reliable transmitter and a method for manufacturing the same.

(従来技術及び発明が解決しようとする問題点)従来の
光送信器は、光源となる半導体V−ザ(以下LDと把子
りとそれを駆動・変調する電子回路の各々全個別の部品
として製作し、しかる後、それらを接続する形態ケとっ
ていた。しかしながら、このLd)な方式では、部品間
の配線に伴う伝搬遅延や浮遊容量のtめ、動作が遅くな
るほか、接続部分に起因する信頼性の低下も問題となる
。したがって、高速かつ高信頼の光送信器を構成するに
ぼ、光素子と電子素子七一体化した光・電子集積回路が
必要である。特に、ヘテロ接合バイポーラトランジスタ
(Heter。
(Prior Art and Problems to be Solved by the Invention) A conventional optical transmitter consists of a semiconductor laser (hereinafter referred to as an LD, a clamp, and an electronic circuit that drives and modulates the light source), each of which is made up of individual components. However, in this Ld) method, operation is slow due to propagation delay and stray capacitance caused by wiring between components, and problems caused by connections. Deterioration in reliability due to this is also a problem. Therefore, in order to construct a high-speed and highly reliable optical transmitter, an optical/electronic integrated circuit that integrates optical elements and seven electronic elements is required. In particular, heterojunction bipolar transistors (Heter.

5turucture Bipolar Transi
stor以下HBTと把子)は、高い電流駆動能力と高
速動作性を有することから、HBTとLD’に組合せ之
集積回路が、尚連光送信器として有望である。
5structure Bipolar Transi
Since the stor (hereinafter referred to as HBT and stor) has high current drive capability and high-speed operation, an integrated circuit combining the HBT and LD' is promising as a continuous optical transmitter.

HBTとLDを用い集積回路を構成する試みとしては、
ジエ・カアツ(J、 Katz )らの報告(Appl
、 Ph7s、 Lett、+ 37(2)、 198
0 )がある。
As an attempt to construct an integrated circuit using HBT and LD,
Report by J. Katz et al. (Appl.
, Ph7s, Lett, +37(2), 198
0).

第3図は上記の報告に示された構成を示すもので、この
素子はn”−GaAs基板20上に、基板側工υ第1層
n −AlGaAs 21、第2層p −GaAs 2
2、第31m n −AlGaAs 23エピタキシヤ
ルI[−成長し、npn構造ニジ成るHBTを製作する
と共に、Beイオンを第31−詔からp−GaAs 2
2まで注入することで、第3/11123のn −Al
GaAsの一部t−pW24に変え%  npp構造エ
ク成るLDとしても動作させられる工う工夫されている
。しかしながら、この工うな構造には次の工うな欠点が
ある。
FIG. 3 shows the configuration shown in the above report, and this device is made of an n''-GaAs substrate 20, a first layer of n-AlGaAs 21 on the substrate side, and a second layer of p-GaAs 2.
2. The 31st mn-AlGaAs 23 epitaxial I[- was grown to fabricate an HBT with an npn structure, and Be ions were added to the p-GaAs 2 from the 31st edict.
By implanting up to 2, the 3rd/11123rd n-Al
It has been devised that it can also be operated as an LD with an npp structure in place of the t-pW24 part of GaAs. However, this strange structure has the following drawbacks.

すなわち、LDの活性層として使用する第2層nのp 
−GaAs ハs 目出キャリアによる光吸収で、レー
ザ発振閾値が上界するのを避ける必要から、ドーピング
濃度全高くする(≧5 Xl01′t−rn−’ )こ
とは望ましくない。一方、このp −GaAs層は、H
BTのベース部分としても使用されるが、HBTにおい
ては、動作速度の目安となるカットCc:コレクタ容址
ノで与えられることから分かる工うに、ベース濃度を高
くし、ベース抵抗を低減することが動作上有利である。
That is, the p of the second layer n used as the active layer of the LD
-GaAs s Since it is necessary to prevent the laser oscillation threshold from being raised due to light absorption by visible carriers, it is not desirable to increase the total doping concentration (≧5 Xl01't-rn-'). On the other hand, this p-GaAs layer
It is also used as the base part of BT, but in HBT, it is possible to increase the base concentration and reduce the base resistance, as can be seen from the cut Cc: Collector capacity, which is a guideline for operating speed. Operationally advantageous.

以上のことから明らかな二うに、LD、HBT%々を同
時に高性能化するためには、各々に適し之組成。
It is clear from the above that in order to improve the performance of LD and HBT at the same time, compositions suitable for each must be selected.

膜厚、ドーピング#匿を選ぶ必要があり、カアツらの工
うな、率なるnpn構遺からなるエピタキシャル膜のみ
を用いる方法では不十分である0 この問題を解決するためには、LDに適し几nnp(も
しくはnpps あるいは活性層をアンドープとしたり
構造と、HBTに適し7′Cnpn構造をもつエピタキ
シャル多層膜を連続的に形成し、各々のエピタキシャル
膜に対し、LD。
It is necessary to choose the film thickness and doping density, and a method using only an epitaxial film consisting of a primary npn structure, such as Kaatsu et al.'s method, is insufficient.To solve this problem, it is necessary to An epitaxial multilayer film having an nnp (or npps) structure with an undoped active layer and a 7'Cnpn structure suitable for HBT is successively formed, and LD is applied to each epitaxial film.

HBTfr、別個に製作すれば良いが、このような多層
構造では、LDもしくはHBTの下部電極を取り出丁際
、深いエツチングをする必要があるため、表面段差が大
きく、乗積化には適さない構造となる。1ft% LD
、HBT用のエピタキシャル膜全平面上で分けて成長さ
せる選択成長も技術的に難しく、集積回路への適用には
問題が多い。
HBTfr can be fabricated separately, but in such a multilayer structure, it is necessary to perform deep etching when removing the lower electrode of the LD or HBT, resulting in large surface steps, making it unsuitable for multilayer stacking. It becomes a structure. 1ft% LD
, selective growth in which the epitaxial film for HBT is grown separately over the entire plane is also technically difficult, and there are many problems in its application to integrated circuits.

(問題点を解決する几めの手段) 本発明の目的は、HBT、LD各々に対し、その素子特
性上有利なエピタキシャル膜の成長を可能にすると共に
、そのために生じる段差越え等の問題を回避し、高性能
かつ集積化の容易な光・電子集積回路及びその製造方法
を提供することにある。
(Detailed means for solving the problem) An object of the present invention is to enable the growth of epitaxial films that are advantageous in terms of device characteristics for both HBTs and LDs, and to avoid problems such as overpassing of steps that arise due to this. Another object of the present invention is to provide a high-performance, easy-to-integrate optical/electronic integrated circuit and a method for manufacturing the same.

上記の目的を達成するkめ、本発明は半絶縁性基板上に
、M1導電型の第1の半導体層、第1の半導体層に比し
てナロウギヤツプである第1導電型の第2の半導体層、
第2の半導体層に比してワイドギャップである第1導電
型の第3の半4体j−がj賊次槓層された第1の多層エ
ピタキシャル膜に、第2の半導体層を箔性贋、第1及び
第3の半導体層?クララド層とする横型接合ストライプ
レーザが構成され、前記の第1の多層エピタキシャル操
上に第14亀型の高濃度不純物を有する第4の半導体層
、及び第1導電型の第5の半導体層、第2導電型の第6
の半導体層、第6の半導体層に比してワイドギャップで
ある第1導電型の第7の半導体層、第1導電型の高v!
に度不純物を有する第8の半導体層が順次積層され7’
C第2の多層エピタキシャル膜に、第5の半導体層ケコ
レクタ、第6.第7.第8の半導体層阿に形成され次第
2導電量の高濃度不純物狽域tベースコンタクト領域、
第6の半導体層内のベースコンタクト領域以外をベース
、第7の半導体層内のベースコンタクト領域以外を工ば
ツタとするペテロ接合バイポーラトランジスタが構成さ
れること全特徴とする光・電子集積回路を発明の要旨と
するものである。
To achieve the above object, the present invention provides a first semiconductor layer of M1 conductivity type, and a second semiconductor layer of first conductivity type, which has a narrow gap compared to the first semiconductor layer, on a semi-insulating substrate. layer,
A second semiconductor layer is attached to the first multilayer epitaxial film in which a third half body of the first conductivity type, which has a wider gap than the second semiconductor layer, is layered with a foil layer. Fake, first and third semiconductor layers? A lateral junction stripe laser having a Clarado layer is configured, a fourth semiconductor layer having a 14th turtle-type high concentration impurity on the first multilayer epitaxial layer, and a fifth semiconductor layer of a first conductivity type; 6th conductivity type
, a seventh semiconductor layer of the first conductivity type which has a wider gap than the sixth semiconductor layer, and a high v! of the first conductivity type.
An eighth semiconductor layer containing impurities is sequentially stacked 7'.
A fifth semiconductor layer collector, a sixth . 7th. As soon as the eighth semiconductor layer is formed, a high concentration impurity region having a conductivity of 2 is formed in a base contact region;
An opto-electronic integrated circuit characterized in that a Peter junction bipolar transistor is constructed in which a portion other than the base contact region in the sixth semiconductor layer is a base, and a portion other than the base contact region in the seventh semiconductor layer is a vine. This is the gist of the invention.

さらに本発明は半絶縁性基板上に、第1導電型の第1の
半導体ノー、第1の牛4体層に比してナロワギャップで
ある第1導電型の第2の半導体層・第2の半導体j―に
比してワイドギャップである第1導電型の第3の半導体
層を順次積層して第1の多層エピタキシャル膜を形成し
、第1の多層エピタキシャル膜内に、第2の半導体層を
活性層、第1及び第3の半導体層をクラッド層とする横
型接合ストライプV−ザを構成し、第1の多層エピタキ
シャル膜上に第1導電型の高濃度不純物を有する第4の
半導体層、第1導電型の第5の半導体層、第2導電型の
第6の半導体層、第6の半導体層に比してワイドギャッ
プである第1導電型の第7の半導体層、第1導電型の高
濃度不純物を有する第8の半導体層を順次積層して第2
の多層エピタキシャル@を形成し、第6.第7.第8の
半導体層内にイオン注入或いに気相拡散法を用いて第2
導を型の高濃度不純物領域を選択的に形成し、第5の半
導体層tコレクタ、W、6.第7.第8の半導体層内に
形成され定温2導電型の高濃度不純物領域をベースコン
タクト領域、第6の半導体層内のベースコンタクト9A
域以外tベース、第7の半導体層内のベースコンタクト
領域以外をエミッタとするヘテロ接合バイポーラトラン
ジスタを構成することを特徴とする光・電子集積回路の
製造方法を発明の要旨とするものである。
Further, the present invention provides a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, which has a narrower gap than the first four-layer structure, on the semi-insulating substrate. A first multilayer epitaxial film is formed by sequentially stacking third semiconductor layers of the first conductivity type, which have a wider gap than the semiconductor j-, and a second semiconductor layer is formed in the first multilayer epitaxial film. A fourth semiconductor which constitutes a horizontal junction stripe V-ZA in which the layer is an active layer and the first and third semiconductor layers are cladding layers, and has a first conductivity type high concentration impurity on the first multilayer epitaxial film. a fifth semiconductor layer of the first conductivity type, a sixth semiconductor layer of the second conductivity type, a seventh semiconductor layer of the first conductivity type having a wider gap than the sixth semiconductor layer; A second semiconductor layer is formed by sequentially stacking an eighth semiconductor layer having a high concentration impurity of a conductivity type.
6. Form a multilayer epitaxial @. 7th. The second semiconductor layer is formed using ion implantation or vapor phase diffusion into the eighth semiconductor layer.
selectively forming conductor-type high concentration impurity regions, forming the fifth semiconductor layer t-collector, W, 6. 7th. The high concentration impurity region of constant temperature 2 conductivity type formed in the eighth semiconductor layer is used as a base contact region, and the base contact 9A in the sixth semiconductor layer is used as a base contact region.
The gist of the invention is a method for manufacturing an opto-electronic integrated circuit, which is characterized in that a heterojunction bipolar transistor is constructed in which a base other than the base contact region in a seventh semiconductor layer is used as an emitter.

しかして本発明の特徴とする点は次の点にある0 まず、HBT及びLDK通した映厚1組成。However, the characteristics of the present invention are as follows. First, the film thickness is 1 composition through HBT and LDK.

不純物濃度を実現するmめ、各々の素子構造に対応する
エピタキシャル膜として、基板側工りJljtにn n
 n n” n p n n+ニジなる多7m 換k、
MOVPE 。
In order to realize the impurity concentration, the substrate side is etched as an epitaxial film corresponding to each element structure.
n n” n p n n+niji naru multi 7m exchange k,
MOVPE.

MBE、LPE等の結晶成長技術を用いて形成し、この
エピタキシャル膜に谷素子を製作する。
It is formed using a crystal growth technique such as MBE or LPE, and a valley element is manufactured in this epitaxial film.

LDは下部nnnn+層を利用し、ここへ横型接合スト
ライプレーザ(Transverse Junctio
nStripe以下TJSと把子)全製作する。TJS
構造とし友結果、LDの電極は第4層n+層から取り吊
すことが可能であるtめ、深いエツチングが必要なく、
集積化に適し几平坦な表面構造が実現できる。
The LD uses the lower nnnn+ layer, and a lateral junction stripe laser (Transverse Junction) is inserted here.
nStripe (hereafter referred to as TJS and Hashi) will be fully manufactured. T.J.S.
As a result of the structure, the LD electrode can be suspended from the fourth n+ layer, so deep etching is not required.
A flat surface structure suitable for integration can be realized.

HBTのベース層はLDとは独立になっている次め、高
濃度ドーピングが可能であり、さらに、傾斜バンドギャ
ップ構造とすることで、ペース内での電子の走行時間が
短縮てれ、電流増幅率の増大がはかれる。
Since the base layer of the HBT is independent of the LD, high concentration doping is possible.Furthermore, by having a graded bandgap structure, the transit time of electrons within the pace is shortened, which increases current amplification. An increase in the rate is measured.

このようなエピタキシャル膜構造は、従来の光・電子集
積回路の膜構造とは全く異なるものである。
Such an epitaxial film structure is completely different from the film structure of conventional opto-electronic integrated circuits.

次に本発明の実施例を添付図面について説明する0 なお実施例は一つの例示でろって、本発明の精神を逸脱
しない範囲で個々の変更あるいは改良を行いうることは
言9までもない。
Next, embodiments of the present invention will be described with reference to the accompanying drawings.0 It should be noted that the embodiments are merely illustrative, and it goes without saying that individual changes or improvements can be made without departing from the spirit of the present invention.

第1図は本発明の実施例を示すもので、その構成は次の
とおりである。図において1はGaAaエリなる半絶縁
性基板で、この半絶縁性基板上に、第144型の@10
半導体層2のn −At3:Ga1−。
FIG. 1 shows an embodiment of the present invention, and its configuration is as follows. In the figure, 1 is a semi-insulating substrate made of GaAa. On this semi-insulating substrate, a 144th type @10
n-At3:Ga1- of semiconductor layer 2;

As%第1の半導体層2に比ベナロウギヤツプである第
1導電量の第2の半導体層3のn −GaAs(又はA
tyGal−yAs ) (工> y )、第2の半導
体層3に比してワイドギャップである第1導電型の第3
の半導体層4のn −kL□Ga□−よAsがノ臓次積
層され、半導体+1112.3.4に工V第1の多層エ
ピタキシャルlUk形成し、この多層エピタキシャル膜
に半4体鳩3を活性層、半導体層2及び4をクラッド層
とする横型受合ストライプ/−ザを構成する。ついで第
1の多層エピタキシャル膜上に第1導屯型の高濃度不純
物を有する剥4の半導体層5のn+−GaAs 、つい
で第1尋成型の第5の半導体層6のn −GaAs 、
第2纒篭型の第6の半導体層7のp −Atz’Ga1
−1’ Aa s第6の半導体;―に比してワイドギャ
ップである第1尋成型の第7の半導体層8のn −At
zGa l−2As sついで第14篭型の尚濃度不純
物を有する第8の半導体層9のn”−GaAsを順次積
層して第2の多層エピタキシャル膜を形成し、嘔らに半
導体層7゜8.9の鴇域円に第254−直型の鍋強度不
純吻狽域10に形成する。しかして第5の半導体ノ曽6
をコレクタ、第2導電量の高濃度不縄物填域lOtベー
スコンタクト狽域、第6の半導体層7門のベースコンタ
クト狽域外ケベース、第7の半導体11g8のベースコ
ノタクト領域外全エミッタとするヘテロ接合バイポーラ
トランジスタ全形成する。
As% n-GaAs (or A
tyGal-yAs) (Engineering>y), the third semiconductor layer of the first conductivity type has a wide gap compared to the second semiconductor layer 3.
The n -kL□Ga□- and As of the semiconductor layer 4 are layered one after another, and the first multilayer epitaxial lUk is formed on the semiconductor +1112.3.4. A horizontal reception stripe/-the active layer and semiconductor layers 2 and 4 are used as cladding layers. Next, n + -GaAs of the stripped semiconductor layer 5 having a first conductivity type high concentration impurity on the first multilayer epitaxial film, then n -GaAs of the first thinly molded fifth semiconductor layer 6,
p -Atz'Ga1 of the second cage-shaped sixth semiconductor layer 7
-1' Aa s sixth semiconductor;
Next, a second multilayer epitaxial film is formed by sequentially stacking the 14th cage-type n''-GaAs of the eighth semiconductor layer 9 having impurity concentration. .9 is formed in the 254th straight pot strength impurity area 10.Therefore, the fifth semiconductor noso 6 is formed.
Let be the collector, the high concentration impurity filling area lOt of the second conductivity, the base contact area of the 7 gates of the sixth semiconductor layer, the base outside the base contact area of the seventh semiconductor layer 11g8, and all the emitters outside the base contact area of the seventh semiconductor 11g8. All heterojunction bipolar transistors are formed.

さらに説明をつけ加えゐと、半絶稼匣GaAs基板1の
直上にある半導体層2はn −At:、Ga1−、As
(0くx〈1)であり、ここはレーザダイオード(以下
LDと記す)のクラッド層となる。半導体層3はLDの
活性層となる部分でn −GaAsもしくはn −At
yGa t−y As (但踵z>y)1りなる。(適
切な不純@(Si)濃度は5X10つ鴨3である。)半
導体層4はn −AtzGa 1−2 AsでLDのク
ラッド層となる。M組成’jez>yとしているので、
半導体N3の屈折率は半纏体M2お工び4工や大きく、
光閉じ込め効果が働いてレーザ閾値の低減がはかられて
いる。半導体WI5はコンタクト層として設けたn”−
GaAs層であり、LDの電極をとるほか、HBTのコ
レクタ電極も、この層からとる。半導体層6はn −G
aAsであジ、HBTのコレクタ部分となる。半導体/
#7は傾斜バンドギャップ構造からなるp領域で、HB
Tの6一ス層となる部分である。適切な不純物(Be)
濃度は5 xlO”/cW1’である。半導体層8はn
−AAGa 1−z AsでHBTのエミッタとなる部
分である。
To add further explanation, the semiconductor layer 2 directly above the semi-active GaAs substrate 1 is made of n-At:, Ga1-, As.
(0x<1), and this becomes the cladding layer of a laser diode (hereinafter referred to as LD). The semiconductor layer 3 is a portion that becomes the active layer of the LD and is made of n -GaAs or n -At.
yGa ty-y As (However, z>y) becomes 1. (An appropriate impurity@(Si) concentration is 5×10×3.) The semiconductor layer 4 is n-AtzGa 1-2 As and becomes the cladding layer of the LD. Since the M composition 'jez>y,
The refractive index of the semiconductor N3 is as large as that of the semi-integrated body M2.
The optical confinement effect works to reduce the laser threshold. The semiconductor WI5 has an n”- layer provided as a contact layer.
This layer is a GaAs layer, and in addition to the LD electrode, the HBT collector electrode is also formed from this layer. The semiconductor layer 6 is n-G
aAs serves as the collector portion of the HBT. semiconductor/
#7 is a p region consisting of a tilted bandgap structure, and HB
This is the part that becomes the 6th layer of T. Appropriate impurity (Be)
The concentration is 5 xlO"/cW1'. The semiconductor layer 8 has n
-AAGa 1-z As is the part that becomes the emitter of the HBT.

半導体層9はn”−GaAsでHBTのエミッタおよび
ペース電極をとるコンタクト層である。不純物領域10
はZn + Be + Mg等のp型不純物をイオン注
入もしくは気相拡散し几p+領域で、ベース層とのコン
タクトを取る几めに設けである。
The semiconductor layer 9 is a contact layer made of n''-GaAs and serves as the emitter and space electrode of the HBT. Impurity region 10
A p-type impurity such as Zn + Be + Mg is ion-implanted or vapor-phase diffused to form a p+ region, and is provided in a manner to make contact with the base layer.

しかして半導体/fi 7’を傾斜バンドギャップペー
スとする。この場合には、p−At2Ga1層−2’ 
Asにおいて、z′の値をゼロから2まで連続的に変化
させであるので、そのバンド構造は第2図(b)のLP
/!/cなる。し之がって、ベース領域へ注入され7’
C電子は、内部電界で加速され、従来のベース領域で電
子が拡散する場合(第り図a参照)工υ速いドリフト運
度で走行することになる。
Thus, the semiconductor/fi 7' is made into a graded bandgap pace. In this case, p-At2Ga1 layer-2'
In As, the value of z' is continuously changed from zero to 2, so the band structure is LP in Figure 2(b).
/! /c becomes. Therefore, it is injected into the base region 7'
The C electrons are accelerated by the internal electric field, and when electrons are diffused in the conventional base region (see Figure A), they travel with a faster drifting speed.

この効果はベース走行時間τについて、拡散の(K:ボ
ルソマン定数I T 11絶対温度、q:電子の電荷量
りとなるので、ベース両端でのバンドギャップ差△Eg
t−0,2eVとすると走行時間は約1/4に短縮され
ることになる。この結果、電流利得βの増大がはかれる
ほか、電子と正孔の再、結合が減る等、HBTの特性向
上が期待できる0 ま念半導体層7にp −GaAsを用いることもできる
This effect is related to the base transit time τ, where (K: Bolsomann constant I T 11 absolute temperature of diffusion, q: electron charge amount, band gap difference △Eg at both ends of the base)
If it is set to t-0.2 eV, the travel time will be shortened to about 1/4. As a result, in addition to increasing the current gain β, it is also possible to use p-GaAs for the semiconductor layer 7, which is expected to improve the characteristics of the HBT, such as reducing the recombination of electrons and holes.

E、B、Ci夫々エミッタ、ペース、コレクタ電極を示
す。
E, B, and Ci indicate emitter, pace, and collector electrodes, respectively.

LDについては、Zn + Be + Mg等のp型不
純物を半導体層2〜5にイオン注入もしくは気相拡散し
てp+幀域11を作り、しかる後、熱処理によってp型
不純物ケ再拡散して12に示すp領域を形成する。13
.13’はB、H等のイオン注入による絶縁領域を示す
。P、Nは夫々電極を示す。
For the LD, a p-type impurity such as Zn + Be + Mg is ion-implanted or vapor-phase diffused into the semiconductor layers 2 to 5 to form a p+ region 11, and then the p-type impurity is re-diffused by heat treatment to form a p-type impurity region 12. A p region shown in is formed. 13
.. Reference numeral 13' indicates an insulating region formed by ion implantation of B, H, or the like. P and N indicate electrodes, respectively.

電極をコンタクト層5に設けてm電すると、電流は半導
体層2.3.4同のpn接合を流れることV(なる。之
だし、この場合半導体N3にできるpn接合と半導体層
2お工び4にできるpn接合では、キャリアに対する内
部障壁が半畳体層3の方が低いtめ、電流は主に半導体
層3のpn接合を流れこの部分がLDの活性層となるO 次に製造順序について説明する。
When an electrode is provided on the contact layer 5 and a current is applied, the current flows through the same pn junction in the semiconductor layer 2.3.4. In the pn junction formed in 4, the internal barrier to carriers is lower in the semiconducting layer 3, so the current mainly flows through the pn junction in the semiconductor layer 3, which becomes the active layer of the LD.Next, regarding the manufacturing order. explain.

ピン半絶縁性GaA s基板l上に第1の半導体層2の
n −At、Gat、As t−形成し、ついで第1の
半導体層に比べてナロウギヤツプである第2の半導体層
30n −GaAl1又はn −AtyGa 1− y
As (ここにx > y ) Ir、形成し、ついで
半導体層3に比してワイドギャップである第30半導体
鳩4のn−AtよGa1−エAsi形成して、第1の多
層エピタキシャル膜を形成し、この第1の多層エピタキ
シャル膜内に、半導体層3を活性層、半導体層2及び4
をクラッド層とする■型適合ストライプレーザ?構成す
る。
A first semiconductor layer 2 (n-At, Gat, Ast) is formed on a pinned semi-insulating GaAs substrate l, and then a second semiconductor layer 30n-GaAl1 or n-GaAl1 having a narrow gap compared to the first semiconductor layer is formed. n-AtyGa 1-y
As (where x > y) Ir is formed, and then n-At, Ga1-air, and Asi of the 30th semiconductor layer 4, which has a wider gap than the semiconductor layer 3, are formed to form the first multilayer epitaxial film. The semiconductor layer 3 is formed as an active layer, and the semiconductor layers 2 and 4 are formed in this first multilayer epitaxial film.
■Type compatible stripe laser with cladding layer? Configure.

幹)ついで第1の多1−エピタキシャル嗅上に高濃度不
純物を有する第4の半導体層5のn”−GaAsを形成
し、その上に第5の半4体層6のn −GaAsを形成
し、さらに第6の半4体層7のn −AL、/Ga1−
2’As 1第6の半導体層7しζ比してワイドギャッ
プである第7の半導体層8のn −At2Ga1−2A
s sついで高濃度不純物を有する第8の半導体層9の
n −GaAsを積層して第2の多層エピタキシャル膜
を形成し、第6.第7.第8の半導体ノー7゜8.9の
一部にイオン注入あるいは気相拡散隣を用いてp型の高
a度不純物狽域10を選択的に形成した後、半導体層6
tコレクタに、高a度不純物領域10ヲベースコンタク
ト領域、第6の半導体層7をペース、第7の半導体層8
をエミッタとするヘテロ接合バイポーラトランジスタを
構成する。
Next, a fourth semiconductor layer 5 of n''-GaAs having a high concentration of impurities is formed on the first poly-epitaxial layer, and a fifth n-GaAs layer of a fifth semi-quadram layer 6 is formed thereon. In addition, n -AL, /Ga1- of the sixth semi-quaternary layer 7
2'As 1 n -At2Ga1-2A of the seventh semiconductor layer 8 which has a wide gap compared to the sixth semiconductor layer 7
s s Next, a second multilayer epitaxial film is formed by laminating the eighth semiconductor layer 9 of n-GaAs having a high concentration of impurities. 7th. After selectively forming a p-type high a degree impurity region 10 in a part of the eighth semiconductor layer 7° 8.9 using ion implantation or vapor phase diffusion, the semiconductor layer 6
A high-a-grade impurity region 10, a base contact region, a sixth semiconductor layer 7, and a seventh semiconductor layer 8 are placed on the T collector.
A heterojunction bipolar transistor is constructed with the emitter.

(ハ)ついでイオン注入絶縁領域13ヲ形成し、 LD
全構成する。
(c) Next, an ion-implanted insulating region 13 is formed, and the LD
Complete configuration.

なお、上記の工うな傾斜バンド構造は、結晶成長中にそ
の原料となる物質の比率を変化させてゆくことで実現で
きる。例えばAlGaAsの傾斜バンド構造を有機金属
気相エピタキシャル法(Metalorganic V
apor Phase Epitaxy )で製作する
場合には、トリメチルガリウム(TMG)を含む水素ガ
スとアルシン(AsHs )ガスの流量を一定にしなが
ら、トリメチルアルミニウム(TMA)を含む水素ガス
の流!lを連続的に変化させる方法をとるものである。
Note that the above-mentioned inclined band structure can be realized by changing the ratio of the raw materials during crystal growth. For example, the tilted band structure of AlGaAs can be fabricated using metalorganic vapor phase epitaxial method (Metalorganic V epitaxial method).
apor Phase Epitaxy), the flow rate of hydrogen gas containing trimethylaluminum (TMA) is kept constant while the flow rate of hydrogen gas containing trimethylgallium (TMG) and arsine (AsHs) gas is constant. This method uses a method of continuously changing l.

尚第1.第3.第7の半導体層にInPx第2゜第4.
第5.第8の半導体層にInGaAs 又はInGaA
sP s第6の半導体層にInP又は I nGaAs
又はInGaAsP f用いることもできる。
First of all. Third. The seventh semiconductor layer has InPx second and fourth layers.
Fifth. InGaAs or InGaA is used as the eighth semiconductor layer.
sP s InP or InGaAs for the sixth semiconductor layer
Alternatively, InGaAsP f can also be used.

さらに上記の説明中p型tn型に、nfiをp型にする
こともできる。
Furthermore, in the above description, nfi can be made p-type instead of p-type tn-type.

(発明の効果〕 以上説明し友工うに、本発明によればLDとHBTを両
者の特性を損ねることなく同一基板上に集積するもので
あり、この結果、高速かつ高信頼な光・電子集積回路の
製作が可能となる。
(Effects of the Invention) As explained above, according to the present invention, an LD and an HBT can be integrated on the same substrate without impairing their characteristics, and as a result, high-speed and highly reliable optical/electronic integration can be achieved. It becomes possible to manufacture circuits.

このLつな光・電子集積回路は、光通信の大容量化に適
した光送信器として利用できるオリ点がある。
This L-connected optical/electronic integrated circuit has the advantage that it can be used as an optical transmitter suitable for increasing the capacity of optical communication.

さらにま九本発明においては横型接合ストライプレーザ
の活性層濃度と、ヘテロ接合バイポーラトランジスタの
ペース濃度とを別に設定することができるので、レーザ
のしきい値電流が低く(10mA程度)、横型接合スト
ライプレーザとカットオフ周波数が高い(IGHz以上
)へテロ接合バイポーラトランジスタとを同一基板上に
形成することができる。
Furthermore, in the present invention, since the active layer concentration of the lateral junction stripe laser and the base concentration of the heterojunction bipolar transistor can be set separately, the threshold current of the laser is low (about 10 mA), and the lateral junction stripe laser has a low threshold current (about 10 mA). A laser and a heterojunction bipolar transistor with a high cutoff frequency (IGHz or higher) can be formed on the same substrate.

ま友横注入型の接合ストライプレーザを用いている之め
、従来例のようにレーザの下側から電極を取り出すため
の深いエツチング溝を形成する必要がなく、表面段差を
小にすることができる。
Since a Mayu horizontal injection type junction stripe laser is used, there is no need to form a deep etching groove to take out the electrode from the bottom of the laser as in the conventional case, and the surface level difference can be reduced. .

ま之トランジスタにおいて傾斜バンドギャップベース構
造としたために、電流増幅率を高くすることができる。
Since the transistor has a sloped bandgap base structure, the current amplification factor can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の光・電子集積回路の実施例、第2図は
本発明及び従来例のバンドギャップ構成を示し、第3図
は従来例の構成を示す。 1・・・・・・半絶縁性基板GaAs 2・・・・・・第1の半導体層n −AL:l:Ga 
1−、A33・・・・・・第2の半導体層n−GaAs
又はAtyGa 1−yAs (x>−4・・・・・・
第3の半導体/# n −At工Ga□−□As5・・
・・・・第4の半導体M n”−GaAs6・・・・・
・第5の半導体)ili n −GaAs7・・・・・
・M6の半導体層p −At2Ga1−2’As8・・
・・・・第7の半導体ノーn −At2Ga1−、As
9・・・・・・第8の半導体層n”−GaAs10・・
・・・・高@度不純物唄域 11・・・・・・p+領領 域2・・・・・・再拡散領域 13、13’・・・イオン注入絶縁領域第1囚 第2図 (a) ベース       イI千 (b)    ”’″′辛 イ1+携畦1″N!
FIG. 1 shows an embodiment of the opto-electronic integrated circuit of the present invention, FIG. 2 shows the bandgap configuration of the present invention and the conventional example, and FIG. 3 shows the configuration of the conventional example. 1...Semi-insulating substrate GaAs 2...First semiconductor layer n-AL:l:Ga
1-, A33... Second semiconductor layer n-GaAs
or AtyGa 1-yAs (x>-4...
Third semiconductor/#n-At engineering Ga□-□As5...
...Fourth semiconductor Mn"-GaAs6...
・Fifth semiconductor) ili n -GaAs7...
・M6 semiconductor layer p-At2Ga1-2'As8...
...Seventh semiconductor node n -At2Ga1-, As
9...Eighth semiconductor layer n"-GaAs10...
...High @ degree impurity region 11 ... P+ region 2 ... Rediffusion region 13, 13' ... Ion implantation insulation region 1st cell Fig. 2 (a) Base I 1,000 (b) ``''''Spicy 1 + Portable 1''N!

Claims (12)

【特許請求の範囲】[Claims] (1)半絶縁性基板上に、第1導電型の第1の半導体層
、第1の半導体層に比してナロウギヤツプである第1導
電型の第2の半導体層、第2の半導体層に比してワイド
ギャップである第1導電型の第3の半導体層が順次積層
された第1の多層エピタキシャル膜に、第2の半導体層
を活性層、第1及び第3の半導体層をクラッド層とする
横型接合ストライプレーザが構成され、前記の第1の多
層エピタキシャル膜上に第1導電型の高濃度不純物を有
する第4の半導体層、及び第1導電量の第5の半導体層
、第2導電型の第6の半導体層、第6の半導体層に比し
てワイドギャップである第1導電型の第7の半導体層、
第1導電型の高濃度不純物を有する第8の半導体層が順
欠積層された第2の多層エピタキシャル膜に、第5の半
導体層をコレクタ、第6、第7、第8の半導体層内に形
成された第2導電型の高濃度不純物領域をベースコンタ
クト領域、第6の半導体層内のベースコンタクト領域以
外をベース、第7の半導体層内のベースコンタクト領域
以外をエミッタとするヘテロ接合バイポーラトランジス
タが構成されることを特徴とする光・電子集積回路。
(1) A first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type having a narrow gap compared to the first semiconductor layer, and a second semiconductor layer on a semi-insulating substrate. A first multilayer epitaxial film in which a third semiconductor layer of a first conductivity type with a wide gap is sequentially laminated, the second semiconductor layer is an active layer, and the first and third semiconductor layers are cladding layers. A lateral junction stripe laser is configured, in which a fourth semiconductor layer having a first conductivity type and a high concentration impurity is formed on the first multilayer epitaxial film, a fifth semiconductor layer having a first conductivity amount, and a second semiconductor layer having a first conductivity type and a high concentration impurity. a sixth semiconductor layer of a conductivity type; a seventh semiconductor layer of a first conductivity type having a wider gap than the sixth semiconductor layer;
A second multilayer epitaxial film in which an eighth semiconductor layer having a high concentration of impurity of the first conductivity type is laminated in sequence, a fifth semiconductor layer is placed in the collector, and a fifth semiconductor layer is placed in the sixth, seventh, and eighth semiconductor layers. A heterojunction bipolar transistor in which the formed high concentration impurity region of the second conductivity type is used as a base contact region, a portion other than the base contact region in the sixth semiconductor layer is used as a base, and a portion other than the base contact region in the seventh semiconductor layer is used as an emitter. An optical/electronic integrated circuit characterized by comprising:
(2)第1導電型がn型、第2導電型がp型であること
を特徴とする特許請求の範囲第1項記載の光・電子集積
回路。
(2) The opto-electronic integrated circuit according to claim 1, wherein the first conductivity type is n type and the second conductivity type is p type.
(3)第1、第3、第7の半導体層がAlGaAs、第
2、第4、第5、第8の半導体層がGaAs、第6の半
導体層がGaAs或いはAlGaAsであることを特徴
とする特許請求の範囲第1項記載の光・電子集積回路。
(3) The first, third, and seventh semiconductor layers are AlGaAs, the second, fourth, fifth, and eighth semiconductor layers are GaAs, and the sixth semiconductor layer is GaAs or AlGaAs. An optical/electronic integrated circuit according to claim 1.
(4)第1、第3、第7の半導体層がInP、第2、第
4、第5、第8の半導体層がInGaAs又はInGa
AsP、第6の半導体層がInP又はInGaAs又は
InGaAsPであることを特徴とする特許請求の範囲
第1項記載の光・電子集積回路。
(4) The first, third, and seventh semiconductor layers are InP, and the second, fourth, fifth, and eighth semiconductor layers are InGaAs or InGa.
2. The opto-electronic integrated circuit according to claim 1, wherein the sixth semiconductor layer is InP, InGaAs, or InGaAsP.
(5)第6の半導体層が、第5の半導体層との接続部分
でのAl組成が0、第7の半導体層との接続部分でのA
l組成が第7の半導体層のAl組成に等しくなるように
、Al組成が順次変化するAlGaAsであることを特
徴とする特許請求の範囲第3項記載の光・電子集積回路
(5) The sixth semiconductor layer has an Al composition of 0 at the connection part with the fifth semiconductor layer and an Al composition of A at the connection part with the seventh semiconductor layer.
4. The opto-electronic integrated circuit according to claim 3, wherein the optical/electronic integrated circuit is made of AlGaAs in which the Al composition changes sequentially so that the l composition is equal to the Al composition of the seventh semiconductor layer.
(6)半絶縁性基板がGaAs或いはInPであること
を特徴とする特許請求の範囲第1項記載の光・電子集積
回路。
(6) The opto-electronic integrated circuit according to claim 1, wherein the semi-insulating substrate is GaAs or InP.
(7)半絶縁性基板上に、第1導電型の第1の半導体層
、第1の半導体層に比してナロウギヤツプである第1導
電型の第2の半導体層、第2の半導体層に比してワイド
ギャップである第1導電型の第3の半導体層を順次積層
して第1の多層エピタキシャル膜を形成し、第1の多層
エピタキシャル膜内に、第2の半導体層を活性層、第1
及び第3の半導体層をクラッド層とする横型接合ストラ
イプレーザを構成し、第1の多層エピタキシャル膜上に
第1導電型の高濃度不純物を有する第4の半導体層、第
1導電型の第5の半導体層、第2導電型の第6の半導体
層、第6の半導体層に比してワイドギャップである第1
導電型の第7の半導体層、第1導電型の高濃度不純物を
有する第8の半導体層を順次積層して第2の多層エピタ
キシャル膜を形成し、第6、第7、第8の半導体層内に
イオン注入或いは気相拡散法を用いて第2導電型の高濃
度不純物領域を選択的に形成し、第5の半導体層をコレ
クタ、第6、第7、第8の半導体層内に形成された第2
導電型の高濃度不純物領域をベースコンタクト領域、第
6の半導体層内のベースコンタクト領域以外をベース、
第7の半導体層内のベースコンタクト領域以外をエミッ
タとするヘテロ接合バイポーラトランジスタを構成する
ことを特徴とする光・電子集積回路の製造方法。
(7) A first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type having a narrow gap compared to the first semiconductor layer, and a second semiconductor layer on a semi-insulating substrate. A first multilayer epitaxial film is formed by sequentially stacking a third semiconductor layer of a first conductivity type with a wide gap compared to the first multilayer epitaxial film. 1st
and a lateral junction stripe laser having a third semiconductor layer as a cladding layer, a fourth semiconductor layer having a high concentration impurity of the first conductivity type on the first multilayer epitaxial film, and a fifth semiconductor layer of the first conductivity type. a semiconductor layer of the second conductivity type, a sixth semiconductor layer of the second conductivity type, and a first semiconductor layer having a wider gap than the sixth semiconductor layer.
A second multilayer epitaxial film is formed by sequentially stacking a seventh semiconductor layer of a conductivity type and an eighth semiconductor layer having a high concentration of impurities of a first conductivity type, and a sixth, seventh, and eighth semiconductor layer are formed. A second conductivity type high concentration impurity region is selectively formed within the collector, sixth, seventh, and eighth semiconductor layers using ion implantation or vapor phase diffusion, and a fifth semiconductor layer is formed within the collector, sixth, seventh, and eighth semiconductor layers. The second
The high concentration impurity region of the conductivity type is a base contact region, the area other than the base contact region in the sixth semiconductor layer is a base,
A method for manufacturing an opto-electronic integrated circuit, comprising configuring a heterojunction bipolar transistor having an emitter in a region other than the base contact region in the seventh semiconductor layer.
(8)第1導電型がn型、第2導電型がp型であること
を特徴とする特許請求の範囲第7項記載の光・電子集積
回路の製造方法。
(8) The method for manufacturing an optoelectronic integrated circuit according to claim 7, wherein the first conductivity type is n type and the second conductivity type is p type.
(9)第1、第3、第7の半導体層がAlGaAs、第
2、第4、第5、第8の半導体層がGaAs、第6の半
導体層がGaAs或いはAlGaAsであることを特徴
とする特許請求の範囲第7項記載の光・電子集積回路の
製造方法。
(9) The first, third, and seventh semiconductor layers are AlGaAs, the second, fourth, fifth, and eighth semiconductor layers are GaAs, and the sixth semiconductor layer is GaAs or AlGaAs. A method for manufacturing an opto-electronic integrated circuit according to claim 7.
(10)第1、第3、第7の半導体層がInP、第2、
第4、第5、第8の半導体層がInGaAs又はInG
aAsP、第6の半導体層がInP又はInGaAs又
はInGaAsPであることを特徴とする特許請求の範
囲第7項記載の光・電子集積回路の製造方法。
(10) The first, third, and seventh semiconductor layers are InP;
The fourth, fifth, and eighth semiconductor layers are InGaAs or InG.
8. The method of manufacturing an opto-electronic integrated circuit according to claim 7, wherein the aAsP and the sixth semiconductor layer are InP, InGaAs, or InGaAsP.
(11)第6の半導体層が、第5の半導体層との接続部
分でのAl組成が0、第7の半導体層との接続部分での
Al組成が第7の半導体層のAl組成に等しくなるよう
に、Al組成が順次変化するAlGaAsであることを
特徴とする特許請求の範囲第9項記載の光・電子集積回
路の製造方法。
(11) The Al composition of the sixth semiconductor layer is 0 at the connection part with the fifth semiconductor layer, and the Al composition of the sixth semiconductor layer is equal to the Al composition of the seventh semiconductor layer. 10. The method of manufacturing an opto-electronic integrated circuit according to claim 9, wherein the Al GaAs is used in which the Al composition changes sequentially so that the Al composition changes sequentially.
(12)半絶縁性基板がGaAs或いはInPであるこ
とを特徴とする特許請求の範囲第7項記載の光・電子集
積回路の製造方法。
(12) The method for manufacturing an opto-electronic integrated circuit according to claim 7, wherein the semi-insulating substrate is GaAs or InP.
JP10776286A 1986-05-13 1986-05-13 Optical-electronic integrated circuit and manufacture thereof Pending JPS62264661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10776286A JPS62264661A (en) 1986-05-13 1986-05-13 Optical-electronic integrated circuit and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10776286A JPS62264661A (en) 1986-05-13 1986-05-13 Optical-electronic integrated circuit and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS62264661A true JPS62264661A (en) 1987-11-17

Family

ID=14467349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10776286A Pending JPS62264661A (en) 1986-05-13 1986-05-13 Optical-electronic integrated circuit and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS62264661A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096160A (en) * 2005-09-30 2007-04-12 Oki Data Corp Semiconductor composite device, printer head using the same, and image forming apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756792A (en) * 1980-09-24 1982-04-05 Tokyo Shibaura Electric Co Fuel assembly with measuring cord
JPS57197862A (en) * 1981-05-29 1982-12-04 Fujitsu Ltd Active semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756792A (en) * 1980-09-24 1982-04-05 Tokyo Shibaura Electric Co Fuel assembly with measuring cord
JPS57197862A (en) * 1981-05-29 1982-12-04 Fujitsu Ltd Active semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096160A (en) * 2005-09-30 2007-04-12 Oki Data Corp Semiconductor composite device, printer head using the same, and image forming apparatus

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