JP2780275B2 - Embedded semiconductor laser - Google Patents
Embedded semiconductor laserInfo
- Publication number
- JP2780275B2 JP2780275B2 JP63219361A JP21936188A JP2780275B2 JP 2780275 B2 JP2780275 B2 JP 2780275B2 JP 63219361 A JP63219361 A JP 63219361A JP 21936188 A JP21936188 A JP 21936188A JP 2780275 B2 JP2780275 B2 JP 2780275B2
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- Japan
- Prior art keywords
- layer
- current
- semiconductor laser
- buried
- type
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Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は光通信や光情報処理に用いられる半導体レー
ザに関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor laser used for optical communication and optical information processing.
(従来の技術とその問題点) 半導体レーザは光通信や光情報処理に用いられるキー
デバイスの一つであり、高速の変調特性を持ち、かつ高
い効率で発振することが期待されている。しかし、従来
の半導体レーザでは上記2つの特性をともに満足するこ
とが困難であった。以下、従来製作されてきた半導体レ
ーザの問題点を先ず述べ、次にこれらの問題点を改善す
る目的で試みられている第2の従来技術の残されている
問題点について説明する。(Prior art and its problems) A semiconductor laser is one of key devices used for optical communication and optical information processing, and is expected to have high-speed modulation characteristics and oscillate with high efficiency. However, it has been difficult for a conventional semiconductor laser to satisfy both of the above two characteristics. Hereinafter, the problems of the conventionally manufactured semiconductor laser will be described first, and then the remaining problems of the second prior art which has been attempted to improve these problems will be described.
従来製作されている代表的な半導体レーザとして、2
重溝平面埋込み構造半導体レーザ(Double Channel Pla
nar Buried Heterostructure Laser Diode:略称DC−PBH
LD)があり、ジャーナル・オブ・ライトウェーブ・テ
クノロジー、LT−1巻、1983年3月号、195−202頁に詳
述されている。この半導体レーザは、第2図(a)のよ
うに溝部分をpnpn構成にし、埋込み界面に形成されるpn
接合の接合電位により電流を阻止するようになってい
る。この構造に代表されるpn接合の接合電位による電流
阻止構造は接合に電圧が直接印加されるため、接合への
印加電圧が高く接合を横切って流れる電流が大きくなり
やすい点、及びpn接合が10pF以上の静電容量を有するた
め10Gb/s近い高速変調は困難であるという問題点があっ
た。Conventionally manufactured typical semiconductor lasers include 2
Double Channel Pla
nar Buried Heterostructure Laser Diode: DC-PBH
LD), which is described in detail in Journal of Lightwave Technology, LT-1, Vol. 1983, March 1983, pp. 195-202. This semiconductor laser has a pnpn structure in a groove portion as shown in FIG.
The current is blocked by the junction potential of the junction. In a current blocking structure based on the junction potential of a pn junction represented by this structure, since a voltage is directly applied to the junction, the voltage applied to the junction is high and the current flowing across the junction is likely to be large, and the pn junction is 10 pF There is a problem that high-speed modulation near 10 Gb / s is difficult due to the above-mentioned capacitance.
次に、これらの問題点を改善するため、図2(b)の
ように活性領域の両脇を深い準位をつくる不純物を含ん
だ半絶縁性半導体層で埋込んだ半導体レーザが開発され
ている。Next, in order to solve these problems, a semiconductor laser in which both sides of an active region are buried with a semi-insulating semiconductor layer containing an impurity for forming a deep level as shown in FIG. 2B has been developed. I have.
この半導体レーザの作製例は、エレクトロニクス・レ
ターズ(Electron.Lett.22巻(1986年1214頁)に記載さ
れている。この従来の第2の半導体レーザにおいては、
p層とn層とが高抵抗埋込層を介しているため、従来の
第1の半導体レーザに比べ低容量で高速変調特性が大幅
に改善されている。しかし、この従来素子では、素子に
印加する電圧を高くすると、埋込み層に電流が流れ発振
効率が減少する問題点があった。An example of manufacturing this semiconductor laser is described in Electronics Letters (Electron. Lett., Vol. 22, 1986, page 1214).
Since the p-layer and the n-layer are interposed through the high-resistance buried layer, the capacity and the high-speed modulation characteristic are significantly improved compared to the conventional first semiconductor laser. However, this conventional device has a problem that when the voltage applied to the device is increased, a current flows through the buried layer and the oscillation efficiency is reduced.
本発明の目的は、上記の従来の問題点である埋め込み
層中の電流を殆ど零にし、高速変調特性および発振効率
ともに優れた半導体レーザを提供することである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor laser in which the current in the buried layer, which is a conventional problem described above, is reduced to almost zero, and high-speed modulation characteristics and oscillation efficiency are excellent.
(問題点を解決するための手段) 本発明は、活性領域の上側と下側を各々第1導電形及
び第2導電形のクラッド層により挟んだメサ状の電流通
電部と、電流通電部の両側を深い不純物準位を有する半
導体からなる電流阻止層で埋込んだ構造を有する埋込み
構造半導体レーザにおいて、前記活性領域と少なくとも
一方の導電形の前記クラッド層とに接する位置に、禁制
帯幅が前記活性領域およびクラッド層の禁制帯幅よりも
常に大きい半導体からなるバンドギャップバリア層を前
記電流通電部と前記電流阻止層の間に設けたことを特徴
とする。(Means for Solving the Problems) The present invention provides a mesa-shaped current-carrying part in which the upper and lower sides of an active region are sandwiched by cladding layers of a first conductivity type and a second conductivity-type, respectively. In a buried structure semiconductor laser having a structure in which both sides are buried with a current blocking layer made of a semiconductor having a deep impurity level, a forbidden band width is provided at a position in contact with the active region and the cladding layer of at least one conductivity type. A band gap barrier layer made of a semiconductor that is always larger than the forbidden band width of the active region and the cladding layer is provided between the current conducting portion and the current blocking layer.
第2の発明は、前記バンドギャップバリア層が互いに
格子定数の異なる膜を積層した多重膜構造であることを
特徴とする。A second invention is characterized in that the bandgap barrier layer has a multi-layer structure in which films having different lattice constants are stacked.
第3の発明は、前記バンドギャップバリア層がInGaP
層であることを特徴とする。In a third aspect, the band gap barrier layer is made of InGaP.
Characterized in that it is a layer.
(発明の作用・原理) 本発明の作用・原理について図面を参照しながら説明
する。(Operation and Principle of the Invention) The operation and principle of the present invention will be described with reference to the drawings.
本発明の半導体レーザは、第1図に示したように、活
性領域11をp形クラッド層12とn形クラッド層13とで挟
んだメサ状の電流通電部を、深い不純物準位を有する半
導体層からなる電流阻止層14で埋込み、かつ少なくとも
活性領域11およびp形クラッド層12と接する部分の禁制
帯幅が、活性領域11およびp形クラッド層12の禁制帯幅
よりもそれぞれの部分において常に大きな電流阻止層部
分15を設けた点が特徴である。16は基板、17は電極であ
る。これに対し、従来の第1の半導体レーザでは、第2
図(a)のように活性層11、p形クラッド層12、n形ク
ラッド層からなるメサ状電流通電部をp形埋込み層21で
埋め込んだ基本構成をもつ。このとき、活性領域以外を
流れるもれ電流は、印加電圧がp形埋込み層21とn形ク
ラッド層13に殆ど直接印加されるため、pn接合を横切る
電流23が、無視出来ない程度になる。特にn形埋込み層
22が存在する場合、p形埋込み層21とn形クラッド層13
の層構成がnpnトランジスタ作用によりもれ電流を増幅
する恐れがあった。このため、p形埋込み層21中を2重
溝の外側へ流れる電流24を設けてpn接合への電圧印加を
緩和する工夫がなされている。しかし2重溝の外側へ流
れる電流24がもれ電流として増える問題点が従来あっ
た。また、埋込み層のpn接合容量が大きいため素子容量
を小さくできなかった。As shown in FIG. 1, the semiconductor laser according to the present invention includes a mesa-shaped current-carrying portion in which an active region 11 is sandwiched between a p-type cladding layer 12 and an n-type cladding layer 13 by a semiconductor having a deep impurity level. The band gap buried in the current blocking layer 14 and at least in contact with the active region 11 and the p-type cladding layer 12 is always smaller in each part than the band gap of the active region 11 and the p-type cladding layer 12. The feature is that a large current blocking layer portion 15 is provided. 16 is a substrate and 17 is an electrode. On the other hand, in the conventional first semiconductor laser, the second
As shown in FIG. 1A, the element has a basic structure in which a mesa-shaped current-carrying portion including an active layer 11, a p-type cladding layer 12, and an n-type cladding layer is buried with a p-type buried layer 21. At this time, the leakage current flowing outside the active region is almost directly applied to the p-type buried layer 21 and the n-type cladding layer 13, so that the current 23 crossing the pn junction is not negligible. Especially n-type buried layer
When the p-type buried layer 21 and the n-type cladding layer 13 are present,
There is a fear that the layer structure of this may leak due to the action of the npn transistor and amplify the current. For this reason, the current 24 flowing in the p-type buried layer 21 to the outside of the double groove is provided to reduce the voltage application to the pn junction. However, there has been a problem that the current 24 flowing outside the double groove leaks and increases as a current. Also, the pn junction capacitance of the buried layer was large, so that the device capacitance could not be reduced.
第2の従来例では第2図(b)のように深い不純物準
位を有する電流阻止層14を埋め込んだ構成が形成されて
いる。この結果、電圧は電流阻止層中に順次印加される
ため、接合容量に関する問題点は大幅に改善された。し
かし第2の従来例では、電流阻止層の禁制帯幅はp型ク
ラッド層やn形クラッド層と等しく、かつ電子捕獲型の
深い不純物準位を有する半絶縁性半導体が電流阻止層と
して使われていた。この場合、電流阻止層に用いた半導
体層単独では、極めて高抵抗であるにもかかわらず、第
2図(b)のようなレーザ構造中では全電流の10%前後
のもれ電流24がある問題点が残されていた。このもれ電
流25の発生原因は、電流阻止層14のp形クラッド層12と
接する近傍において、不純物に捕獲された電子の負電荷
に向けてp形クラッド層12中の正孔が引きよせられ、正
孔濃度とともに電子濃度も高い領域がp形クラッド層両
脇に生じるためである。即ち正孔が不純物に捕獲されな
いことから起因している。In the second conventional example, a structure in which a current blocking layer 14 having a deep impurity level is buried as shown in FIG. 2B is formed. As a result, since the voltage is sequentially applied to the current blocking layer, the problem relating to the junction capacitance is greatly improved. However, in the second conventional example, the band gap of the current blocking layer is equal to that of the p-type cladding layer or the n-type cladding layer, and a semi-insulating semiconductor having an electron trapping type deep impurity level is used as the current blocking layer. I was In this case, although the semiconductor layer used alone as the current blocking layer has an extremely high resistance, the leakage current 24 is about 10% of the total current in the laser structure as shown in FIG. 2B. The problem remained. The cause of the leakage current 25 is that the holes in the p-type cladding layer 12 are attracted to the negative charges of the electrons trapped by the impurities in the vicinity of the current blocking layer 14 in contact with the p-type cladding layer 12. This is because regions having both a high hole concentration and a high electron concentration are formed on both sides of the p-type cladding layer. That is, this is because holes are not captured by impurities.
本発明では、このもれ電流の発生原因を取除くため、
p形クラッド層12および活性領域11中の高濃度の正孔が
電流阻止層中に流入することを妨げかつn形クラッド層
13や活性領域11からの電子の流入を防ぐ層構造を本素子
に導入した。すなわち、本発明では少なくとも正孔が流
入する恐れのある領域近傍において、禁制帯幅がp形ク
ラッド層12や活性領域11の禁制帯幅よりも常に大きい電
流阻止層領域としてバンドギャップバリア層15を導入し
た。これに加えてn型クラッド層からの電子の流入も減
少させるためn型クラッド層と接する領域に対しても、
禁制帯幅がn型のクラッド層の禁制帯幅よりも大きい薄
膜バンドギャップバリア層15を設けると、もれ電流を更
に減少できる。このバンドギャップバリア層15界面にお
ける禁制帯幅差はわずかなものでも室温の温度エネルギ
ー0.025eV程度以上あれば十分バリアとして働くため、
もれ電流成分24は極めて減少する。In the present invention, in order to remove the cause of the leakage current,
High concentration holes in the p-type cladding layer 12 and the active region 11 are prevented from flowing into the current blocking layer and the n-type cladding layer
A layer structure for preventing electrons from flowing from the active region 13 and the active region 11 was introduced into this device. That is, in the present invention, the band gap barrier layer 15 is used as a current blocking layer region in which the forbidden band width is always larger than the forbidden band width of the p-type cladding layer 12 or the active region 11 at least in the vicinity of the region where holes may flow. Introduced. In addition, in order to reduce the inflow of electrons from the n-type cladding layer, also in the region in contact with the n-type cladding layer,
By providing the thin-film bandgap barrier layer 15 whose forbidden band width is larger than the forbidden band width of the n-type cladding layer, the leakage current can be further reduced. Even if the difference in the forbidden band width at the interface of the bandgap barrier layer 15 is small, if the temperature energy at room temperature is about 0.025 eV or more, it works as a sufficient barrier,
The leakage current component 24 is extremely reduced.
また正孔捕獲型の深い不純物準位を有する半導体を電
流阻止層14に用いた場合も、同様に捕獲されない電子が
流入する恐れのある領域近傍に、禁制帯幅のより大きな
バンドギャップバリア層15を設けてやればよい。すなわ
ち電流阻止層が活性領域及びn形クラッド層と接する部
分にバンドギャップバリア層を設ければ、従来に比べて
もれ電流を減少できる。更にもれ電流低域をより効果的
にするためにはそのバンドギャップバリア層15を、p型
クラッド層を含めた電流通電部の全面に設けてやればよ
い。Also, when a semiconductor having a deep impurity level of a hole trapping type is used for the current blocking layer 14, a band gap barrier layer 15 having a larger forbidden band width is similarly provided in the vicinity of a region where electrons not trapped may flow. Should be provided. That is, if a bandgap barrier layer is provided at a portion where the current blocking layer contacts the active region and the n-type cladding layer, the leakage current can be reduced as compared with the conventional case. Further, in order to make the leakage current low region more effective, the band gap barrier layer 15 may be provided on the entire surface of the current carrying portion including the p-type cladding layer.
次に本発明の第2の発明の作用について説明する。埋
込み構造半導体レーザとして代表的なInGaAsP/InP系半
導体レーザに本発明のバンドギャップバリア層15を導入
しようとするとき、クラッド層のInPより禁制帯の大き
な材料としてInGaPが考えられる。しかし、InGaPの格子
定数はGa成分が増えるにつれInPの格子定数より減少す
るため、膜成長において転位が生じ厚膜を成長するのが
難しい問題点があった。本発明はバンドギャップバリア
層構造を多層膜構造とすることで上記の問題点を軽減し
ようとするものである。すなわち、電流通電部側にInP
より広禁制帯幅で格子定数がInPより小さなInGaP層の薄
膜を形成し、引きつづき格子定数の大きな層と小さな層
を組み合せ多層構造にすることで、転位の発生を回避す
ることができる。すなわち、多層構造の場合、格子不整
合の歪みを隣接層間で吸収するファクターがあるため、
転位の少ない膜成長ができる。Next, the operation of the second invention of the present invention will be described. When trying to introduce the band gap barrier layer 15 of the present invention into an InGaAsP / InP-based semiconductor laser which is a typical buried structure semiconductor laser, InGaP is considered as a material having a larger forbidden band than InP of the cladding layer. However, the lattice constant of InGaP decreases from the lattice constant of InP as the Ga component increases, so that there is a problem that dislocations occur in the film growth and it is difficult to grow a thick film. The present invention is intended to alleviate the above-mentioned problems by making the band gap barrier layer structure a multilayer film structure. In other words, InP
By forming a thin film of an InGaP layer having a wider bandgap and a lattice constant smaller than that of InP, and subsequently combining a layer having a large lattice constant and a layer having a small lattice constant to form a multilayer structure, dislocations can be avoided. In other words, in the case of a multilayer structure, there is a factor that absorbs lattice mismatch distortion between adjacent layers.
Film growth with few dislocations can be achieved.
以下、本発明について実施例をあげ更に詳しく説明す
る。Hereinafter, the present invention will be described in more detail with reference to examples.
(実施例1) 本発明の第1の実施例の概略構造は第1図のものと同
じである。本実施例では先ずn形InP基板16の上にn形I
nPクラッド層13、波長1.3μm組成InGaAsP活性層11、p
形InPクラッド層12を順次成長し、通常のエッチング工
程に従って深さ約2.5μm幅10μmの溝を活性領域幅1.5
μmの逆メサ状電流通電部の両側に形成した。次いでバ
ンドギャップバリア層15としてInPの禁制帯幅1.35eVよ
りも大きな禁制帯幅を持つInGaP層をメサ状電流通電部
の側壁に成長した。InGaPの膜厚は格子定数の不整合下
での許容できる範囲の厚さに成長した。本実施例では禁
制帯幅が1.7eVのIn0.6Ga0.4P層を成長し膜厚は0.05μ
mであった。成長方法は気相成長法を用いた。この成長
方法においては、結晶面による成長速度が異なる特性が
あるため、溝の側面に選択的に成長が可能である。本実
施例では逆メサ形状電流通電部のp型クラッド層12部分
に露出させた結晶面は成長速度の大きなA面であり、一
方素子表面等は成長速度の極めて遅い(001)面である
ため、InGaPのメサ側面への選択成長が容易に行なえ
た。その後、第2の従来例と同様に、電子捕獲型の深い
不純物準位を有する鉄(Fe)をドープしたInPを溝全面
に埋込み平面埋込み形の半導体レーザを作製した。Embodiment 1 The schematic structure of the first embodiment of the present invention is the same as that of FIG. In this embodiment, first, an n-type I
nP cladding layer 13, wavelength 1.3 μm composition InGaAsP active layer 11, p
An InP cladding layer 12 is sequentially grown, and a groove having a depth of about 2.5 μm and a width of 10 μm is formed in accordance with a normal etching process.
It was formed on both sides of a μm inverted mesa current conducting portion. Next, as a bandgap barrier layer 15, an InGaP layer having a forbidden band width larger than the forbidden band width of InP of 1.35 eV was grown on the side wall of the mesa-shaped current conducting portion. The thickness of InGaP grew to an acceptable range under lattice mismatch. In this embodiment, an In 0.6 Ga 0.4 P layer having a forbidden band width of 1.7 eV is grown to a thickness of 0.05 μm.
m. As a growth method, a vapor phase growth method was used. In this growth method, since the growth rate varies depending on the crystal plane, the growth can be selectively performed on the side surface of the groove. In this embodiment, the crystal face exposed on the p-type cladding layer 12 of the reverse-mesa-shaped current-carrying portion is the A-plane having a high growth rate, while the element surface is the (001) plane having a very low growth rate. InGaP was easily grown selectively on the mesa side. Thereafter, similarly to the second conventional example, an electron trapping type InP doped with iron (Fe) having a deep impurity level is buried in the entire surface of the groove to produce a planar buried semiconductor laser.
この結果、本実施例では第3図実線31のように、もれ
電流の全電流に占める割合(もれ電流比)は、活性領域
の電流密度が2KA/cm2付近で約2%であることが計算機
シミュレーションにより示された。このもれ電流比は第
3図破線41に示す第1の従来素子のもれ電流比見積り値
約30%や、第3図一点鎖線42に示す第2の従来素子のも
れ電流比見積値約8%に比べ大幅に減少しており、実験
でももれ電流が小さいことが確認された。なお本実施例
ではInGaP層5およびInP電流阻止層には、電子捕獲型の
Fe不純物をドープし、そのトラップ濃度はいずれも5×
1015cm-3と設定した。また、このトラップ濃度を2×10
15cm-3から2×1016cm-3まで変えた場合ももれ電流比は
同様に小さかった。なおワイドギャップ電流阻止層部分
はFe以外の電子捕獲型の不純物をドープしても良いし、
アンドープでも良い。この結果本実施例では従来に比べ
高効率で発振ししかも高速変調が可能となった。As a result, in this embodiment, as shown by the solid line 31 in FIG. 3, the ratio of the leakage current to the total current (leakage current ratio) is about 2% when the current density in the active region is around 2 KA / cm 2. This was shown by computer simulation. The leakage current ratio is approximately 30%, which is the estimated value of the leakage current ratio of the first conventional element shown by the broken line 41 in FIG. 3, or the estimated value of the leakage current ratio of the second conventional element, shown by the dashed line 42 in FIG. It is much smaller than about 8%, and it was confirmed in experiments that the leakage current was small. In this embodiment, the InGaP layer 5 and the InP current blocking layer have an electron trapping type.
Doped with Fe impurities, the trap concentration of which is 5 ×
It was set to 10 15 cm -3 . In addition, this trap concentration is set to 2 × 10
The leakage current ratio was similarly small when changing from 15 cm −3 to 2 × 10 16 cm −3 . The wide gap current blocking layer may be doped with an electron trapping type impurity other than Fe.
It may be undoped. As a result, in this embodiment, oscillation was performed with higher efficiency than in the prior art, and high-speed modulation was possible.
(実施例2) 第4図は第2の実施例を示す素子概略断面図である。
実施例1とは基本構造は同じであるが、電流阻止層44の
半導体層が電子捕獲型のかわりに正孔捕獲型となってい
る。また、p形基板、およびクラッド層のp形とn形の
導電形が実施例1の場合と入替っている。正孔捕獲型の
深い不純物として本実施例ではTiをドープした。このと
き、nクラッド層13と活性領域11の側壁にInGaP層の薄
膜を成長し、実施例1と同じく良好な電流ブロッキング
特性が得られた。また、Tiの替わりにCoやCrをドープし
た場合、更にはアンドープの場合でももれ電流が小さい
ことが確認された。Example 2 FIG. 4 is a schematic sectional view of an element showing a second example.
Although the basic structure is the same as that of the first embodiment, the semiconductor layer of the current blocking layer 44 is of a hole trapping type instead of an electron trapping type. Further, the p-type substrate and the p-type and n-type conductivity types of the cladding layer are replaced with those in the first embodiment. In this embodiment, Ti is doped as a hole trapping type deep impurity. At this time, a thin film of an InGaP layer was grown on the side walls of the n-cladding layer 13 and the active region 11, and good current blocking characteristics were obtained as in Example 1. Also, it was confirmed that leakage current was small even when Co or Cr was doped instead of Ti, or even when undoped.
なお上記実施例1及び2ではバンドギャップバリア層
15を電流阻止層44の側壁部分に形成したが、各々p形ク
ラッド層及び活性層とn形クラッド層及び活性層と接す
る側壁部分のみに設ければ発明の効果は充分得られる。In Examples 1 and 2, the band gap barrier layer was used.
Although 15 is formed on the side wall portion of the current blocking layer 44, the effect of the present invention can be sufficiently obtained if it is provided only on the side wall portion in contact with the p-type cladding layer and the active layer and the n-type cladding layer and the active layer.
(実施例3) 第5図は第3の実施例を示す素子概略断面図である。
実施例1とは基本構造は同じであるが、バンドギャップ
バリア層15をメサ両脇の溝全面に成長した点が異なって
いる。成長方法は有機金属気相成長(MOCVD)法を用い
た。この成長方法においては、結晶面による成長速度依
存が小さいため、溝の全面に成長が可能である。本実施
例では逆メサ形状電流通電部の溝全面に、InGaPの成長
が容易に行なえた。その後、第2の従来例と同様に、電
子捕獲型の深い不純物準位を有する鉄(Fe)をドープし
たInPを溝全面に埋込み平面埋込み形の半導体レーザを
作製した。Example 3 FIG. 5 is a schematic sectional view of an element showing a third example.
The basic structure is the same as that of the first embodiment, except that the band gap barrier layer 15 is grown on the entire surface of the groove on both sides of the mesa. As a growth method, a metal organic chemical vapor deposition (MOCVD) method was used. In this growth method, the growth rate depends on the crystal plane is small, so that the entire surface of the groove can be grown. In this example, InGaP could be easily grown on the entire surface of the groove of the reverse-mesa-shaped current conducting portion. Thereafter, similarly to the second conventional example, an electron trapping type InP doped with iron (Fe) having a deep impurity level is buried in the entire surface of the groove to produce a planar buried semiconductor laser.
この結果、本実施例では第3図実線32のように、もれ
電流の全電流に占める割合(もれ電流比)は、活性領域
の電流密度が2KA/cm2付近で1%よりも小さく殆ど零で
あることが計算機シミュレーションにより示された。こ
のもれ電流比は第3図破線41に示す第1の従来素子のも
れ電流比見積り値約30%や、第3図一点鎖線42に示す第
2の従来素子のもれ電流比見積値約8%に比べ大幅に減
少しており、実験でももれ電流が小さいことが確認され
た。なお本実施例ではInGaP層15およびInP電流阻止層に
は、電子捕獲型のFe不純物をドープし、そのトラップ濃
度はいずれも5×1015cm-3と設定した。また、このトラ
ップ濃度を2×1015cm-3から2×1016cm-3まで変えた場
合ももれ電流比は同様に小さかった。なおバンドギャッ
プ電流阻止層部分はFe以外の電子捕獲型の不純物をドー
プしても良いし、アンドープでも良い、この結果本実施
例では従来に比べ高効率で発振ししかも高速変調が可能
となった。As a result, in this embodiment, as shown by the solid line 32 in FIG. 3, the ratio of the leakage current to the total current (leakage current ratio) is smaller than 1% when the current density of the active region is around 2 KA / cm 2. Computer simulation showed that it was almost zero. The leakage current ratio is approximately 30%, which is the estimated value of the leakage current ratio of the first conventional element shown by the broken line 41 in FIG. 3, or the estimated value of the leakage current ratio of the second conventional element, shown by the dashed line 42 in FIG. It is much smaller than about 8%, and it was confirmed in experiments that the leakage current was small. In this example, the InGaP layer 15 and the InP current blocking layer were doped with an electron trapping type Fe impurity, and the trap concentration was set to 5 × 10 15 cm −3 . When the trap concentration was changed from 2 × 10 15 cm −3 to 2 × 10 16 cm −3, the leakage current ratio was similarly small. The band gap current blocking layer portion may be doped with an electron trapping type impurity other than Fe or may be undoped. As a result, in this embodiment, oscillation oscillated with higher efficiency than that of the conventional one and high-speed modulation was made possible. .
(実施例4) 第6図は第4の実施例を示す素子概略断面図である。
実施例3とは基本構造は同じであるが、電流阻止層44の
半導体層が電子捕獲型のかわりに正孔捕獲型となってい
る。また、p形基板、およびクラッド層のp形とn形の
導電形が実施例1の場合と入替っている。正孔捕獲型の
深い不純物として本実施例ではTiをドープした。このと
き、nクラッド層13と活性領域11の側壁にInGaP層の薄
膜を成長し、実施例1と同じく良好な電流ブロッキング
特性が得られた。またTiの替りに少なくともCo、Crのい
ずれかをドープした場合、更にはアンドープの場合でも
もれ電流が小さいことが確認された。Example 4 FIG. 6 is a schematic sectional view of an element showing a fourth example.
Although the basic structure is the same as that of the third embodiment, the semiconductor layer of the current blocking layer 44 is of a hole trap type instead of an electron trap type. Further, the p-type substrate and the p-type and n-type conductivity types of the cladding layer are replaced with those in the first embodiment. In this embodiment, Ti is doped as a hole trapping type deep impurity. At this time, a thin film of an InGaP layer was grown on the side walls of the n-cladding layer 13 and the active region 11, and good current blocking characteristics were obtained as in Example 1. It was also confirmed that the leakage current was small when at least one of Co and Cr was doped instead of Ti, and even when undoped.
(実施例5) 第7図は第2の発明の実施例を示す素子概略断面図で
ある。本実施例の基本構造は実施例3の基本構造(第5
図)と同じであるが、バンドギャップバリア層15が多重
膜構造71からなっている点が異なっており、特徴点であ
る。バンドギャップバリア層15材料としてInGaP層とInP
層を用いた。InGaP層はInP層と格子不整合があるが、例
えばIn0.6Ga0.4P組成の場合ワイドギャップ層は約0.01
5μmまでの膜厚であれば転位なして繰り返し積層する
ことが可能である。本実施例では成長方法として有機金
属気相成長法を用い、In0.6Ga0.4P層とInP層とを0.01
μmづつ10層を交互に成長した。本実施例では、この後
p形で低濃度のInP層を電流阻止層14として溝に埋込み
平坦埋込み構造の半導体レーザを作製した。この結果、
本実施例の半導体レーザのもれ電流は発振閾電流値付近
で十分小さく、かつ転位等による発振閾電流値の劣化等
が見られない良好な素子特性が得られた。また、本実施
例の電流阻止層14には半絶縁InP層を用いても勿論よ
い。本実施例ではn形InP基板の例を示したがp形InP基
板の場合も同時に多重膜構造バリア層15がもれ電流低域
に有効であった。上記実施例1〜5では、活性領域に波
長1.3μmで発振する組成のInGaAsPを用いたがこの組成
に限定されないのは明らかである。Embodiment 5 FIG. 7 is a schematic sectional view of an element showing an embodiment of the second invention. The basic structure of the present embodiment is the same as that of Embodiment 3 (fifth embodiment).
This is the same as FIG. 2 except that the bandgap barrier layer 15 has a multi-layer structure 71. InGaP layer and InP as band gap barrier layer 15 material
Layers were used. Although the InGaP layer has lattice mismatch with the InP layer, for example, in the case of In 0.6 Ga 0.4 P composition, the wide gap layer is about 0.01.
If the film thickness is up to 5 μm, it is possible to repeatedly laminate without dislocation. In this embodiment, metalorganic vapor phase epitaxy is used as a growth method, and the In 0.6 Ga 0.4 P layer and the InP layer
Ten μm layers were grown alternately. In this embodiment, a p-type low concentration InP layer is used as a current blocking layer 14 in the trench to fabricate a semiconductor laser having a flat buried structure. As a result,
The leakage current of the semiconductor laser of this example was sufficiently small near the oscillation threshold current value, and good device characteristics were obtained in which the oscillation threshold current value did not deteriorate due to dislocation or the like. In addition, a semi-insulating InP layer may of course be used for the current blocking layer 14 of this embodiment. In this embodiment, the example of the n-type InP substrate is shown. However, also in the case of the p-type InP substrate, the multi-layered structure barrier layer 15 simultaneously leaks and is effective in a low current region. In Examples 1 to 5, InGaAsP having a composition oscillating at a wavelength of 1.3 μm was used in the active region, but it is clear that the composition is not limited to this composition.
また上記実施例では、気相成長法による選択的膜形成
の例を示したが、成長方法は気相成長法に限らずガスソ
ース分子線エピタキシャル成長などの他の成長法を用い
てもよい。Further, in the above embodiment, an example of selective film formation by a vapor phase growth method has been described, but the growth method is not limited to the vapor phase growth method, and another growth method such as gas source molecular beam epitaxial growth may be used.
更に、上記実施例では、InP基板上のInGaAsP/InP材料
系が用いられたが、GaAs基板上のAlGaAs/GaAs材料系やA
lGaInP/GaInP材料系についても同様に適用が可能であ
る。Further, in the above embodiment, the InGaAsP / InP material system on the InP substrate was used.
The same applies to lGaInP / GaInP material systems.
(発明の効果) 本発明の半導体レーザは、従来素子に比べもれ電流を
殆ど零にでき従って高効率で発振し、かつ従来素子の改
善目的であった低容量化による高速変調も可能であり、
光通信や光情報処理の光源素子に適する。(Effect of the Invention) The semiconductor laser of the present invention can make the current almost zero as compared with the conventional device, oscillates with high efficiency, and can perform high-speed modulation by reducing the capacity, which was an object of improvement of the conventional device. ,
Suitable for light source devices for optical communication and optical information processing.
第1図は本発明の埋込み半導体レーザの第1の発明の素
子構造を示す斜視図、第2図(a)は第1の従来素子の
概略構造を示す断面図、第2図(b)は第2の従来素子
の概略構造を示す断面図、第3図は本発明素子、第1の
従来素子、第2の従来素子のもれ電流量と活性領域電流
密度の関係の計算機シミュレーション結果を示す図、第
4図は第2の実施例の素子構造を示す概略断面図、第5
図は第3の実施例の素子概略断面図、第6図は第4の実
施例の素子概略断面図、第7図は第2の発明の実施例の
素子概略断面図である。 11……活性領域、12……p形クラッド層、 13……n形クラッド層、14……電流阻止層、 15……バンドギャップバリア層、16……n形基板、 17……電極、21……p形埋込層、22……n形埋込層 23,24……第1の従来素子のもれ電流経路、 25……第2の従来素子のもれ電流経路、 31……本発明の実施例1の素子のもれ電流・電流密度関
係、 32……本発明の実施例3の素子のもれ電流・電流密度関
係 41……第1の従来素子のもれ電流・電流密度関係 42……第2の従来素子のもれ電流・電流密度関係、 43……p型基板、44……正孔捕獲形の電流阻止層 71……多重膜構造。FIG. 1 is a perspective view showing an element structure of a buried semiconductor laser according to the first invention of the present invention, FIG. 2 (a) is a sectional view showing a schematic structure of a first conventional element, and FIG. FIG. 3 is a cross-sectional view showing a schematic structure of a second conventional element, and FIG. 3 shows a computer simulation result of a relationship between a leakage current amount and an active region current density of the element of the present invention, the first conventional element, and the second conventional element. FIG. 4 is a schematic sectional view showing the element structure of the second embodiment, and FIG.
FIG. 6 is a schematic sectional view of the element of the third embodiment, FIG. 6 is a schematic sectional view of the element of the fourth embodiment, and FIG. 7 is a schematic sectional view of the element of the embodiment of the second invention. 11 active region, 12 p-type cladding layer, 13 n-type cladding layer, 14 current blocking layer, 15 band gap barrier layer, 16 n-type substrate, 17 electrode 21 ... p-type buried layer, 22 ... n-type buried layer 23, 24 ... leakage current path of the first conventional element, 25 ... leakage current path of the second conventional element, 31 ... Leakage current / current density relationship of the device according to the first embodiment of the present invention, 32: leakage current / current density relationship of the device of the third embodiment of the present invention 41 ... Leakage current / current density of the first conventional device Relationship 42: leakage current / current density relationship of the second conventional element 43: p-type substrate 44: hole trapping type current blocking layer 71: multi-layer structure.
Claims (3)
び第2導電形のクラッド層により挟んだメサ状の電流通
電部と、電流通電部の両側を深い不純物準位を有する半
導体からなる電流阻止層で埋込んだ構造を有する埋込み
構造半導体レーザにおいて、前記活性領域と少なくとも
一方の導電形の前記クラッド層とに接する位置に、禁制
帯幅が前記活性領域およびクラッド層の禁制帯幅よりも
常に大きい半導体からなるバンドギャップバリア層を前
記電流通電部と前記電流阻止層の間に設けたことを特徴
とする埋込み構造半導体レーザ。A semiconductor having a mesa-shaped current-carrying portion having upper and lower sides of an active region sandwiched by cladding layers of a first conductivity type and a second conductivity type, respectively, and a deep impurity level on both sides of the current-carrying portion. In a buried structure semiconductor laser having a structure buried with a current blocking layer, the forbidden band has a forbidden band width at a position in contact with the active region and the cladding layer of at least one conductivity type. A buried semiconductor laser, wherein a bandgap barrier layer made of a semiconductor that is always larger than a width is provided between the current conducting portion and the current blocking layer.
定数の異なる膜を積層した多重膜構造であることを特徴
とする請求項1記載の埋込み構造半導体レーザ。2. The buried semiconductor laser according to claim 1, wherein said band gap barrier layer has a multi-layer structure in which films having different lattice constants are stacked.
あることを特徴とする請求項1又は2記載の埋込み構造
半導体レーザ。3. A buried semiconductor laser according to claim 1, wherein said band gap barrier layer is an InGaP layer.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-23190 | 1988-02-02 | ||
JP2319088 | 1988-02-02 | ||
JP63-42758 | 1988-02-24 | ||
JP4275888 | 1988-02-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01302791A JPH01302791A (en) | 1989-12-06 |
JP2780275B2 true JP2780275B2 (en) | 1998-07-30 |
Family
ID=26360506
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Families Citing this family (4)
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JPH0541559A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor laser |
JP5206368B2 (en) * | 2008-11-27 | 2013-06-12 | 富士通株式会社 | Optical semiconductor device |
JP5287369B2 (en) * | 2009-03-05 | 2013-09-11 | 富士通株式会社 | Semiconductor light emitting device and manufacturing method thereof |
JP2010219102A (en) * | 2009-03-13 | 2010-09-30 | Opnext Japan Inc | Semiconductor laser device |
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JPS61228693A (en) * | 1985-04-02 | 1986-10-11 | Fujitsu Ltd | Semiconductor light emitting device |
JPS61230388A (en) * | 1985-04-05 | 1986-10-14 | Fujitsu Ltd | Buried type semiconductor laser |
JPS6249687A (en) * | 1985-08-29 | 1987-03-04 | Fujitsu Ltd | Semiconductor laser |
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1988
- 1988-08-31 JP JP63219361A patent/JP2780275B2/en not_active Expired - Fee Related
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