JPS62235785A - Veritical field-effect transistor - Google Patents
Veritical field-effect transistorInfo
- Publication number
- JPS62235785A JPS62235785A JP8050886A JP8050886A JPS62235785A JP S62235785 A JPS62235785 A JP S62235785A JP 8050886 A JP8050886 A JP 8050886A JP 8050886 A JP8050886 A JP 8050886A JP S62235785 A JPS62235785 A JP S62235785A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diode
- conductivity type
- outer periphery
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は縦型電界効果トランジスタ（以下縦型ＭＯ８Ｆ
ＥＴと略す）Ｋ関し、特に内蔵される逆方向ダイオード
のサージ耐量向上に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a vertical field effect transistor (hereinafter referred to as a vertical MO8F transistor).
(abbreviated as ET), it particularly relates to improving the surge resistance of the built-in reverse diode.
従来、縦型ＭＯ８ＦＥＴは第セ図に示すように、寄生ト
ランジスタアクション防止のため、ｐウェル領域１，１
′間をソース電極６でシ１−トしており、ソース２−ド
レイン９間にダイオードが内蔵された形となっている。Conventionally, vertical MO8FETs have p-well regions 1 and 1 to prevent parasitic transistor action, as shown in Fig.
A diode is built in between the source 2 and the drain 9.
このダイオードを積極的に働かせようとの応用が最近増
加傾向にあり、特に、Ｌ負荷転流時の過電圧保護用ダイ
オードとして使う用途が増えてきている。Recently, there has been an increase in the number of applications in which diodes are used to actively work, and in particular, their use as overvoltage protection diodes during L load commutation has been increasing.
上述の機な用途に用いる場合、内蔵ダイオードは云わゆ
るツェナーダイオードの如く働き、サージ電圧が印加さ
れた場合ブレークダウンして一定電圧で過電圧を防ぎ、
そのままの状態で過電正分のエネルギーを電流として流
す。本来トランジスタアクシロン防止のために考慮した
以上の電流がダイオードを流れる事となるため、従来の
構造では、素子部でのトランジスタアクシロンにより、
ツェナーダイオードを外付けした場合に比べてはるかに
小さなエネルギーで、素子部が破壊してしまうと云う欠
点があった。When used in the above-mentioned applications, the built-in diode acts like a so-called Zener diode, and when a surge voltage is applied, it breaks down and maintains a constant voltage to prevent overvoltage.
In this state, the energy equal to the amount of the overcurrent flows as a current. In the conventional structure, the transistor axilon in the element part causes more current to flow through the diode than was originally considered to prevent the transistor axilon.
The drawback was that the element part would be destroyed by much less energy than when an external Zener diode was attached.
本発明は縦型ＭＯ８ＦＥＴとして動作する素子部と逆方
向ダイオードとして動作する外周部とに機能を構造でわ
け、外周部の耐圧を素子部よシ低くする事により、素子
部にある寄生トランジスタが動作を行こさない様にして
、耐量向上をはかるものである。The present invention has a structure that divides the functions into an element part that operates as a vertical MO8FET and an outer peripheral part that operates as a reverse diode, and by making the breakdown voltage of the outer peripheral part lower than that of the element part, the parasitic transistor in the element part operates. This is intended to improve durability by preventing this from occurring.
本発明の縦型電界効果トランジスタは、第１導電型の半
導体基板の一重部に形成された第２導電型のウェル領域
と、このウェル領域内に形成された第１導電型のソース
領域と、ソース領域と半導体基板との間のウェル領域の
表面に絶縁膜を介して形成されたゲート電極とを有する
縦型電界効果トランジスタにおいて、この縦型電界効果
トランジスタの外周にウェル領域より深い第２導電型の
ダイオード領域を設けたことを特徴とする。A vertical field effect transistor of the present invention includes: a well region of a second conductivity type formed in a single portion of a semiconductor substrate of a first conductivity type; a source region of a first conductivity type formed within the well region; In a vertical field effect transistor having a gate electrode formed on the surface of a well region between a source region and a semiconductor substrate with an insulating film interposed therebetween, a second conductive layer deeper than the well region is formed on the outer periphery of the vertical field effect transistor. It is characterized by having a type diode region.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明をＮチャネル縦型ＭＯ８ＦＥＴに応用し
た一実施例の縦断面図である。Ｎ−の半導体基板８の裏
面側にＮ のドレイン層９を形成し、表面側ＫＰウェル
層１およびダイオード領域ＩＩを＋
形成し、Ｐウェル層１内にＮ のソース層２を形成する
。Ｐウェル層１およびダイオード領域１′にＰウェル高
濃度層７を形成し、ソース電極の配線で接続する。ゲー
ト電極３をソース層２と半導体基板８の間のＰウェル層
１の上にゲート絶縁膜４を介して形成し、ゲート電極３
とソース電極６の配線とは絶縁膜５で絶縁し、縦型ＭＯ
８ＦＥＴが形成される。ダイオード領域１′ は縦型Ｍ
Ｏ８ＦＥＴの外周に形成する。ここで外周のダイオード
領域１′は縦型ＭＯ８ＦＥＴの形成されている素子部の
Ｐウェル層１よりも深く押込んで、素子部より深く形成
する。これによって外周のダイオード領域の耐圧は、素
子部のＰウェル層より低くなる。FIG. 1 is a longitudinal sectional view of an embodiment in which the present invention is applied to an N-channel vertical MO8FET. An N2 drain layer 9 is formed on the back side of the N- type semiconductor substrate 8, a front side KP well layer 1 and a diode region II are formed on the + side, and an N2 source layer 2 is formed in the P well layer 1. A P-well high concentration layer 7 is formed in the P-well layer 1 and the diode region 1', and connected by a source electrode wiring. A gate electrode 3 is formed on the P-well layer 1 between the source layer 2 and the semiconductor substrate 8 with a gate insulating film 4 interposed therebetween.
and the wiring of the source electrode 6 are insulated by an insulating film 5, and the vertical MO
8FETs are formed. Diode region 1' is vertical type M
Formed on the outer periphery of O8FET. Here, the diode region 1' on the outer periphery is pushed deeper than the P well layer 1 of the element part where the vertical MO8FET is formed, and is formed deeper than the element part. As a result, the diode region on the outer periphery has a lower breakdown voltage than the P-well layer in the element portion.
次にかような素子に外部より過電圧が印加された場合の
動作を説明する。ダイオード領域のブレークダウン電圧
をこえる過電圧が印加されると、外周のダイオード領域
１′ と半導体基板８とのダイオードがブレークダウン
し、ブレークダウン電流が、過電圧のエネルギーに応じ
て、外周部のみに流れる。この場合素子部は全く動作し
ないため、ドレイン９−Ｐウェル層１−ソース層２で形
成される寄生トランジスタは全く動作せずこのため素子
部は破゛壊をまぬがれる。また外周部のダイオードのサ
ージ耐量はツェナーダイオードと全く同機に面積に比例
するため、必要に応じて耐量設定も可能である。Next, the operation when an overvoltage is applied to such an element from the outside will be explained. When an overvoltage exceeding the breakdown voltage of the diode region is applied, the diode between the outer diode region 1' and the semiconductor substrate 8 breaks down, and a breakdown current flows only to the outer circumference depending on the energy of the overvoltage. . In this case, since the element section does not operate at all, the parasitic transistor formed by the drain 9-P well layer 1-source layer 2 does not operate at all, and therefore the element section is prevented from being destroyed. In addition, the surge resistance of the outer peripheral diode is proportional to the area, just like the Zener diode, so it is possible to set the surge resistance as necessary.
以上述べたように本発明は、縦型ＭＯ８ＦＥＴの形成さ
れている素子部の外周に、低耐圧のダイオードとして働
くダイオード領域を設ける事によって、ダイオードの過
電圧耐量を独立に大きく設計できる効果がある。As described above, the present invention has the effect that the overvoltage withstand capacity of the diode can be independently designed to be large by providing a diode region that functions as a low voltage diode on the outer periphery of the element portion where the vertical MO8FET is formed.
第１図は本発明の一実施例のＮチャネル縦型型界効果ト
ランジスタの縦断面図、第２図は従来の縦型電界効果ト
ランジスタの断面図である。
１・・・・・・Ｐウェル層、１′・・・・・・ダイオー
ド領域、２・・・・・・ソース層、３・・・・・・ゲー
ト電極、４・・・・・・ゲート絶縁膜、５・・・・・・
絶縁膜、６・・・・・・ソース電極、７・・・・・・Ｐ
ウェル高濃度層、８・・・・・・半導体基板、９・・・
・・・ドレイン層。
６一FIG. 1 is a longitudinal sectional view of an N-channel vertical field effect transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional vertical field effect transistor. 1...P well layer, 1'...diode region, 2...source layer, 3...gate electrode, 4...gate Insulating film, 5...
Insulating film, 6...source electrode, 7...P
Well high concentration layer, 8... Semiconductor substrate, 9...
...Drain layer. 61
Claims (1)
型のウェル領域と、該ウェル領域内に形成された第１導
電型のソース領域と、ソース領域と半導体基板との間の
ウェル領域の表面に絶縁膜を介して形成されたゲート電
極とを有する縦型電界効果トランジスタにおいて、該縦
型電界効果トランジスタの外周に前記ウェル領域より深
い第２導電型のダイオード領域を設けたことを特徴とす
る縦型電界効果トランジスタ。A well region of a second conductivity type formed on one principal surface of a semiconductor substrate of a first conductivity type, a source region of a first conductivity type formed within the well region, and a region between the source region and the semiconductor substrate. In a vertical field effect transistor having a gate electrode formed on the surface of a well region with an insulating film interposed therebetween, a diode region of a second conductivity type deeper than the well region is provided on the outer periphery of the vertical field effect transistor. A vertical field effect transistor characterized by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8050886A JPS62235785A (en) | 1986-04-07 | 1986-04-07 | Veritical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8050886A JPS62235785A (en) | 1986-04-07 | 1986-04-07 | Veritical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62235785A true JPS62235785A (en) | 1987-10-15 |
Family
ID=13720255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8050886A Pending JPS62235785A (en) | 1986-04-07 | 1986-04-07 | Veritical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62235785A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01215067A (en) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | Vertical insulating gate field effect transistor |
| JPH03105980A (en) * | 1989-09-20 | 1991-05-02 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US5191395A (en) * | 1990-04-02 | 1993-03-02 | Fuji Electric Co., Ltd. | Mos type semiconductor device with means to prevent parasitic bipolar transistor |
| JP2006140372A (en) * | 2004-11-15 | 2006-06-01 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| WO2010061244A1 (en) * | 2008-11-27 | 2010-06-03 | Freescale Semiconductor, Inc. | Power mos transistor device and switch apparatus comprising the same |
| US8604560B2 (en) | 2008-11-27 | 2013-12-10 | Freescale Semiconductor, Inc. | Power MOS transistor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206073A (en) * | 1981-06-12 | 1982-12-17 | Hitachi Ltd | Mis semiconductor device |
-
1986
- 1986-04-07 JP JP8050886A patent/JPS62235785A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206073A (en) * | 1981-06-12 | 1982-12-17 | Hitachi Ltd | Mis semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01215067A (en) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | Vertical insulating gate field effect transistor |
| JPH03105980A (en) * | 1989-09-20 | 1991-05-02 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US5191395A (en) * | 1990-04-02 | 1993-03-02 | Fuji Electric Co., Ltd. | Mos type semiconductor device with means to prevent parasitic bipolar transistor |
| JP2006140372A (en) * | 2004-11-15 | 2006-06-01 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| WO2010061244A1 (en) * | 2008-11-27 | 2010-06-03 | Freescale Semiconductor, Inc. | Power mos transistor device and switch apparatus comprising the same |
| US8530953B2 (en) | 2008-11-27 | 2013-09-10 | Freescale Semiconductor, Inc. | Power MOS transistor device and switch apparatus comprising the same |
| US8604560B2 (en) | 2008-11-27 | 2013-12-10 | Freescale Semiconductor, Inc. | Power MOS transistor device |
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