JP3189589B2 - Insulated gate type semiconductor device - Google Patents
Insulated gate type semiconductor deviceInfo
- Publication number
- JP3189589B2 JP3189589B2 JP22473994A JP22473994A JP3189589B2 JP 3189589 B2 JP3189589 B2 JP 3189589B2 JP 22473994 A JP22473994 A JP 22473994A JP 22473994 A JP22473994 A JP 22473994A JP 3189589 B2 JP3189589 B2 JP 3189589B2
- Authority
- JP
- Japan
- Prior art keywords
- insulated gate
- zener diode
- semiconductor device
- electrode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 55
- 230000005684 electric field Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は絶縁ゲートバイポーラト
ランジスタ（以下、ＩＧＢＴと記す）または絶縁ゲート
電界効果トランジスタ（以下、MOSFETと記す）等の絶縁
ゲート型半導体装置に関する。
【０００２】
【従来の技術】過電圧保護回路をMOSFETチップ内に内蔵
した半導体装置において、過電圧保護素子をMOSFETと分
離された絶縁膜上に設ける構造は既に特公平5−63949号
公報にて提案されている。図２はその従来例であり、縦
型MOSFETとそれに接続されたゲート保護素子の（ａ）断
面構造図、（ｂ）等価回路を示す。ここで、１はｎ型半
導体層、２はMOSFETのゲート絶縁膜、３はフィールド絶
縁膜、４はｐ型多結晶半導体層であり例えば硼素がドー
プされたものである。５は高濃度不純物をドープしたｎ
型多結晶半導体層、例えば砒素がドープされたもので、
ソース電極７及び電極１７に接続されている。電極１７
は絶縁ゲート電極９に接続している。また、１０はｐ型
ベース領域、１２はMOSFETのｎ型ソース領域、１４はｎ
型の半導体基板、１３はドレイン電極である。
【０００３】以上のように構成された半導体装置の等価
回路は、（ｂ）図に示すように、縦型MOSFETQ2のゲート
・ソース間に、互いに直列に接続された保護ダイオード
３１及び３２が接続された回路となる。縦型MOSFETQ2
は、ゲート絶縁膜２，ｎ型高濃度不純物のソース領域１
２，ｐ型のベース領域１０，多結晶シリコンの絶縁ゲー
ト電極９，半導体基板１４（ｎ型高濃度不純物基板）よ
り成っている。ここで、３１，３２のダイオードはMOSF
ETQ2の絶縁ゲート電極９に過大な外部サージが印加され
ないように動作するものであることから、MOSFETQ2のゲ
ート絶縁膜２の静電破壊防止のために有効なものであ
る。
【０００４】また、従来、過電圧保護回路部に過電圧検
知のためのアバランシェダイオードを拡散ｐウェルによ
り形成したもの（特開平4−332172 号公報）も提案され
ている。
【０００５】
【発明が解決しようとする課題】ＩＧＢＴの適用分野と
して主に、電子レンジやＣＲＴの水平偏向出力回路で用
いられる電圧共振回路があるが、ＩＧＢＴをこれらの回
路に適用する際にはサージ等の過電圧に対して素子とし
て十分な耐量を確保する必要がある。しかしながら、上
記従来技術（特公平5−63949号公報）にはソース・ドレ
イン間の高耐圧化の保護素子については考慮されておら
ず、ＩＧＢＴやMOSFETをさらに高耐圧，大電流域で用い
た場合、素子が破壊してしまうという問題がある。
【０００６】また、過電圧保護回路部に過電圧検知のた
めのアバランシェダイオードを拡散ｐウエルにより形成
したもの(特開平4−332172 号公報)については、アバラ
ンシェダイオードの面積がチップ全体の約５％を占める
ことから、ＩＧＢＴのオン特性に影響を及ぼすという問
題がある。
【０００７】本発明は、以上述べた従来技術の問題点を
解決し、高耐圧でかつ信頼性の高い絶縁ゲート型半導体
装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の絶縁ゲート型半導体装置では、半導体基
板における電界緩和領域の表面上にツェナーダイオード
を設け、このツェナーダイオードを絶縁ゲート電極とド
レイン電極の間に接続する。
【０００９】
【作用】本発明によれば、ソース・ドレイン間にツェナ
ーダイオードの耐圧を超える電圧が加わるとツェナーダ
イオードが降伏し、アバランシェ電流がゲート回路に流
れる。この時のソース・ドレイン間電圧はアバランシェ
時の電圧でクランプされる。このアバランシェ電流がゲ
ート回路のゲート抵抗を流れることによりゲート電位が
上昇し、絶縁ゲートのしきい値電圧以上に達すると、半
導体装置はオン状態となる。すなわち、電流を流すこと
によって半導体装置を過電圧から保護するものである。
【００１０】さらに、ツェナーダイオードは電界緩和領
域上に設けるので、ツェナーダイオードに費やす面積ロ
スがなく、半導体装置のオン特性を犠牲にすることがな
い。
【００１１】
【実施例】図１は本発明の一実施例を示す。縦型ＩＧＢ
Ｔとそれに接続されたゲート保護素子の（ａ）Ａ−Ａ′
面の断面構造、（ｂ）平面パターンの一部、（ｃ）等価
回路である。ここで１はｎ型半導体層（例えば比抵抗６
０Ωcm，厚さ６０μｍのシリコン）、２はＩＧＢＴのゲ
ート絶縁膜（ＳｉＯ2 等、厚さ７０ｎｍ）、３はターミ
ネーション部のフィールド絶縁膜（ＳｉＯ2等、厚さ１.
５μｍ）、４はｐ型多結晶半導体層（厚さ０.５μｍ の
ポリシリコン）であり例えばｐ型不純物であるボロンが
低濃度でドープされたもの、５はｎ型多結晶半導体層
(厚さ０.５μｍのポリシリコン）であり例えばｎ型不純
物である砒素が高濃度でドープされたものである。ｐ型
多結晶半導体層４およびｎ型多結晶半導体層５は複数個
直列に接続され、両端部となるｎ型多結晶半導体層５は
電極８および１７に接続されている。この電極８はドレ
イン電極と電気的に同電位であり、電極１７はアルミ配
線により絶縁ゲート電極９に接続している。１０はｐ型
ベース領域、１２はIGBTのｎ型ソース領域、１１はター
ミネーション部の電界緩和領域（ｐ型半導体シリコン
層）で、いわゆるフィールド・リミティング・リング構
造になっている。１３はドレイン電極、１４は半導体基
板（ｐ型シリコン基板）である。
【００１２】以上のように、本実施例の半導体装置は、
（ｃ）図に示したIBGTQ1と多結晶半導体層からなるツェ
ナーダイオード３０から構成され、縦型IGBTQ1のゲート
・ドレイン間にツェナーダイオード３０が接続された回
路となる。縦型IGBTQ1は、ｎ型ソース領域１２，ｐ型ベ
ース領域１０、多結晶シリコンの絶縁ゲート電極９，半
導体基板１４より成っている。ツェナーダイオードの構
成はｎ+ ｐ構造ダイオードの直列接続（例えば４０個直
列）より成っており、ＩＧＢＴチップ周辺のターミネー
ション部のフィールド絶縁膜３（酸化膜）上にリング状
に形成する。
【００１３】本実施例において、電圧共振回路における
フライバック電圧のように、IGBTのターンオフの際にソ
ース・ドレイン間に過電圧が加わると、IGBTQ1より若干
耐圧を低く設定した直列接続したツェナーダイオード３
０が降伏し、アバランシェ電流がゲート回路に流れる。
この時ソース・ドレイン間電圧はアバランシェ時の電圧
でクランプされる。このアバランシェ電流がゲート回路
のゲート抵抗を流れることによりゲート電位が上昇し、
IGBTQ1のしきい値電圧以上に達すると、瞬間的にＩＧＢ
Ｔはオン状態となり、過電圧から保護される。
【００１４】また、ターミネーション上に直列接続した
ツェナーダイオード３０を形成するので過電圧保護回路
の付加による面積の増加はなく、その結果IGBTQ1のオン
特性に影響を与えない。
【００１５】さらに、本実施例においては、ｐ型多結晶
半導体層４とｎ型多結晶半導体層５からなる複数のｐｎ
接合が、複数個のフィールド・リミッティング・リング
(11)の配列方向に沿ってほぼ平行に配列される。これに
より、フィールド絶縁膜３の上に形成したツェナーダイ
オード３０内の電界の方向とフィールド・リミッティン
グ・リング部のシリコン表面の電界の方向が一致するの
で、フィールド絶縁膜３の厚み方向に過大な電位差がか
からない。従って、フィールド絶縁膜３の劣化が起こら
ないので、ツェナーダイオード３０を付加したことによ
るターミネーションへの悪影響がない。また、半導体基
板表面の電位を直列接続したツェナーダイオード３０の
電位と一致するように電界制限領域１１の位置と不純物
濃度をコントロールすれば、ツェナーダイオードの領域
は半絶縁性のターミネーション保護膜としても有効に働
く。以上のことから信頼性の高い耐圧特性を得ることが
できる。
【００１６】図３は本発明の他の実施例を示し、縦型Ｉ
ＧＢＴとそれに接続された過電圧保護素子の（ａ）断面
構造図，（ｂ）等価回路、及び（ｃ）平面パターンの一
部である。この実施例では、保護素子が過電圧検知のた
めの高耐圧ツェナーダイオード３０と逆流防止およびゲ
ート保護のための低耐圧ツェナーダイオード３１で構成
される。ゲート・ドレイン間に設けられた高耐圧ツェナ
ーダイオード３０は前記実施例と同様、ｎ+ ｐ構造のツ
ェナーダイオードを直列接続したものである。直列接続
する個数は、過電圧印加時にIGBTQ1よりも先にアバラン
シェ降伏させ、過電圧検知機能を動作させるようIGBTQ1
の素子耐圧より若干低く設定する。また、ゲート・ソー
ス間に設けられた低耐圧ツェナーダイオード３１も前記
高耐圧ツェナーダイオード３０と同様にｎ+ ｐ構造のツ
ェナーダイオードを数個直列接続し、IGBTQ1のゲート絶
縁膜２の静電破壊防止に用いる。高耐圧ツェナーダイオ
ード３０と低耐圧ツェナーダイオード３１のゲート側は
共通であるので電極１７により接続し、低耐圧ツェナー
ダイオード３１の下部にはIGBTQ1のｐ型ベース領域１０
を伸ばし、IGBTQ1のラッチアップ防止を図る。上記低耐
圧ツェナーダイオード３１がチップ全体に占める面積は
IGBTQ1の損失のトレードオフに影響を及ぼさない程度の
ものであり、問題はない。
【００１７】図４は本発明の更に他の実施例であり、縦
型ＩＧＢＴとそれに接続された過電圧保護素子の断面図
を示す。この実施例の特徴は、高耐圧化技術として知ら
れているジャンクション・ターミネーション・エクステ
ンション構造に直列接続したツェナーダイオードを適用
した点にあり、図１中の電界緩和領域１１を設ける代わ
りに、ｐ型ベース領域１０に接してｎ+ 型リング領域１
６側に伸びるｐ- 型半導体層４０を設けた点にある。ジ
ャンクション・ターミネーション・エクステンション構
造の場合も電界緩和領域１１を設ける場合と同様、ツェ
ナーダイオード中の電位分布が半導体基板表面の電位分
布と一致するようにｐ- 型半導体層４０の位置および不
純物濃度を設定することにより、ツェナーダイオード領
域は半絶縁性のターミネーション用保護膜としても有効
に働き、信頼性の高い耐圧特性を得ることができる。
【００１８】次に、図１に示した半導体装置の製造方法
を図５を用いて説明する。図において、(ａ）,（ｂ）,
（ｃ）,（ｄ）はそれぞれ図１に示した高耐圧半導体集
積回路装置の製造方法の各工程を示している。
【００１９】（ａ）；ｎ型半導体層１の主表面にイオン
打ち込み法および熱拡散によってｐ型ベース領域１０お
よび電界緩和領域１１を選択的に形成する。ここで、ｐ
型ベース領域１０と電界緩和領域１１のイオン打ち込み
は所望の接合深さと不純物濃度を得るため、各々硼素ド
ーズ量および拡散時間を設定する。ｐ型ベース領域１０
は電界緩和領域１１に比べ、接合深さが浅く、且つ不純
物濃度が低い。その後、熱酸化によりｎ型半導体層１の
主表面を例えば１.５μｍ 酸化し、部分的にホトエッチ
ングで除去する。以上によりIGBTQ1のターミネーション
部の第１の絶縁膜３（フィールド酸化膜）と電界緩和領
域１１およびＩＧＢＴのｐ型ベース領域１０を形成す
る。
【００２０】（ｂ）；ｎ型半導体層１の主表面に熱酸化
によりIGBTQ1のゲート絶縁膜２を例えば７００Å形成す
る。次に、ＣＶＤ法により多結晶シリコンを例えば０.
５ μｍ積層する。その後、イオン打ち込み法により多
結晶シリコン全面にｐ型不純物である例えば硼素を低ド
ーズ量(例えば６×１０13cm-2)で打ち込み保護素子とな
るツェナーダイオード３０の低濃度ｐ型領域４（例えば
幅４.５μｍ)を形成する。次にツェナーダイオード３０
の高濃度のｎ型多結晶半導体層５（例えば幅２.０μｍ)
を形成するため、ホトリソグラフィにてツェナーダイオ
ード３０の低濃度ｐ型領域となる部分にホトレジストを
残し、ｎ型不純物である例えば砒素を高ドーズ量(例え
ば１×１０16cm-2)で打ち込む。この砒素の打ち込みはI
GBTQ1の絶縁ゲート電極９およびゲート配線の低抵抗化
を兼ねている。以上により、IGBTQ1の過電圧保護素子で
あるツェナーダイオード３０を形成する。なお、１個当
たりのツェナー電圧が８Ｖのツェナーダイオードを４０
個直列接続した場合、３２０Ｖの耐圧を得た。
【００２１】（ｃ）；（ｂ）で形成した多結晶シリコン
をホトリソグラフィにてパターニング後、ドライエッチ
ングにより部分的に除去する。次に、加工した多結晶シ
リコンおよびホトレジストをマスクとし、イオン打ち込
み法により砒素を高ドーズ量で打ち込み、熱処理を施す
ことにより、IGBTQ1のｎ型ソース領域とチップ端部のチ
ャネルストッパーとなるｎ+ 型リング領域１６を形成す
る。
【００２２】（ｄ）；主表面にＣＶＤ法により第２絶縁
膜１５となるＰＳＧ膜を積層し、コンタクト部の開口の
ためのホトエッチングを施す。その後、ＡＬ−Ｓｉを電
子ビーム蒸着やスパッタリング法によって例えば５μｍ
積層し、選択的にホトエッチングする。これにより、IG
BTQ1のソース電極７，ツェナーダイオード３０の両端の
IGBTQ1の絶縁ゲート電極９と接続する電極１７およびド
レイン電極１３と電気的に接続する電極８が形成され
る。次にパッシベーション膜として応力を緩和でき、且
つ外部からの湿気に対して有効な耐湿性の高い材料、例
えば、ＰＩＱやＰＳＧを形成し、最後にドレイン電極を
主表面の裏面に形成する。
【００２３】本製法によれば、過電圧検知部はｎ型半導
体基板１内の拡散ｐウエル層ではなく、多結晶シリコン
にイオン打ち込みを施して形成するツェナーダイオード
３０を用いるため加工精度が良好であり、その結果アバ
ランシェ電圧の絶対値を規定し易い。
【００２４】以上、本発明の実施したＩＧＢＴについて
述べたが、本発明はＩＧＢＴのみならずMOSFETなどの絶
縁ゲートを有する半導体装置に対して適用できる。ま
た、上述した実施例において導電型を逆極性にしても、
同様の効果がある。さらに、本実施例においては保護素
子はツェナーダイオードのみであるが、ツェナーダイオ
ードと他の回路素子からなる保護回路を形成しても良
い。
【００２５】
【発明の効果】本発明によれば、チップ面積を増大させ
ることなく保護素子としてのツェナーダイオードを絶縁
ゲート型半導体装置に内蔵できるので、半導体装置のオ
ン特性を犠牲にすることなく信頼性の向上が可能とな
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor such as an insulated gate bipolar transistor (hereinafter referred to as IGBT) or an insulated gate field effect transistor (hereinafter referred to as MOSFET). Related to the device. 2. Description of the Related Art In a semiconductor device having an overvoltage protection circuit built in a MOSFET chip, a structure in which an overvoltage protection element is provided on an insulating film separated from a MOSFET has already been proposed in Japanese Patent Publication No. 5-63949. ing. FIG. 2 shows a conventional example thereof, and shows (a) a sectional structural view and (b) an equivalent circuit of a vertical MOSFET and a gate protection element connected thereto. Here, 1 is an n-type semiconductor layer, 2 is a gate insulating film of a MOSFET, 3 is a field insulating film, and 4 is a p-type polycrystalline semiconductor layer, for example, doped with boron. 5 is n doped with high concentration impurities
Type polycrystalline semiconductor layer, for example, doped with arsenic,
It is connected to the source electrode 7 and the electrode 17. Electrode 17
Is connected to the insulated gate electrode 9. 10 is a p-type base region, 12 is an n-type source region of the MOSFET, and 14 is an n-type source region.
The semiconductor substrate 13 is a drain electrode. As shown in FIG. 1B, the equivalent circuit of the semiconductor device configured as described above has protection diodes 31 and 32 connected in series with each other between the gate and source of the vertical MOSFET Q2. Circuit. Vertical MOSFET Q2
Are a gate insulating film 2 and a source region 1 of an n-type high concentration impurity.
2, a p-type base region 10, a polycrystalline silicon insulated gate electrode 9, and a semiconductor substrate 14 (n-type high-concentration impurity substrate). Here, the diodes 31 and 32 are MOSF
Since it operates so that an excessive external surge is not applied to the insulated gate electrode 9 of the ETQ2, it is effective for preventing electrostatic breakdown of the gate insulating film 2 of the MOSFET Q2. [0004] Conventionally, a device in which an avalanche diode for detecting an overvoltage is formed by a diffusion p-well in an overvoltage protection circuit (Japanese Patent Laid-Open No. 4-332172) has also been proposed. [0005] As an application field of the IGBT, there is mainly a voltage resonance circuit used in a horizontal deflection output circuit of a microwave oven or a CRT. When the IGBT is applied to these circuits, It is necessary to ensure a sufficient resistance as an element against an overvoltage such as a surge. However, the above-mentioned prior art (Japanese Patent Publication No. 5-63949) does not consider a protection element having a high withstand voltage between a source and a drain. However, there is a problem that the element is destroyed. In the overvoltage protection circuit section in which an avalanche diode for detecting overvoltage is formed by a diffusion p-well (Japanese Patent Laid-Open No. 4-332172), the area of the avalanche diode occupies about 5% of the entire chip. Therefore, there is a problem that the ON characteristics of the IGBT are affected. An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an insulated gate semiconductor device having high withstand voltage and high reliability. In order to achieve the above object, in the insulated gate semiconductor device of the present invention, a Zener diode is provided on a surface of an electric field relaxation region in a semiconductor substrate, and the Zener diode is provided. Connected between the insulated gate electrode and drain electrode. According to the present invention, when a voltage exceeding the breakdown voltage of the Zener diode is applied between the source and the drain, the Zener diode breaks down and an avalanche current flows through the gate circuit. The source-drain voltage at this time is clamped by the avalanche voltage. When the avalanche current flows through the gate resistance of the gate circuit, the gate potential increases. When the gate potential reaches or exceeds the threshold voltage of the insulated gate, the semiconductor device is turned on. That is, the semiconductor device is protected from overvoltage by flowing a current. Further, since the Zener diode is provided on the electric field relaxation region, there is no area loss consumed for the Zener diode, and the ON characteristics of the semiconductor device are not sacrificed. FIG. 1 shows an embodiment of the present invention. Vertical IGB
T and (a) AA 'of the gate protection element connected thereto.
FIG. 3B is a sectional structure of a plane, (b) a part of a plane pattern, and (c) an equivalent circuit. Here, 1 is an n-type semiconductor layer (for example, a
0 Ωcm, silicon having a thickness of 60 μm), 2 is an IGBT gate insulating film (SiO 2 or the like, 70 nm thick), 3 is a field insulating film of a termination portion (SiO 2 or the like, 1.
5 μm), 4 is a p-type polycrystalline semiconductor layer (polysilicon having a thickness of 0.5 μm), for example, doped with boron, which is a p-type impurity, at a low concentration.
(Polysilicon having a thickness of 0.5 μm), for example, doped with arsenic, which is an n-type impurity, at a high concentration. A plurality of p-type polycrystalline semiconductor layers 4 and n-type polycrystalline semiconductor layers 5 are connected in series, and n-type polycrystalline semiconductor layers 5 at both ends are connected to electrodes 8 and 17. The electrode 8 has the same electric potential as the drain electrode, and the electrode 17 is connected to the insulated gate electrode 9 by aluminum wiring. Reference numeral 10 denotes a p-type base region, 12 denotes an n-type source region of the IGBT, and 11 denotes an electric field relaxation region (p-type semiconductor silicon layer) of a termination portion, which has a so-called field limiting ring structure. 13, a drain electrode; and 14, a semiconductor substrate (p-type silicon substrate). As described above, the semiconductor device of this embodiment is
(C) A circuit composed of the IBGTQ1 shown in the figure and a Zener diode 30 composed of a polycrystalline semiconductor layer, and having the Zener diode 30 connected between the gate and the drain of the vertical IGBTQ1. The vertical IGBT Q1 comprises an n-type source region 12, a p-type base region 10, an insulated gate electrode 9 of polycrystalline silicon, and a semiconductor substrate 14. The structure of the Zener diode is composed of a series connection (for example, 40 in series) of n + p type diodes, and is formed in a ring shape on the field insulating film 3 (oxide film) in the termination portion around the IGBT chip. In this embodiment, when an overvoltage is applied between the source and the drain when the IGBT is turned off, such as a flyback voltage in a voltage resonance circuit, a series-connected zener diode 3 having a withstand voltage slightly lower than that of the IGBT Q1 is used.
0 breaks down and avalanche current flows to the gate circuit.
At this time, the source-drain voltage is clamped by the avalanche voltage. When this avalanche current flows through the gate resistance of the gate circuit, the gate potential rises,
When the voltage exceeds the threshold voltage of IGBTQ1, IGB
T turns on and is protected from overvoltage. Further, since the zener diode 30 connected in series on the termination is formed, there is no increase in area due to the addition of the overvoltage protection circuit, and as a result, the ON characteristics of the IGBTQ1 are not affected. Further, in the present embodiment, a plurality of pns composed of a p-type polycrystalline semiconductor layer 4 and an n-type polycrystalline semiconductor layer 5 are formed.
Joints with multiple field limiting rings
They are arranged almost in parallel along the arrangement direction of (11). As a result, the direction of the electric field in the Zener diode 30 formed on the field insulating film 3 matches the direction of the electric field on the silicon surface of the field limiting ring portion, so that the direction of the electric field becomes excessively large in the thickness direction of the field insulating film 3. No potential difference is applied. Therefore, since the field insulating film 3 does not deteriorate, the addition of the zener diode 30 does not adversely affect the termination. If the position of the electric field limiting region 11 and the impurity concentration are controlled so that the potential on the surface of the semiconductor substrate matches the potential of the Zener diode 30 connected in series, the Zener diode region is also effective as a semi-insulating termination protection film. Work on. From the above, highly reliable breakdown voltage characteristics can be obtained. FIG. 3 shows another embodiment of the present invention.
It is (a) sectional structure drawing of GBT and the overvoltage protection element connected to it, (b) equivalent circuit, and (c) a part of plane pattern. In this embodiment, the protection element is composed of a high-voltage Zener diode 30 for detecting overvoltage and a low-voltage Zener diode 31 for backflow prevention and gate protection. The high voltage Zener diode 30 provided between the gate and the drain is formed by connecting in series a Zener diode having an n + p structure, as in the above embodiment. The number of IGBTQ1s connected in series is set so that the avalanche breakdown occurs before the IGBTQ1 when overvoltage is applied and the overvoltage detection function is activated.
Is set slightly lower than the element breakdown voltage. Also, similarly to the high-voltage Zener diode 30, a low-voltage Zener diode 31 provided between the gate and the source is connected in series with several Zener diodes having an n + p structure to prevent electrostatic breakdown of the gate insulating film 2 of the IGBTQ1. Used for Since the gate sides of the high-voltage Zener diode 30 and the low-voltage Zener diode 31 are common, they are connected by the electrode 17, and below the low-voltage Zener diode 31, the p-type base region 10 of the IGBT Q1 is formed.
To prevent latch-up of IGBTQ1. The area occupied by the low voltage Zener diode 31 in the whole chip is
It does not affect the IGBTQ1 loss trade-off, so there is no problem. FIG. 4 shows still another embodiment of the present invention, and is a sectional view of a vertical IGBT and an overvoltage protection element connected thereto. The feature of this embodiment lies in that a zener diode connected in series is applied to a junction termination extension structure known as a high withstand voltage technology. Instead of providing the electric field relaxation region 11 in FIG. N + type ring region 1 in contact with base region 10
The point is that ap − type semiconductor layer 40 extending to the sixth side is provided. Also in the case of the junction termination extension structure, the position and impurity concentration of the p − type semiconductor layer 40 are set so that the potential distribution in the Zener diode matches the potential distribution on the surface of the semiconductor substrate, similarly to the case where the electric field relaxation region 11 is provided. By doing so, the Zener diode region effectively functions as a semi-insulating termination protection film, and a highly reliable breakdown voltage characteristic can be obtained. Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. In the figure, (a), (b),
(C) and (d) show respective steps of the method of manufacturing the high withstand voltage semiconductor integrated circuit device shown in FIG. (A); A p-type base region 10 and an electric field relaxation region 11 are selectively formed on the main surface of the n-type semiconductor layer 1 by ion implantation and thermal diffusion. Where p
In the ion implantation of the mold base region 10 and the electric field relaxation region 11, the boron dose and the diffusion time are set in order to obtain a desired junction depth and impurity concentration. p-type base region 10
Has a shallower junction depth and a lower impurity concentration than the electric field relaxation region 11. Thereafter, the main surface of the n-type semiconductor layer 1 is oxidized by, for example, 1.5 μm by thermal oxidation and partially removed by photoetching. As described above, the first insulating film 3 (field oxide film) of the termination portion of the IGBT Q1, the electric field relaxation region 11, and the p-type base region 10 of the IGBT are formed. (B): A gate insulating film 2 of IGBTQ1 is formed on the main surface of the n-type semiconductor layer 1 by thermal oxidation, for example, at a thickness of 700.degree. Next, the polycrystalline silicon is, for example,
Laminate 5 μm. Thereafter, a low-concentration p-type region 4 (for example, boron) of a Zener diode 30 serving as a protection element is implanted at a low dose (for example, 6 × 10 13 cm −2 ) with, for example, boron as a p-type impurity over the entire surface of the polycrystalline silicon by ion implantation. (Width 4.5 μm). Next, the Zener diode 30
High-concentration n-type polycrystalline semiconductor layer 5 (for example, having a width of 2.0 μm)
Is formed, a photoresist is left in a portion to be a low concentration p-type region of the Zener diode 30 by photolithography, and an n-type impurity such as arsenic is implanted at a high dose (for example, 1 × 10 16 cm −2 ). This implantation of arsenic is I
The resistance of the insulated gate electrode 9 and the gate wiring of the GBTQ1 is also reduced. As described above, the Zener diode 30 which is the overvoltage protection element of the IGBT Q1 is formed. In addition, a Zener diode having a Zener voltage of 8 V per one is connected to 40
When these were connected in series, a withstand voltage of 320 V was obtained. (C); After the polycrystalline silicon formed in (b) is patterned by photolithography, it is partially removed by dry etching. Next, using the processed polycrystalline silicon and photoresist as a mask, arsenic is implanted at a high dose by an ion implantation method, and a heat treatment is performed to thereby provide an n + type source region of the IGBTQ1 and a channel stopper at a chip end portion. A ring region 16 is formed. (D): A PSG film serving as the second insulating film 15 is laminated on the main surface by the CVD method, and is subjected to photoetching for opening a contact portion. Thereafter, AL-Si is deposited to a thickness of, for example, 5 μm by electron beam evaporation or sputtering.
Laminate and selectively photoetch. This allows IG
Source electrode 7 of BTQ1 and both ends of Zener diode 30
An electrode 17 connected to the insulated gate electrode 9 and an electrode 8 electrically connected to the drain electrode 13 of the IGBT Q1 are formed. Next, a material having high moisture resistance, for example, PIQ or PSG, which can relieve stress as a passivation film and is effective against external moisture, is formed, and finally, a drain electrode is formed on the back surface of the main surface. According to the present manufacturing method, the overvoltage detector uses not the diffusion p-well layer in the n-type semiconductor substrate 1 but the zener diode 30 formed by ion-implanting polycrystalline silicon. As a result, it is easy to define the absolute value of the avalanche voltage. Although the IGBT according to the present invention has been described above, the present invention can be applied not only to the IGBT but also to a semiconductor device having an insulated gate such as a MOSFET. Further, even if the conductivity type is reversed in the embodiment described above,
There is a similar effect. Further, in this embodiment, the protection element is only the Zener diode, but a protection circuit including the Zener diode and other circuit elements may be formed. According to the present invention, a Zener diode serving as a protection element can be built in an insulated gate semiconductor device without increasing the chip area, so that the reliability can be reduced without sacrificing the ON characteristics of the semiconductor device. The performance can be improved.
【図面の簡単な説明】
【図１】本発明の一実施例。
【図２】従来例。
【図３】本発明の他の実施例。
【図４】本発明の更に他の実施例。
【図５】図１に示した半導体装置の製造方法。
【符号の説明】
１…ｎ型半導体層、２…ゲート絶縁膜、３…フィールド
絶縁膜、４…ｐ型多結晶半導体層、５…ｎ型多結晶半導
体層、６…絶縁膜、７…ソース電極、８，１７…電極、
９…絶縁ゲート電極、１０…ｐ型ベース領域、１１…電
界緩和領域、１２…ｎ型ソース領域、１３…ドレイン電
極、１４…半導体基板、１５…第２絶縁膜、１６…ｎ+
型リング領域、３０…ツェナーダイオード。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an embodiment of the present invention. FIG. 2 is a conventional example. FIG. 3 shows another embodiment of the present invention. FIG. 4 shows still another embodiment of the present invention. FIG. 5 is a method for manufacturing the semiconductor device shown in FIG. 1; [Description of Signs] 1 ... n-type semiconductor layer, 2 ... gate insulating film, 3 ... field insulating film, 4 ... p-type polycrystalline semiconductor layer, 5 ... n-type polycrystalline semiconductor layer, 6 ... insulating film, 7 ... source Electrodes, 8, 17, ... electrodes,
9 ... insulated gate electrode, 10 ... p-type base region, 11 ... electric field relaxation region, 12 ... n-type source region, 13 ... drain electrode, 14 ... semiconductor substrate, 15 ... second insulating film, 16 ... n +
Mold ring region, 30 ... Zener diode.
フロントページの続き (56)参考文献 特開 平６−196706（ＪＰ，Ａ) 特開 平３−38881（ＪＰ，Ａ) 特開 平５−206471（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 29/06 Continuation of front page (56) References JP-A-6-196706 (JP, A) JP-A-3-38881 (JP, A) JP-A-5-206471 (JP, A) (58) Fields investigated (Int) .Cl. 7 , DB name) H01L 29/78 H01L 29/06
Claims (1)
絶縁ゲート電極を設けた動作領域と、動作領域に隣接
し、フィールド・リミッティング・リング構造を有する
電界緩和領域と、電界緩和領域の表面に形成する絶縁膜
と、絶縁膜上に設けられ、一主電極と絶縁ゲート電極の
間に接続され、複数のｐｎ接合を有するツェナーダイオ
ードと、動作領域から伸びるべース領域上に設けられ、
他の主電極と絶縁ゲート電極の間に接続されるツェナー
ダイオードと、を有することを特徴とする絶縁ゲート型
半導体装置。 【請求項２】請求項１において、前記各ツエナーダイオ
ードが多結晶半導体からなることを特徴とする絶縁ゲー
ト型半導体装置。 【請求項３】請求項１または請求項２において、前記複
数のｐｎ接合が、前記フィールド・リミッティング・リ
ング構造における複数のフィールド・リミッティング・
リングの配列方向に沿って平行に配列されることを特徴
とする絶縁ゲート型半導体装置。 【請求項４】請求項１〜３のいずれか１頃において、前
記一主電極と前記絶縁ゲート電極の間に接続される前記
ツェナーダイオードが高耐圧ツェナーダイオードであ
り、前記他の主電極と前記絶縁ゲート電極の間に接続さ
れる前記ツェナーダイオードが低耐圧ツェナーダイオー
ドであることを特徴とする絶縁ゲート型半導体装置。 【請求項５】請求項２において、前記絶縁ゲート電極
が、前記各ツェナーダイオードの前記多結晶半導体と同
じ工程で形成される多結晶半導体からなることを特徴と
する絶縁ゲート型半導体装置。(57) [Claim 1] An electric field having a field limiting ring structure adjacent to the operation area and an operation area provided with a pair of main electrodes and an insulated gate electrode on the same semiconductor substrate. A relaxation region, an insulating film formed on a surface of the electric field relaxation region, a zener diode provided on the insulation film, connected between one main electrode and an insulated gate electrode, having a plurality of pn junctions, and extending from the operation region. Provided on the base area,
An insulated gate semiconductor device comprising: a Zener diode connected between another main electrode and an insulated gate electrode. 2. The insulated gate semiconductor device according to claim 1, wherein each of said Zener diodes comprises a polycrystalline semiconductor. 3. The plurality of pn junctions according to claim 1, wherein the plurality of pn junctions are formed by a plurality of field limiting rings in the field limiting ring structure.
An insulated gate semiconductor device which is arranged in parallel along a direction in which rings are arranged. 4. The method according to claim 1, wherein the Zener diode connected between the one main electrode and the insulated gate electrode is a high voltage Zener diode, and the Zener diode is connected to the other main electrode. The insulated gate semiconductor device, wherein the zener diode connected between the insulated gate electrodes is a low withstand voltage zener diode. 5. The insulated gate semiconductor device according to claim 2, wherein said insulated gate electrode is made of a polycrystalline semiconductor formed in the same step as said polycrystalline semiconductor of each said Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22473994A JP3189589B2 (en) | 1994-09-20 | 1994-09-20 | Insulated gate type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22473994A JP3189589B2 (en) | 1994-09-20 | 1994-09-20 | Insulated gate type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0888354A JPH0888354A (en) | 1996-04-02 |
| JP3189589B2 true JP3189589B2 (en) | 2001-07-16 |
Family
ID=16818487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22473994A Expired - Fee Related JP3189589B2 (en) | 1994-09-20 | 1994-09-20 | Insulated gate type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3189589B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102018115637A1 (en) * | 2018-06-28 | 2020-01-02 | Infineon Technologies Ag | Power semiconductor component |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100331540B1 (en) * | 2000-06-23 | 2002-04-06 | 김덕중 | MOS-type semiconductor device with electrostaticdischarge diode between gate and emitter |
| JP2006093505A (en) * | 2004-09-27 | 2006-04-06 | Sanyo Electric Co Ltd | Protecting device for mos type element, and semiconductor device |
| JP2008177328A (en) | 2007-01-18 | 2008-07-31 | Denso Corp | Semiconductor device and manufacturing method thereof |
| JP5298488B2 (en) * | 2007-09-28 | 2013-09-25 | 富士電機株式会社 | Semiconductor device |
| JP2009111304A (en) * | 2007-11-01 | 2009-05-21 | Fuji Electric Device Technology Co Ltd | Overvoltage protective function built-in mos semiconductor apparatus and method of manufacturing the same |
| JP5358926B2 (en) * | 2007-11-01 | 2013-12-04 | 富士電機株式会社 | Silicon carbide trench MOS type semiconductor device |
| JP5867623B2 (en) | 2012-11-08 | 2016-02-24 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN104981903B (en) * | 2013-03-14 | 2017-12-01 | 富士电机株式会社 | Semiconductor device |
| JP6430424B2 (en) * | 2016-03-08 | 2018-11-28 | 株式会社東芝 | Semiconductor device |
| CN109952633B (en) * | 2016-09-13 | 2022-05-27 | 新电元工业株式会社 | Semiconductor device and method for manufacturing the same |
| JP6872933B2 (en) * | 2017-03-01 | 2021-05-19 | 株式会社豊田中央研究所 | Semiconductor device |
-
1994
- 1994-09-20 JP JP22473994A patent/JP3189589B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102018115637A1 (en) * | 2018-06-28 | 2020-01-02 | Infineon Technologies Ag | Power semiconductor component |
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| Publication number | Publication date |
|---|---|
| JPH0888354A (en) | 1996-04-02 |
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