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JPS62213117A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62213117A
JPS62213117A JP5571786A JP5571786A JPS62213117A JP S62213117 A JPS62213117 A JP S62213117A JP 5571786 A JP5571786 A JP 5571786A JP 5571786 A JP5571786 A JP 5571786A JP S62213117 A JPS62213117 A JP S62213117A
Authority
JP
Japan
Prior art keywords
substrate
layer
gaas
gaas layer
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5571786A
Other languages
Japanese (ja)
Inventor
Akihiro Hashimoto
明弘 橋本
Takeshi Kamijo
健 上條
Masao Kobayashi
正男 小林
Nozomi Watanabe
望 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5571786A priority Critical patent/JPS62213117A/en
Publication of JPS62213117A publication Critical patent/JPS62213117A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent cracks from being generated when a compound semiconductor layer is made to grow thickly and directly on a Si substrate, by performing selective growth of the compound semiconductor layer on an exposed regions not covered with a mask layer on the Si substrate on which the mask layer made of the insulating film are partially formed. CONSTITUTION:A GaAs layer 25 grows partially on a Si substrate 11 by making the GaAs layer 25 or the like grow as a compound semiconductor layer only on the region which is not covered with a mask layer 23. Therefore, strain caused by difference between thermal expansion coefficiency of the Si substrate 11 and that of the GaAs layer 25 becomes smaller than the strain in the GaAs layer growing over the whole surface of the Si substrate. Hence, cracks are prevented from being generated and a bend of the wafer becomes extremely small, capable of manufacturing the semiconductor element with good yield.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、Si基板上に化合物半導体素子を製造する
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a compound semiconductor device on a Si substrate.

(従来の技術) 従来から、安価で強度も大きくかつ熱伝導率も大きいS
i基板上に発光或いは高速動作する素子の作製が可能な
GaAs等の化合物半導体層を成長させ、これらSi及
び化合物半導体双方の特徴を生かして半導体素子を製造
する試みがなされている。
(Conventional technology) S
Attempts have been made to grow a compound semiconductor layer such as GaAs on which a device that emits light or operates at high speed is produced on an i-substrate, and to manufacture a semiconductor device by taking advantage of the characteristics of both Si and compound semiconductors.

この目的のため、分子線エピタキシャル成長法(MBE
法)或いは有機金属気相成長法(MOCVD法)によっ
てSt基板上全面にGaAs層を成長さiた後素子作製
を行う方法がある。
For this purpose, molecular beam epitaxial growth (MBE)
Alternatively, there is a method in which a GaAs layer is grown on the entire surface of an St substrate by a metal organic chemical vapor deposition method (MOCVD method) and then the device is manufactured.

このGaAs層の成長方法としては例えば文献(ジャー
ナル オン クリスタル グ ロ ウ ス(Journ
al of (:rystal Growth ) 、
68 [13(1984)P、21〜26)に開示され
ているものがある。この文献にはSi基板上にGaAs
層を直接結晶成長させる方法及びこの方法によって得ら
れた結晶の品質についての報告がなされている。そして
、この方法によれば、先ず、Si基板上に低温度(40
0〜600℃)で薄い厚みに成長させたGaAs層と、
このGaAs層上にGaAs層及びGaAj!As層を
交互に積層した層とから成るバッファ層を成長させ、そ
の後、このバッファ居士にGaAs層を成長させていて
、この方法を用いることによりて電子デバイス及び光デ
バイスの双方の作製に用いて好適な結晶を得ていた。
For example, the method for growing this GaAs layer is described in the literature (Journal on Crystal Growth).
al of (:rystal Growth),
68 [13 (1984) P, 21-26). This document describes GaAs on a Si substrate.
Reports have been made on methods for direct crystal growth of layers and on the quality of crystals obtained by this method. According to this method, first, the Si substrate is coated at a low temperature (40°C).
A GaAs layer grown to a thin thickness at a temperature of 0 to 600°C);
A GaAs layer and GaAj! are formed on this GaAs layer. A buffer layer consisting of alternately laminated As layers is grown, and then a GaAs layer is grown on this buffer layer, and by using this method, it can be used to fabricate both electronic devices and optical devices. A suitable crystal was obtained.

又、Si基板上にGaAs層を直接成長させる他の方法
として以下に説明するような方法もある(日刊工業新聞
(昭和60年9月25日))。
In addition, there is another method for directly growing a GaAs layer on a Si substrate, as described below (Nikkan Kogyo Shimbun (September 25, 1985)).

先ず、アルシン及び水素の混合ガス雰囲気中でSi基板
を約900℃の温度で熱処理した後、このSi基板上全
面に400〜450℃の温度でGaAs層を例えば20
0人というような簿い膜厚に成長させる。次に、この薄
いGaAs層上にGaAS層を700〜850℃の温度
で成長させることによフて、E P D (Etch 
Pit Density)が小ざ〈電子移動度が520
0cm2/V−seeと大きなGaAs結晶層を得てい
た。
First, a Si substrate is heat-treated at a temperature of about 900°C in a mixed gas atmosphere of arsine and hydrogen, and then a GaAs layer is formed on the entire surface of the Si substrate at a temperature of 400 to 450°C.
We will grow the film to a level where there are no people. Next, by growing a GaAs layer on this thin GaAs layer at a temperature of 700 to 850°C, EPD (Etch
Pit Density) is small (electron mobility is 520
A large GaAs crystal layer of 0 cm2/V-see was obtained.

第2図(A)及びCB)は半導体素子の従来の製造方法
を概略的に示す製造工程図である。
FIGS. 2(A) and 2(CB) are manufacturing process diagrams schematically showing a conventional method for manufacturing semiconductor devices.

先ず、上述したような方法によってSi基板11上全面
にGaAs層13を成長させる(第2図(A))。次に
、フォトエツチング技術によってこのGaAs層13の
不要部分を除去し、半導体素子形成のために必要なGa
As層領域13aを残存させる(第2図(B))。そし
て、残存したGaAs層領域13aに、或いは、Si基
板も含めた領域に所望とする半導体素子を作製していた
。尚、第2図(B)においてI5は素子間を電気的に或
いは光学的に分離する等の目的で設けた例えばSi3N
4膜等から成る絶縁層を示す。
First, a GaAs layer 13 is grown on the entire surface of the Si substrate 11 by the method described above (FIG. 2(A)). Next, unnecessary portions of this GaAs layer 13 are removed using photoetching technology, and Ga necessary for forming a semiconductor element is removed.
The As layer region 13a is left (FIG. 2(B)). Then, a desired semiconductor element was fabricated in the remaining GaAs layer region 13a or in the region including the Si substrate. In FIG. 2(B), I5 is a Si3N film, for example, provided for the purpose of electrically or optically isolating the elements.
An insulating layer consisting of four films, etc. is shown.

(発明が解決しようとする問題点) しかしながら、この出願人に係る調査によれば、Si基
板上全面にGaAs層を成長させるような従来の製造方
法では、このGaAs層の厚みが増すに従い、Si基板
と、GaAs層との熱膨張率の違いによってこれらの歪
が大きくなり、これがため、GaAs層の厚みが薄いう
ちはその厚みに応じSi基板及びGaAs層から成るウ
ェハの反りが生じ、さらに、GaAs層の厚みがある程
度以上となるとこのGaAs層にクラックか生じてしま
うという問題点があることが分かった。
(Problems to be Solved by the Invention) However, according to research conducted by the applicant, in the conventional manufacturing method in which a GaAs layer is grown all over the Si substrate, as the thickness of the GaAs layer increases, the Si These strains increase due to the difference in thermal expansion coefficient between the substrate and the GaAs layer, and as a result, as long as the GaAs layer is thin, the wafer consisting of the Si substrate and the GaAs layer warps depending on the thickness. It has been found that there is a problem in that when the thickness of the GaAs layer exceeds a certain level, cracks occur in the GaAs layer.

実際、例えば2インチ(1インチは約2.54cm、)
のSi基板上全面にGaAs層を約4μmの厚みに成長
させた場合ウェハの反りが数10μmにもなり、さらに
、4μmよりも厚い厚みに成長させた場合このGaAs
層にクラックが生ずる。
In fact, for example, 2 inches (1 inch is about 2.54 cm)
When a GaAs layer is grown on the entire surface of a Si substrate to a thickness of approximately 4 μm, the wafer warpage will be several tens of μm.Furthermore, when grown to a thickness thicker than 4 μm, this GaAs
Cracks form in the layer.

ところで、半導体素子の製造に際しその素子を薄い厚み
のGaAs層によって製造が可能な例えばFET(電界
効果トランジスタ)のような素子とした場合上述したウ
ェハの反りも小さいので、素子製造上支障とはならない
By the way, when a semiconductor device is manufactured using a thin GaAs layer, such as an FET (field effect transistor), the above-mentioned wafer warpage is small, so it does not pose a problem in device manufacturing. .

しかし、素子の製造に際しある程度に厚いGaAs層を
必要とするような場合は、前述した原因で生じるウェハ
の反りがフォトエツチング工程でのマスク合わせ或いは
露光量の正確さを低下させる原因となり、これがため、
半導体素子の製造歩留まりが低下する。又、Si基板上
に例えば化合物半導体レーザ素子を製造するような場合
はGaAs層の厚みを101μm程度とする必要があり
(詳細は後述する。)、従フて、4μm程度の厚みでク
ラックが生じてしまうようでは素子の製造を行うことが
出来ない。
However, when manufacturing a device that requires a GaAs layer that is somewhat thick, the warping of the wafer caused by the above-mentioned causes reduces the accuracy of mask alignment or exposure dose in the photoetching process, which leads to ,
The manufacturing yield of semiconductor devices decreases. Furthermore, when manufacturing a compound semiconductor laser device on a Si substrate, for example, the thickness of the GaAs layer needs to be about 101 μm (details will be described later), and cracks occur at a thickness of about 4 μm. It is not possible to manufacture the device if the process ends.

この発明の目的は、上述した問題点を解決し、Si基板
上に化合物半導体層を直接厚い厚みに成長させても所望
とする半導体素子を得ることが出来ると共に、半導体素
子を歩留まり良く製造することが出来る方法を提供する
ことにある。
An object of the present invention is to solve the above-mentioned problems, to obtain a desired semiconductor device even if a compound semiconductor layer is directly grown to a large thickness on a Si substrate, and to manufacture the semiconductor device with a high yield. The goal is to provide a method that can be used.

(問題点を解決するための手段) この目的の達成を図るため、この発明によれば、Si基
板上に化合物半導体層を成長させて半導体素子を製造す
るに当り、 Si基板上に例えば絶縁膜から成るマスク層を部分的に
形成する工程と、このSi基板の、このマスク層によっ
て覆われていない露出領域に化合物半導体層を選択成長
させる工程とを含むことを特徴とする。
(Means for Solving the Problems) In order to achieve this object, according to the present invention, when manufacturing a semiconductor element by growing a compound semiconductor layer on a Si substrate, for example, an insulating film is grown on the Si substrate. The present invention is characterized in that it includes the steps of partially forming a mask layer consisting of the following: and selectively growing a compound semiconductor layer in exposed regions of the Si substrate not covered by the mask layer.

この選択成長を例えばMOCVD法或いはガスを原料と
したMBE法等によって行うことが出来る。
This selective growth can be performed, for example, by MOCVD, MBE using gas as a raw material, or the like.

(作用) この発明の半導体素子の製造方法によれば、化合物半導
体層としての例えばGaAs層がSi基板の、マスク層
によって覆われていない領域にのみ成長する。従って、
GaAs層はSi基板上に部分的に成長することになり
、よって、この場合のSi基板と、GaAs層との熱膨
張係数の違いに起因して生ずる歪はSi基板上全面にG
aAs層を成長させた場合の歪よりも小さくなる。
(Function) According to the method for manufacturing a semiconductor device of the present invention, for example, a GaAs layer as a compound semiconductor layer grows only in the region of the Si substrate that is not covered by the mask layer. Therefore,
The GaAs layer will grow partially on the Si substrate, and therefore, the strain caused by the difference in thermal expansion coefficient between the Si substrate and the GaAs layer will be caused by G on the entire surface of the Si substrate.
The strain is smaller than that when an aAs layer is grown.

これがため、Si基板上に化合物半導体層をウェハの反
り或いはGaAs層のクラックを生じさせることな〈従
来よりも厚く成長させることが出来る。
Therefore, a compound semiconductor layer can be grown thicker than before on a Si substrate without warping the wafer or cracking the GaAs layer.

(実施例) 以下、第1図(A)〜(C)を参照してこの発明の半導
体素子の製造方法の一例につき説明する。尚、これらの
図は製造工程中の主要工程でのウェハ断面を示したもの
であるが、この発明が理解できる程度に概略的に示しで
あるにすぎず、各構成成分の寸法、形状及び配置関係は
図示例に限定されるものではない。又、これらの図にお
いて同一の構成成分については同一の符号を付して示し
である。
(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. 1(A) to 1(C). Note that these figures show cross sections of wafers at major steps in the manufacturing process, but they are only shown schematically to the extent that this invention can be understood. The relationship is not limited to the illustrated example. Further, in these figures, the same components are designated by the same reference numerals.

第1図(A)において、11はSi(シリコン)基板を
示す。先ず、硫酸と過酸化水素水とを1対1で混合した
洗浄液によってこのSi基板11の表面を洗浄する。次
に、フッ化水素酸によってこのSi基板IIの表面を僅
かにエツチングしてこの表面を清浄にする。次に、プラ
ズマCVD法或いは熱CVD法によってこのSi基板1
1の表面にマスク層形成のための例えばSi3N4膜か
ら成る絶縁膜21を約2000人の膜厚で形成する(第
1図(A))。
In FIG. 1(A), 11 indicates a Si (silicon) substrate. First, the surface of the Si substrate 11 is cleaned with a cleaning solution containing a 1:1 mixture of sulfuric acid and hydrogen peroxide. Next, the surface of this Si substrate II is slightly etched with hydrofluoric acid to clean the surface. Next, this Si substrate 1 is processed by plasma CVD method or thermal CVD method.
An insulating film 21 made of, for example, a Si3N4 film for forming a mask layer is formed on the surface of the substrate 1 to a thickness of about 2000 mm (FIG. 1(A)).

次に、フォトリソグラフィ及びフッ化水素酸を用いこの
絶縁膜21を所定形状に例えばストライブ状に除去して
、Si基板11上に絶縁膜21の残存した部分で構成さ
れるマスク層23を形成する(第1図(B))。尚、第
1図(B)はSi基板11の一部に着目して示した断面
図であるが、図示しない領域の絶縁膜21の所定の複数
個所にもSi基板IIの一部を露出するストライブ状の
窓がそれぞれ形成されている。
Next, this insulating film 21 is removed in a predetermined shape, for example, in a stripe shape, using photolithography and hydrofluoric acid to form a mask layer 23 made up of the remaining portion of the insulating film 21 on the Si substrate 11. (Figure 1 (B)). Although FIG. 1B is a cross-sectional view focusing on a part of the Si substrate 11, a part of the Si substrate II is also exposed at a plurality of predetermined locations of the insulating film 21 in an area not shown. Each stripe-shaped window is formed.

次に、MOCVD法によって、このマスク層23を含む
Si基板11上に化合物半導体層としての例えばGaA
sの結晶成長を行う。この結晶成長を行うに当り、その
成長条件を成長層内の圧力を例えば100Torrとし
、原料のモル比を例えばI[1/V々20として行うと
、マスク層23の上にはGaAsが成長することなく、
マスク層23によって覆われていないSi基板11の露
出領域にのみGaAsが選択的に成長する(第1図(C
))。
Next, by MOCVD method, a compound semiconductor layer such as GaA is formed on the Si substrate 11 including this mask layer 23.
Perform crystal growth of s. When performing this crystal growth, if the growth conditions are such that the pressure in the growth layer is 100 Torr and the molar ratio of the raw materials is 20, for example, I[1/V, GaAs will grow on the mask layer 23. without any
GaAs grows selectively only in the exposed regions of the Si substrate 11 that are not covered by the mask layer 23 (see FIG.
)).

従って、この実施例の場合Si基板11の所定の複数の
個所にストライブ状のGaAs層25が島状に点在する
Therefore, in this embodiment, striped GaAs layers 25 are scattered in island shapes at a plurality of predetermined locations on the Si substrate 11.

さらに、図示せずも、このGaAs層25領域に、或は
このGaAs層25領域及びSi基板11領域の両頭域
に所望とする電子デバイス及び光デバイスを形成して半
導体素子を得ることが出来る。
Further, although not shown, desired electronic devices and optical devices can be formed in the GaAs layer 25 region or in both regions of the GaAs layer 25 region and the Si substrate 11 region to obtain a semiconductor element.

上述したように、この発明によれば、GaAs層25を
Si基板ll上の半導体素子形成のために必要な領域の
みに個々に分離させた状態で成長させ、然る後、半導体
素子を形成する。従って、Si基板11上全面にGaA
s層を成長させた場合とは異り、この発明の場合は、S
i基板I+の、G a A s 25層を成長させなか
フた領域によってGaAs層25とSi基板11との熱
膨張率の違いによって生ずる歪を緩和することが出来る
As described above, according to the present invention, the GaAs layer 25 is grown individually in only the regions necessary for forming the semiconductor element on the Si substrate 11, and then the semiconductor element is formed. . Therefore, the entire surface of the Si substrate 11 is covered with GaA.
Unlike the case where the S layer is grown, in the case of this invention, the S layer is grown.
The strain caused by the difference in thermal expansion coefficient between the GaAs layer 25 and the Si substrate 11 can be alleviated by the region of the i-substrate I+ where the GaAs 25 layer is not grown.

尚、Si基板11上の、GaAs層25を成長させる位
置、又、GaAs層25の形状及び層厚を半導体素子の
種類に応じて任意好適な位置、形状及び層厚とすること
が出来る。例えばSi基板+1上に成長させた島状のG
aAs層25の広さを1チツプを構成するに必要な広さ
にしても良い。何れの場合も、GaAs層25を半導体
製造に適しかつ上述した熱膨張率の違いに起因する歪低
減が成されるような配置及び形状となるようにする。尚
、この発明によればこのGaAs層25の配置及び形状
の変更をマスク層23の形状を変更することによって容
易に行うことが出来る。
Incidentally, the position on the Si substrate 11 where the GaAs layer 25 is grown, and the shape and layer thickness of the GaAs layer 25 can be set to any suitable position, shape, and layer thickness depending on the type of semiconductor element. For example, an island-shaped G grown on a Si substrate +1
The width of the aAs layer 25 may be set to the width necessary to constitute one chip. In either case, the GaAs layer 25 is arranged and shaped so as to be suitable for semiconductor manufacturing and to reduce strain caused by the above-mentioned difference in coefficient of thermal expansion. According to the present invention, the arrangement and shape of the GaAs layer 25 can be easily changed by changing the shape of the mask layer 23.

尚、上述した実施例は化合物半導体層の選択成長をMO
CVD法を用いて行う例で説明した、しかしこの発明は
この方法に限定されるものではな(MOCVDの代わり
にガスを原料としたMBE法を用い結晶成長条件をこの
MBE法に適した条件とした場合も実施例と同様な効果
が期待できる。
In addition, in the above-mentioned embodiment, the selective growth of the compound semiconductor layer is performed using MO.
Although the invention has been explained using an example using the CVD method, the present invention is not limited to this method. Even in this case, the same effects as in the example can be expected.

又、上述した実施例はSi基板上に成長させる化合物半
導体層をGaAs層とした例につき説明したが、この発
明はこの実施例に限定されるものではなくSi基板上に
直接成長できかつ選択成長が可能な化合物半導体であれ
ばどのようなものにでも適用することが出来る。このよ
うな化合物半導体の例としてはInP系或いはZn5e
系のものが挙げられる。
In addition, although the above-mentioned embodiment has been explained using an example in which the compound semiconductor layer to be grown on the Si substrate is a GaAs layer, the present invention is not limited to this embodiment. It can be applied to any compound semiconductor that can be used. Examples of such compound semiconductors include InP and Zn5e.
Examples include those of the type.

又、上述した実施例ではマスク層としてSi3N4を用
いた例につき説明したが、このマスク層を例えば5in
2或いはAIL203等の絶縁膜を以って構成しても良
い。
Further, in the above embodiment, an example was explained in which Si3N4 was used as the mask layer, but this mask layer was, for example, 5 inches thick.
2 or an insulating film such as AIL203.

さらに、上述した実施例で説明したマスク層の成膜方法
をスパッタ法等の他の好適な方法としても良く、又、マ
スク層のエツチング方法等はドライエツチング法等の他
の好適な方法で行っても良い。
Furthermore, the method for forming the mask layer described in the above embodiments may be performed using other suitable methods such as sputtering, and the etching method for the mask layer may be performed using other suitable methods such as dry etching. It's okay.

(発明の効果) 上述した説明からも明らかなように、この発明の半導体
素子の製造方法によれば、Si基板と、化合物半導体層
との熱膨張係数の違いによって生ずる歪を低減させるこ
とが出来る。従って、Si基板上に従来と同様な厚みで
化合物半導体層を成長させた場合この層でのクラックが
発生することが全くなくかつウェハの反りも非常に小さ
くなるから、ウェハ各所でのマスク合わせや露光を正確
に行うことが出来る。
(Effects of the Invention) As is clear from the above description, according to the method for manufacturing a semiconductor element of the present invention, it is possible to reduce the strain caused by the difference in thermal expansion coefficient between the Si substrate and the compound semiconductor layer. . Therefore, when a compound semiconductor layer is grown on a Si substrate to the same thickness as before, no cracks will occur in this layer and the wafer warpage will be extremely small, making mask alignment at various parts of the wafer easier. Exposure can be performed accurately.

又、この発明の半導体素子の製造方法によれば、クエへ
の反り或いはクラックを発生させることな〈従来よりも
厚い厚みの化合物半導体層をSi基板上に成長させるこ
とが出来る。従って、Si基板上に例えば10μm程度
の厚さの化合物半導体層を成長させることも出来るので
1例えば内部電流狭窄構造を有する半導体レーザ素子等
のような厚い化合物半導体層を必要とする半導体素子を
形成することも可能となる。
Further, according to the method of manufacturing a semiconductor device of the present invention, a compound semiconductor layer thicker than conventional methods can be grown on a Si substrate without causing warping or cracking. Therefore, it is possible to grow a compound semiconductor layer with a thickness of, for example, about 10 μm on a Si substrate, thereby forming a semiconductor device that requires a thick compound semiconductor layer, such as a semiconductor laser device with an internal current confinement structure. It is also possible to do so.

これがため、Si基板上に化合物半導体層を直接厚い厚
みに成長させても所望とする半導体素子を得ることが出
来ると共に、この半導体素子を歩留まり良く製造するこ
とが出来る。
Therefore, even if a compound semiconductor layer is directly grown to a large thickness on a Si substrate, a desired semiconductor element can be obtained, and this semiconductor element can be manufactured with a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)〜(C)はこの発明の半導体素子の製造方
法を説明するための製造工程図、第2図(A)及び(B
)は従来の半導体素子の製造方法を説明するための製造
工程図である。 11・”St(シリコン)基板 21・−絶縁膜、     23・−マスク層25−・
・化合物半導体層(GaAs層)。 特許出願人    沖電気工業株式会社lf:sr(シ
リコン)基極 2f:#色参本g 2J”マスク層 25 : 4taQfl千4h不A ((、aAsA)
この分明【;イ糸る千44拳赤チのgd、方痺の説明居
第1図
FIGS. 1(A) to (C) are manufacturing process diagrams for explaining the method of manufacturing a semiconductor device of the present invention, and FIGS. 2(A) and (B)
) is a manufacturing process diagram for explaining a conventional method of manufacturing a semiconductor element. 11・"St (silicon) substrate 21・-insulating film, 23・-mask layer 25-・
- Compound semiconductor layer (GaAs layer). Patent applicant Oki Electric Industry Co., Ltd. lf: sr (silicon) base 2f: #color sample g 2J” mask layer 25: 4taQfl14hnonA ((,aAsA)
This understanding [; Iituru Sen 44 Fists Red Chi's GD, Explanation of Fangzi Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)Si基板上に化合物半導体層を成長させて半導体
素子を製造するに当り、 Si基板上にマスク層を部分的に形成する工程と、 該Si基板の、該マスク層によって覆われていない露出
領域に化合物半導体層を選択成長させる工程と を含むことを特徴とする半導体素子の製造方法。
(1) In manufacturing a semiconductor device by growing a compound semiconductor layer on a Si substrate, there is a step of partially forming a mask layer on the Si substrate, and a step of forming a mask layer on the Si substrate, and a portion of the Si substrate that is not covered by the mask layer. 1. A method for manufacturing a semiconductor device, comprising the step of selectively growing a compound semiconductor layer in an exposed region.
JP5571786A 1986-03-13 1986-03-13 Manufacture of semiconductor device Pending JPS62213117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5571786A JPS62213117A (en) 1986-03-13 1986-03-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5571786A JPS62213117A (en) 1986-03-13 1986-03-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62213117A true JPS62213117A (en) 1987-09-19

Family

ID=13006622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5571786A Pending JPS62213117A (en) 1986-03-13 1986-03-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62213117A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450431A (en) * 1987-08-20 1989-02-27 Seiko Epson Corp Formation of ii-vi compound semiconductor thin film
JPS6481233A (en) * 1987-09-22 1989-03-27 Seiko Epson Corp Selective growing method of selectively growing thin film of ii-vi compound semiconductor
JPH01181536A (en) * 1988-01-11 1989-07-19 Seiko Epson Corp Selectively growing ii-vi compound semiconductor thin-film
JPH02150020A (en) * 1988-11-30 1990-06-08 Kyocera Corp Semiconductor element and manufacture thereof
JPH0334535A (en) * 1989-06-27 1991-02-14 Intel Corp Manufacture of high-resistance gallium arsenide on silicon substrate
JPH0462917A (en) * 1990-07-02 1992-02-27 Hikari Gijutsu Kenkyu Kaihatsu Kk Selective growth method of compound semiconductor
US5108947A (en) * 1989-01-31 1992-04-28 Agfa-Gevaert N.V. Integration of gaas on si substrates
US5256594A (en) * 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
WO2010140370A1 (en) * 2009-06-05 2010-12-09 住友化学株式会社 Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
WO2010146865A1 (en) * 2009-06-19 2010-12-23 住友化学株式会社 Light emitting device and method for manufacturing a light emitting device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450431A (en) * 1987-08-20 1989-02-27 Seiko Epson Corp Formation of ii-vi compound semiconductor thin film
JPS6481233A (en) * 1987-09-22 1989-03-27 Seiko Epson Corp Selective growing method of selectively growing thin film of ii-vi compound semiconductor
JPH01181536A (en) * 1988-01-11 1989-07-19 Seiko Epson Corp Selectively growing ii-vi compound semiconductor thin-film
JPH02150020A (en) * 1988-11-30 1990-06-08 Kyocera Corp Semiconductor element and manufacture thereof
US5108947A (en) * 1989-01-31 1992-04-28 Agfa-Gevaert N.V. Integration of gaas on si substrates
US5256594A (en) * 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
JPH0334535A (en) * 1989-06-27 1991-02-14 Intel Corp Manufacture of high-resistance gallium arsenide on silicon substrate
JPH0462917A (en) * 1990-07-02 1992-02-27 Hikari Gijutsu Kenkyu Kaihatsu Kk Selective growth method of compound semiconductor
WO2010140370A1 (en) * 2009-06-05 2010-12-09 住友化学株式会社 Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
JP2011014896A (en) * 2009-06-05 2011-01-20 Sumitomo Chemical Co Ltd Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
CN102449785A (en) * 2009-06-05 2012-05-09 住友化学株式会社 Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
US8633496B2 (en) 2009-06-05 2014-01-21 Sumitomo Chemical Company, Limited Optical device and semiconductor wafer
WO2010146865A1 (en) * 2009-06-19 2010-12-23 住友化学株式会社 Light emitting device and method for manufacturing a light emitting device

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