JPS6216564A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To miniaturize the picture element pitch by a method wherein a source contact is formed in self-alingment with the gate electrode surrounding the source in a horizontal MOSSIT, and a transparent electrode is provided on it. CONSTITUTION:A horizontal MOSSIT is of N-channel and consists of a P<-> substrate 11, an N<-> epitaxial layer 12, a shallow drain 13, a deep drain 14, a source diffusion layer 15, a gate insulation film 16, a gate electrode 17 surrounding the source diffusion layer 15, a drain electrode 18, a source electrode 19 formed of a material of 1,000Angstrom or less such as polysilicon Si, etc. that is considered to be transparent, and an insulation film 20. The source contact 15 is formed in self-alignment with respect to the gate electrode 17 so that the distance for the margin is dispensed with. Moreover, the source electrode 19 is formed transparently so that it is also made possible to dispense with the gap for making the sensitivity of photo-electric conversion uniform. With space picture element displacement method, it is made possible to reduce the picture element pitch to 7mum.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a lateral static induction transistor ( (SIT)

[Conventional technology]

Mis(Metal In5uj!ator Sem1
Regarding an image sensor array using a horizontal SIT with a gate structure, the present inventors have proposed, for example, Japanese Patent Application No. 58-245059 and Japanese Patent Application No. 59-595.
25, and rJapanes
e Journal of Applied Phys.
ics J (Vo Il, 2.4. No, 5.19
85>” A New MO3Phototr
Ansistor Operating in a N
on-DestructiveReadout Mod
The presentation was titled e'''.

FIG. 7 is a sectional view showing a conventional horizontal M[1SSIT light receiving element. This MO3SIT is of n-channel type,
Substrate 1 is a P-(1,0,0) substrate whose concentration is 10'
It is in the range of 2 to 10 r S cm73. An n-channel B2 with a thickness of 5 to 15 μm and a concentration of 1 to 5×10′30 is formed on the substrate 1 by an epitaxial method or the like. A source region 5 and a drain region 3 made of a shallow n-diffusion layer.
are formed in a self-aligned manner with respect to the gate electrode 7. In addition, the slope γ of the photoelectric conversion characteristic is set to 1 in the drain region 3.
A deep n' diffusion layer 4 with a depth of 1.0 .mu.m or more is formed in order to reduce the leakage (crosstalk) of optical signals to adjacent pixels. 6 is thickness 200
A gate insulating film of ~1000 A is made of, for example, poly S1 so as to surround the source region 5, and the film thickness is 500 A.
Gate electrodes 7 of 08 or less are formed. 8 is a drain electrode, 9 is a source electrode, and 10 is an insulating film. The drain electrode 8 and the source electrode 9 are formed of polyimide, silicide, or the like.

Next, the planar dimensions of one pixel will be explained.

Reducing the planar dimension of one pixel enables a high-resolution, high-density image sensor, and is an important parameter for an image sensor. In FIG. 7, Ll is the radius of the source contact 5', which with current technology has a length of about 1.0 μm in order to sufficiently reduce the contact resistance. L2 is the overlap between the source contact 5' and the source electrode 9, which currently requires about 1 .mu.m to maintain stable contact. L3 is the gap between the source electrode 9 and the gate electrode 7, and is required to be about 1 μm for stability of photosensitivity. 4 is the gate length, and the photosensitivity is most stable when it is 2.0 μm. L5 is the length of the shallow drain region 3, which is approximately 1 μm.

Further, L6 is the width of half the deep drain region 40, and 1
It is about μm.

[Problem that the invention seeks to solve]

From the above, the radius of the MO5SIT device ends up being about 7 μm, and the minimum pixel is about 14 μm, which results in a pixel pitch of about 10 μm using the one spatial pixel shift method. Here, Ll, L4. L5. L6 will become smaller as technology improves, but the method will be similar to the current method.

Therefore, the pixel size is reduced. For L2. L
3 needs to be changed methodically.

In view of the above points, it is an object of the present invention to provide a solid-state imaging device that can be easily miniaturized, thus achieving high resolution and high integration, as well as having high sensitivity and high uniformity.

[Means and effects for solving the problem] In order to achieve the above object, in the present invention, in a horizontal MO3SIT, the source contact is formed by a self-alignment line with the gate electrode surrounding the source, and a transparent source electrode is formed on the self-alignment line with the gate electrode surrounding the source. will be established.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of the present invention. This lateral MO3SIT is an N-channel type, with 11 being a P-substrate, 12 being an n-equivalent layer, 13 being a shallow drain, 14 being a deep drain, 15 being a source diffusion layer, 16 being a gate insulating film, and 17 being a source diffusion layer. A gate electrode is provided to surround 15, 18 is a drain electrode, and 19 is a source electrode, which is made of poly-Si, ITO, or SnO of 1000 A or less.
It is made of a material that can be considered transparent in the visible light region of 2nd grade. 20 is an insulating film.

As is clear from FIG. 1, according to this embodiment, the source contact 15' is formed in self-alignment with the gate electrode 17, so that the margin for alignment of L2 in FIG. No spacing is required.

Further, since the source electrode 19 is formed of a material that can be considered transparent, the gap L3 for making the photoelectric conversion sensitivity uniform in FIG. 1 is also unnecessary. As a result, the minimum pixel size was approximately 10 μm, and by the spatial pixel shifting method, it was ~7 μm.
It becomes possible to reduce the pixel pitch to m. In addition,
The above degrees are shown in Figure 1 with LIO=1μm and L20
=2. um, L30 = 1 μm.

It was calculated assuming L40=1 μm.

Next, a process for realizing the above self-aligned contact will be described. Various types of this process can be considered, but the first example is IBBETransaction
on 81ectron Devices, vol.
, HD-29, Nα2, pp243-247.19
Si3N4fi1mSelf-ASi announced in 1982
3N4fi1 Liftoff Technique
for 5elective oxidation (SA
A process applying the LTS method will be described with reference to FIGS. 2A to 2C.

In FIG. 2A, after a N layer 22 is formed on a P-substrate 21, a gate insulating film 24 is formed, and then a gate electrode 25 is formed. Next, a resist film 26 is applied, and unnecessary gate electrodes are removed using RIB (Reactive Ion), leaving the resist only on the region that will become the gate by photolithography.
After removing by I/I (IonImp) method etc.
An n+ source diffusion layer 23 is formed by a method such as lantation. After that, ticR (electron Cyc
The Si, N, film 27 is coated by a rotron resonance method, and then the resist and the Si3N film on the resist are removed by a lift-off method.

Thereafter, as shown in FIG. 2B, after surrounding the gate electrode with an insulating film 28 by oxidation or other means, selectively using a Si3N film 28,
7 is removed, and a new source transparent electrode 29 is formed as shown in FIG. 2C.

FIGS. 3A-3D are diagrams illustrating a second process for realizing self-aligned contacts. In FIG. 3A, after forming a N layer 32 on a P-substrate 31, a gate insulating film 3
form 3. After that, a gate electrode 34 is formed, and an insulating film 35 is formed thereon. Next, a resist 36 is formed on the insulating film 35, and then a resist window is formed at a location where the source diffusion layer 38 and the like are to be formed by photolithography.

Thereafter, as shown in FIG. 3B, the portions of the insulating film 35 and gate electrode 34 where the resist window is formed are removed by etching means such as old ε, and then a source diffusion layer 38 is formed by the I/1 method or the like.

Next, as shown in FIG. 3C, after removing the resist 36,
An insulating film 37 is formed by LPCVD method or the like.

Thereafter, as shown in the third diagram, the insulating film 37.degree. 33 on the n+ source diffusion layer 38 is etched by anisotropic etching using the E method. By performing this anisotropic etching,
Electrical insulation between the gate electrode 34 and the subsequently formed transparent electrode 39 is ensured by the sidewall insulating film 37.

FIGS. 4A to 4D are diagrams illustrating the third process. Fourth
In Figure A, a N layer 42 is formed on a P-substrate 41, and then a gate insulating film 43 is formed.

Next, a gate electrode 44 made of, for example, PO+JSi, which can be converted into an insulating film in an oxidizing atmosphere, is formed.

Thereafter, an insulating film 45 is formed on this gate electrode 44, a resist 46 is applied thereon, and then a resist window is opened at a location where a source diffusion layer 48 is to be formed by photolithography.

Thereafter, as shown in FIG. 4, after removing the insulating film 45 and gate electrode 44 in the resist window portion by etching means such as old ε, the source diffusion layer 44 is etched by I/1 method or the like.
form 8.

Thereafter, as shown in FIG. 4C, after removing the resist 46, the gate electrode 44 is oxidized and an insulating film 47 is formed on the side surface thereof.
form.

Next, as shown in the fourth diagram, after etching the gate insulating film 43 on the diffusion layer 48 using RIB or the like, a transparent electrode 49 is formed in this portion.

FIGS. 5A to 5C are diagrams illustrating the fourth process. In FIG. 5A, after forming a N layer 52 on a P-substrate 51, a gate insulating film 53 is formed.

After that, a gate electrode 54 is formed, and a resist 5 is formed thereon.
form 5. Next, the source diffusion layer 5 is
A resist window is opened at the location where the gate electrode 54 and the insulating film 5 are to be formed.
3 is removed by the RIB method or the like.

Thereafter, as shown in FIG. 5B, the resist 55 is removed and oxidized. Note that for the gate electrode 54, a material with a faster oxidation rate than the N layer 52 is selected. For example, when the N layer 52 is made of Si, the gate electrode 54 is DOPO3 (
Doped POly 5ilicon). In this way, an insulating film 57 with a thickness of, for example, about 3000 Å is formed around the gate electrode 54, and an insulating film 59 with a thickness of 1000 Å or less is formed on the N layer 52.

Next, as shown in FIG. 5C, etching is performed using a method such as RIB until the insulating film 59 on the N layer 52 is removed, leaving an insulating film 57 with a thickness of, for example, 2000 Å or more on the gate electrode 54. Thereafter, a source diffusion layer 56 is formed using the I/1 method, and then a source transparent electrode 58 is formed.

FIGS. 6A to 6D are diagrams illustrating the fifth process. In FIG. 6A, after forming a N layer 62 on a P-substrate 61, a gate oxide film 64 and a gate 513N4 film 6 are formed.
5 is formed, and a gate electrode 66 is formed on this gate Si, N, film 65. After that, resist 67 is applied and n
''After removing the resist in the portion where the source diffusion layer 63 is to be formed by photolithography, the unnecessary gate electrode 66 is removed using the resist as a mask.

Thereafter, as shown in FIG. 6B, the resist 67 is removed and the gate electrode 66 is oxidized to form an oxide film 68 having a thickness of, for example, about 3,000 layers. Note that the gate oxide film 64
The thickness is about 500 oxidized. Here, the gate oxide film 64
Since there is a gate 513N4 film 65 thereon, the thickness does not change even in an oxidizing atmosphere.

Next, as shown in FIG. 6C, N
+The gate S+3N4 film 65 and the gate oxide film 64 on the diffusion layer 63 are sequentially removed. Here, the gate oxide film 64
When the etching is stopped, the oxide film 6 on the gate electrode 66 is
8 remains, for example, with a thickness of 200 OA or more. After that, an n+ source diffusion layer 63 is formed by the I/■ method, and then a source transparent electrode 69 is formed as shown in the sixth diagram.

〔Effect of the invention〕

As described above, according to the present invention, a miniaturized horizontal MO3SIT image sensor having a pixel pitch of about 7 μm can be obtained using, for example, the spatial pixel shifting method.

Further, since the source contact is formed by a self-aligned line and a transparent source electrode is provided, the process becomes easy and variations in sensitivity within a chip and between chips can be reduced. Furthermore, since the source electrode fills the hole in the gate electrode, it is also useful for flattening the chip surface. Furthermore, the self-aligned source contact can also be applied to FETs forming peripheral circuits, thereby improving the degree of circuit integration.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2A-
C is a diagram explaining the first example of the manufacturing process, FIGS. 3A-D are diagrams also explaining the second example, and FIG. 4A
-D is a diagram explaining the third example, FIGS. 5A-C are diagrams explaining the fourth example, and FIGS. 6A-D are diagrams explaining the fifth example.
FIG. 7 is a diagram illustrating a conventional technique. 11... Substrate 12... Epitaxial layer 13... Shallow drain 14... Deep drain 15... Source diffusion m 15'... Source contact 16... Gate insulating film 17... Gate electrode 18...Drain electrode 19...Source electrode 20...Insulating film Patent attorney Oki Sugimura
Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] 1. A high-resistance epitaxial layer containing impurities of a different type from that of the substrate is provided on a high-resistance semiconductor substrate, and a source and drain containing impurities of the same type as that of the epitaxial layer are formed on the surface of this epitaxial layer. A solid-state imaging device comprising a static induction transistor in which a gate electrode is formed between the drain and the source via an insulator so as to surround the source, so that a source-drain current flows parallel to the substrate surface. 1. A solid-state imaging device, characterized in that a contact of a source electrode to be connected is formed by self-alignment with the gate electrode, and a transparent source electrode is provided on the source contact.