JPS62140178A - Image editing processor - Google Patents

Abstract

PURPOSE:To attain a compact image editing processor together with a fast processing speed by using an image memory which decides the type of image data by coding plural picture elements and holds the picture data equivalent to plural picture elements and holds the picture data equivalent to plural pages. CONSTITUTION:Image data given from a reader 1 is converted into signals Y, I and Q by a converter 11 and compressed by a compressor 2 to be stored in a disk memory 3 for image data files. Then the contents of the memory 3 are read out to image memories 5-1 and 5-2 containing plural pages and processed and edited. In such a case, the data is transferred to a memory 5 at one side from the disk 3 by a pipeline processor 4. Then the data is edited and developed while it is transferred to a memory 5 at the other side from the other memory 5 as raster data. While the image data on the memory 5 are processed and corrected after various types of processing applied by a CPU 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (I) Technical Field The present invention relates to an image editing processing device that can edit high-density images at high speed.

(+1) Conventional technology Traditionally, this type of equipment has been very expensive and large.

Moreover, it has the drawback of long processing time, and has been used only as a printing system. This was equipment costing hundreds of millions of yen, such as Cytex's RENBONS 300 series and Crossfield's 5TUDIO-800 series of base make-up systems.

(m) Object The present invention eliminates the drawbacks of the conventional systems described above and provides an image editing processing device that is compact, inexpensive, and capable of high-speed processing. A feature of the present invention is that the huge amount of image data generated when reading color images at high resolution,
It compresses data in a format that is easy to edit, reduces the image data to a fraction of the size, corrects and edits the image data that would be required during actual editing, and outputs the results in high resolution and high gradation. .

Overview In general, an image editing device requires the above two editing functions. The former is generally referred to as a hardware pipeline processor, and in this device, executes certain image editing functions that require high speed. Regarding the latter, processing by the CPU is performed interactively with humans (
(It may take some time).

That is, the former pipeline processor performs, for example, affine transformation (enlargement, reduction, rotation) that determines the image layout, spatial filter processing (image enhancement, smoothing, etc.), and color conversion processing using a lookup table (LUT). Mainly performs sequential processing of images such as

The latter processing by the CPU generally performs complicated processing and processing that is difficult to implement in hardware. Here, it refers to processing such as cutting out an image into an arbitrary shape, copying the cut out image to another location, and modifying a part of the image. These processes are generally creative processes created by the operator. It is acceptable even if it takes some time.

However, this function needs to be highly functional.

In order to implement the above two editing processing functions in the largest format, the system architecture of the editing device is required.
It is necessary to think from

In other words, so that both processes can be executed with sufficient functionality and speed,
In order to do this, it is necessary to consider the system structure of the system, the format of the image data handled, the flow of signals, the analysis of functions, etc.

As a result of various studies, the following conclusions were reached regarding the system architecture for a color image editing device.

(1) To perform image editing, image data must be stored as compressed data.

(2) A good compression method is vector quantization, which has an m×m block as one code.

(3) As for hardware processing, it is most rational to perform sequential processing during transfer during the reading process (raster tenter) of a hard disk or the like.

In (1), in order to perform high-resolution, high-gradation image editing processing, the image data capacity is extremely large. For example, A4. When reading lpage in color at 16 pel/mm, the data capacity is approximately 48 Mbytes for 83 colors of R, G. Interacte the image editing mentioned above,
In order to perform this process quickly and with high functionality, it is important to compress the color 1 image data and make it easier to edit. It was concluded that the vector quantization method (2) is optimal for this purpose.

In (3), when processing at high speed with hardware, -
When data in a file such as a hard disk is transferred to memory and processed by hardware on the memory,
There are two processes involved, a transfer process and a processing process, and extra processing time is required. Therefore, if processing can be performed simultaneously during the transfer process, only one process is required, and faster processing becomes possible.

Based on the above conclusions, we determined the system architecture and were able to realize a high-quality, high-performance, high-speed image editing processing device.

A detailed explanation will be given below based on examples.

(IV) Embodiment FIG. 1 is a block diagram of an image editing installation showing an embodiment of the present invention. The image data read by League 1 (for example, 8-bit digital data for R, G, and B) is converted into a signal by a converter 11 and converted into a luminance (Y) signal and color difference signal (1, Q) used in the NTSC signal. be done. Such conversion can be obtained, for example, by matrix calculation using R, G, and H data. Here, the coefficients of the conversion matrix are modified as appropriate in accordance with the color separation characteristics, γ characteristics, etc. of the reader. These Y, I, and Q signals are compressed by a compressor 2, which will be described later, and stored in a disk memory 3 for image data files. The image data on the disk is Im
The data is read out onto IC memories called age memories 5-1 and 5-2, and processed and edited.

Therefore, in order to perform high-speed processing, basic processing is performed by transferring data from the disk to one Image memory using a hardware pipeline processor 4, and from this memory to the other Image memory, data is transferred as raster data. Edited and developed during the process.

On the other hand, the image data on the image memory 5 is subjected to various processes and processed and corrected by the CPU 8. The editing process is displayed on the color CRTIO by the CRT controller 9, and the editing status can be monitored. The edited result is returned to the original image data from the image memory 5 through the decoder 6, and the converter 12 converts this image data into color signals (Ye 11ow, Magenta) compatible with the printer.
, Cyan, Black) and Co1or Pr
1nter 7. Kono edge.

CPU 8 corresponds to the flow of pre-processing data and post-processing data.
Instructs the input/output controllers 13-1 and 13-2 to control the data flow path.

Next, a method for compressing image data will be described.

If the spatial frequency of the Y signal, which is luminance data, is well preserved by dividing it into three color signals of luminance and chrominance, such as Y, I, and Q, the spatial frequency of the chrominance and Q signals, which are color difference signals, will be It is known that there is little visual deterioration in image quality (cutting of high frequency components to some extent).

A data compression method is conceivable in which the color information is represented by the average value of (m is an integer) and the amount of data of a color image is reduced. I
, Q signal block size, such as 2X2.4X4.6X6, is selected depending on the required image quality and allowable memory capacity. For example, set the block size to 4×4
Then, as mentioned above, the memory capacity of A4, l page is 48MByte, and the Y signal is 16MByte+I,
Q signal 2MByte = total 18MByte, about 2.7
The compression ratio is

On the other hand, for the Y signal, unlike the compression of the I and Q signals, a compression method that leaves sufficient resolution data is required.

The first method is a block encoding method.

This method calculates the average value and standard deviation σ of pixel data X within an m×m block. Next, the gray level information for each pixel is expressed in about several bits.

For example, this can be realized by requantizing the calculated value of (x-x)/σ. This compressed data format is 9F
2 (41) The old standard deviation is followed by the grayscale information of each pixel, and the order of the grayscale information corresponds one-to-one to the pixel position within the block. Therefore, by changing the order of this grayscale information, it is possible to rotate pixels within a block.

The second method is an m x m pixel vector quantization technique.

This method converts pixel data in an m×m block into an average value
Data compression is measured by expressing the standard deviation σ, a code representing the rotation of the image, and a code representing the pattern of the image. This compressed data format is as shown in FIG. 2(b). Here, the code representing rotation is, for example, an image pattern within an m x m block.
, 180°, and 270' rotation, and in the vector quantization method using the same pattern code, this is the code representing this angle. In this example, O', 90',
180'.

It is represented by 4 patterns of 270° and 2 bits.

In this method, pixels within a block can be rotated by manipulating a rotation code.

Next, affine transformation will be explained.

In affine transformation, images are enlarged, reduced, moved, and rotated.

The address on the input memory of the input image is (ys +
ys ), the main scanning direction magnification is α, the sub-scanning direction is β, the rotation angle is φ, and the rotation center coordinates are (χc, y
c), When the amount of movement in the main scanning direction is χm and the amount of movement in the sub-scanning direction is ym, the address in the output memory (χD,
yO), the following relational expression holds true.

0 @ Given χo, yo, χS, :! according to 〈■,■.
/ Searching for S. This can be realized, for example, with a configuration as shown in FIG. The explanation will be given below according to FIG. χS is 0
When calculating according to the formula, the initial value offset (DC component) is set in the register 31 as the initial value. Further, a sub-scanning synchronization increment value and a main-scanning synchronization increment value are respectively set in the registers 32 and 37. Setting of this series of values is executed by the CPU according to the reduction ratio and rotation angle.

FIG. 4 is a timing chart showing the relationship among the page synchronization signal, sub-scanning synchronization signal, and main-scanning synchronization signal of the circuit of FIG. 3. When the page synchronization signal falls, generation of sub-scanning synchronization signals is started and is generated for the number of scanning lines existing in the page. A main scanning synchronizing signal is generated at the fall of the sub-scanning synchronizing signal, and is generated for the number of data existing in the scanning line. These signals are generated by a synchronization signal generation circuit (not shown). While the page synchronization signal is at a low level, the selector 33 outputs the value held in the initial value register 31. The 34 adders execute addition at the falling edge of the sub-scanning synchronization signal. The output of 34 is latched to 35 by sub-scan latch synchronization. Further, 36 outputs the output of 35 while the sub-scanning periodic signal is at a low level. Adder 38 adds the output of 36 and the main scanning synchronization increment value of 37 at the falling edge of the main scanning synchronizing signal, and its output is latched in 39 at the rising edge of the main scanning synchronizing signal. The latch 35 holds the address of the input side to which the data at the beginning of the scanning line corresponds, and the latch 39 provides the address of the input side to which each data in the scanning line corresponds. ys can also be determined in exactly the same way according to the equation (input surface).

The address thus obtained is an irrational number because COSφ, Sinφ, etc. are generally irrational numbers. On the actual machine,
A decimal number with sufficient number of bits. An integer address near this decimal address is determined as an input address. In other words, the four points on the input side obtained by rounding down the decimal part of χS and ys (that is, only the integer a part) and adding 1 to it (the value obtained by adding 1 to the integer part and truncating the decimal part) Find interpolated data from the values as follows. The data obtained through this interpolation is used as the data at the point (χo, yo) of the output side address. FIGS. 5 and 6 show the correspondence between addresses on the source side and the destination side. A square grid indicates the address grid on the destination side, and the center of the square is an integer address. A parallelogram grid represents the address grid on the source side, and the center of the parallelogram is an integer address. Point A (χ
o, yo), 4 points a, b, c, dc7) are determined. As shown in Figure 6, the value V (A) of point A is expressed as a,
Values of each point b, c, d■(a), V(b)
, V (c), V Cd-), V (
A) = (1-δ)(ie-e,) V (a) +
(1-ε) V (b)+(1-δ)εv(c)+δε
V (d) −−−−−−−−■ Here, δ is the decimal part of χS, and ε is the decimal part of ys.

FIG. 7 is a block diagram of a circuit for calculating equation (2). 8th
The figure is a diagram explaining FIG. 7, and 71°, 72, and 73 all have the configuration shown in FIG. 8. In Figure 7, V (E) = (1-δ)V (a) + δv (b)v
(F) = (1-L) V (c) + δV (d). In FIG. 8, 83 is a circuit for calculating lk using the fractional parts of χS and ys.

Thus, the obtained output data is output from the PLP 4 to the compressor 2-2 as a result of affine transformation, and is compressed again and stored in the image memory 5-1 or 5-2.
Output to.

The compressor has two sets of line buffers for the number of rasters required for compression, one of which is used to capture the output data of PLP4, and the other is used as a compressed divided image memory for data that has already been captured. It performs operations such as outputting to . The situation is shown in FIG.

As described above, the affine transformation algorithm in this embodiment outputs raster data (in this case, sequentially read data from a file) to the destination side.

At this time, the source memory (in this case, the image memory) is randomly accessed and the original data is input. Therefore, since the affine transformation hardware is pipelined, it is executed in the process of data transfer from the source side image memory to the destination side image memory, making it possible to perform extremely high-speed conversion.

Next, the CRT controller 9 will be explained.

FIG. 10 is a diagram showing the functions of the CRT controller 9.
5 is a compression memory, 9 is a CRT controller, 10 is a color CRT, 8 is a CPU, and 356 is a parameter register set by the CPU. In the present invention, memory addresses are treated as two-dimensional (X and Y), but it is also possible to convert these addresses into one-dimensional addresses. 414F= of the CRT controller in FIG. 10 creates a rectangular area of arbitrary size χw + yw) with an arbitrary start address (χ0°yo) of the memory 5, and performs YD dots,
This is to display and output the resolution of horizontal xD dots on a CRT. Any value χO, :! 10. In addition to the range, χw and yw may be restricted to be multiples of 2 or 4. FIG. 11 shows an embodiment of this CRT controller, in which 101, 102, 103.degree. 104 are parameter registers, 105, 106 are adders, 107, 108 are selectors, and 109.degree. 110 are address latches or registers.

112 is a CRT synchronization circuit, 121 is a horizontal synchronization signal, 12
2 is a vertical synchronization signal, and 123 is a pixel clock. 11
1 is the data latch, 1'28 is the color signal read from the memory, 124 is the color signal to the CRT, 125
is a horizontal address (X), and 126 is a vertical address (Y). The vertical synchronization signal 122 is generated by the CRT synchronization circuit 112.
is generated, and further a horizontal synchronization signal 121 and a pixel clock 123 are generated. The address taken into the Y address latch 110 by 121 is 1 while 122 is ON.
Since the opening price yo102 is selected depending on 08,
y.

becomes. Also, by 123, the X address chichi 109
Since the opening price χolol is selected by 107 while 121 is ON, the address taken in is χO. In other cases, the X address check 109 is 1 clock (
= 1 dot) is increased by χw/XD, the memory address is updated, and scanning in the χ direction is performed. When the horizontal synchronization signal 121 is turned ON and the pixel clock is turned ON, the X address latch 109 is reset to χO. Also, the Y address latch 110 is activated every l horizontal synchronization! The memory address is increased by /w/Yo, the memory address is updated, and a scan is performed in the y direction.

Figure 12 shows a CR that allows rectangular composition on a CRT.
It is a figure showing the function of T controller. Rectangular images 130 and 131 displayed on the CRTIO are images stored as areas 132 and 133 on the memory 5.

Currently, the image 130 is superimposed on the image 131, and the portion of the image 131 where the image 130 is placed is not displayed. This can be obtained by expanding the configuration shown in FIG. FIG. 13 shows an example of its configuration. In FIG. 13, 134, 135.

136 and 137 are intra-region address generation modules with the same internal configuration, 134 is a horizontal address generation module for the area with the highest priority, 135 is also a vertical address generation module, and 136 is an area with the second priority. 137 are horizontal address generation modules, and 137 are also vertical address generation modules. 148 is a horizontal display address counter, and 149 is a vertical display address counter, each of which outputs a horizontal display address 15o and a vertical display address 151. Next, the address generation module will be explained.

Inside 134, 138 is a register that holds a display start address, and 139 is a register that holds a display end display address.

152 and 140 are comparators, and a logic circuit 141 determines whether the signal 150 is included in the register 138 and register 139 area. If it is included in the area,
This address generation module has the right to output a memory address, however, only when both x and Y are established, and the address output by this module 134 and 135 is possible when both signals 153 and 154 are satisfied. When the logic circuit 159 becomes true, the output enable signal 155 is generated, the output buffer 147 is enabled, and the contents of the address register 146 are output to the memory horizontal address bus 125. Similarly module 135
The address is output from the memory vertical address bus 126. If the in-domain signal of either module 134, 135, ie 153 or 154, goes false, the output of logic circuit 159 will also go false, and the outputs of modules 134, 135 will be disabled. At this time, if the in-area signals of the modules 136 and 137 having the second priority, that is, 156 and 157, are true, the output of the logic circuit 160 becomes true, and the address output of the modules 136 and 137 is transferred to the memory address bus 125, 126. When the output of the logic circuit 160 becomes false, the module with the third priority is tested, and the address output tank is subsequently shifted to modules with lower priorities one after another. Of course, when a module with a higher priority than itself acquires the address output tank, that higher module will output the address. On the other hand, the output address will be explained. In the module 134, a register 143 holds a read start memory address, and a register 142 holds an address increment value.

145 is the address register 146 while 153 is false
A selector 144 is configured such that the output of the register 143 is input to the register 146;
This is an adder that adds the contents of 2 and increments by 4. When signal 153 goes true, register 146 is incremented by the contents of register 142 every clock. As described above, with the configuration shown in FIG. 13, rectangular composition on the CRT screen shown in FIG. 12 can be performed.

FIG. 14 is a diagram showing the functions of the CRT controller, which enables arbitrary free-form images to be synthesized and output on the CRT. In FIG. 14, 306 is a mask shape memory, and in the example of FIG. 814, one image area 13
A mask area 162 is defined corresponding to 3, a mask area 161 is defined corresponding to the image area 132, and a mask area 161 is defined corresponding to the image area 132.
A heart-shaped mask is written on it. At this time, as shown on the CRT in FIG. 14, the image area 132 is cut out into a heart shape and displayed superimposed on the image area 133.

The CRT controller 9 performs such processing by pre-reading the mask shape memory 306 before reading out the image memory 5. For example, in this embodiment, a line one line ahead in the vertical address direction is read out to control the mask. When the mask image data to be displayed at vertical address y in CRTIO in FIG. 14 is a mask advanced by yo from the beginning in area 133 and by yl from the beginning in area 132, mask area 1 on mask shape memory 306
62 represents line yO+1, and area 161 represents line y1+1.
It is possible to read each of the data and prepare it for the vertical address y+1 of the next CRTIO. 815 diagram is C
This is an example of an RT controller.

FIG. 15 corresponds to the pair of horizontal and vertical modules of FIG. In Figure 15, 161.162,1
1Er7, 168 is a register that holds a display address, and as in the previous embodiment, the rectangular area on the display specified by this register is controlled by this module. A 2-line mask data buffer 173 is capable of holding two masks, and is a feature of this embodiment. The mask data read in advance by one vertical address is addressed by the counter 174 and input to the logic circuit 176. The logic circuit 176 outputs this signal as a true output when the addresses xD and yD on the display generated by a counter (not shown) are included in the rectangular area to be handled by this module and the mask data is ON. is input to the logic circuit 177, and when the signal PRIOR from a module with higher priority than this module is true, the memory address
Data address buffers 179 and 178 are driven to output T and YDAT. The mask data MSKDT remains in the mask data buffer 17 even during the transfer of data to be displayed.
3 continues to load. The mask data to be used is read from the mask shape memory 306, but it needs to be read out before the display data address, so the mask address register 165, which holds an address one timing ahead of the data address registers 166 and 172,
171. At this time, when there are a plurality of modules, masks may be read simultaneously from different modules, but collisions are prevented by giving permission to use the mask address bus in a time-sharing manner using the ENMSK signal.

As described above, according to this embodiment, it is possible to display images of arbitrary shapes in a superimposed manner on a display at high speed and with high definition. It is characterized by the fact that it can be processed in no time.

Next, image editing functions and operations will be described.

Table 1 shows various image editing functions in this device.

FIG. 16 is a schematic flowchart of editing operations.

Now assume that you want to edit and combine multiple images.

Image input processing 200 means the operation and processing of reading the plurality of images and storing them in a memory for image files. At this time, the aforementioned compressed data is used to reduce the file capacity. Thereafter, in step 204, it is selected whether to perform component processing or layout processing. Parts processing 201
is a table that performs processing such as correction stand conversion within one image, and item A in table 1 generally applies. Layout processing 2
02 corresponds to item B in Table 1, which performs affine transformation that performs processing such as image rotation, scaling, and movement, and compositing processing in the process of determining the layout of multiple image data as completed parts. do.

Here, component processing requires direct conversion of image data, but layout processing requires layout parameter information (
For example, it is sufficient to memorize the image data (for example, the magnification ratio, the position after rotational angle movement, etc.); therefore, the layout processing can be performed by thinning out the image data, displaying it on the CRT display 10, and extracting the parameters.

Once this processing is completed, the actual image data 203
I do. This synthesizes and edits the completed part data onto the image memory under the layout O parameter. After this processing is completed, the data in the image memory is transferred to the printer and output to the printer 206 is performed.

FIG. 17 shows a detailed explanation of the image input process 200. First, the league reads the original 207, compresses the data using the compressor described above (208), and then registers it as a file in, for example, a hard disk. This operation is repeated as long as there are originals, and ends when there are no more originals to read (210).

FIG. 18 shows the contents of component processing. First, a processing item is selected 211 to determine what to do.

First, the color correction 212 transfers the image data from the File to the image memory, and since the image memory also serves as the video memory of the Display, it is immediately output to the CRTIO. ), perform color correction while looking at the CRTIO. This operation does not change the image data in the image memory and looks up the output to the display (CRT) 1o.
Table (LUT) (7) Change (2)
16). The LUT used when the image becomes a desired image is memorized (220).

Contour correction 213 similarly places a spatial filter calculator on the cable that outputs to the CRT, and does not modify the actual image data. Then, information on the spatial filter (for example, coefficients of the well-known Laplacian) is stored (221). Next, the cutout mask 214 is a 1-bit mask placed in parallel with the image memory.
Rewrite the mask memory of p 1 ane. This determines the image area and does not modify the actual image data (218). Other processing is called actual data correction 215. This rewrites the real image data written on the image memory by directly accessing it from the CPU, and writes, erases, and copies images on the real image. When the above processing is completed, the actual data and mask data are registered 222 as a file.

FIG. 19 describes layout processing.

First, image data is written from the file to the image memory (223). At this time, as described above, a plurality of image data may be taken into the image memory using thinned data. The image data of the plurality of images are synthesized and scaled (225) by the CRT controller and outputted onto the CRTIO. At this time, the rotation of the image is performed using a raster operation (RO) using another region Hairfin transformer 4 on the image memory.
P) (224). On the other hand, since the CRT controller can only change the magnification by an integer, the converter 4 similarly performs arbitrary magnification and data creation 226 for a mask memory that limits the output image area is performed next.

The above operations are performed on each image, and layout parameters are extracted (227).

In FIG. 20, a final image is formed based on the above component data and layout parameters. This process can be completely automated. First, the image component data that is superimposed on the bottom is processed first. The layout parameters and mask data of the first image are the pipeline AFF.
INE conversion register, LUT and mask memory (this is a 1-bit memory placed in parallel with the image memory)
Data from the 0th order file, which is set to 0, is transferred to the image memory via these pipeline processors. As a result, the Lascou Operation (ROP)
Processed by

This processing is equal to the number of parts data (only nmaX)
The image memory is repeatedly overwritten (2
30.231).

Next, we will discuss output to the printer.

The image data resulting from editing is created on the image memory and transferred to the printer side. The state of output from the image memory differs depending on the output method 1 of the printer, for example, whether it is field sequential, line sequential, or dot sequential. Such conversion is performed in converter 12 of FIG. Prior to that, the compressed data is decoded into normal pixel data by a decoder 6.

Usually, one printer 7 is connected. However, by connecting multiple printers, faster output is possible, which is especially important in the publishing and printing fields, which require a large amount of output.

The format of storing image data in this image red memory is to compress the density data and restore it back to density data, so the hue difference that occurs when connecting to multiple printers (
This varies depending on the performance of each printer) from one density data to another density data.
Conversion and correction can be performed using kUp Table (LUT).

(This is usually difficult if the image memory is stored in a binarized state.) The converter 12 includes an adjustment mechanism for individual printers using such a LUT.

The color printer 7 outputs an image based on the corrected image data using a conventional method 1 such as a dither method.

(V) Effects As described above, the present invention enables image editing to be performed at high speed and with high functionality by performing image editing using compressed data and by adopting a system architecture suitable for high-speed editing. It is.

Fig. 2 is an explanatory diagram of encoding, Fig. 3 is a block diagram of the address generation section of the affine transformer, Fig. 4 is a timing chart of the address generation section, and Figs. 5 and 6 are diagrams of the original image and A diagram showing the address correspondence of processed images, Figures 7 and 8 are block rotation and block diagrams of the data interpolation circuit, Figure 9 is an explanatory diagram of compression after pipeline processing, Figures 10 and 12
14 are conceptual diagrams of the CRT controller, FIGS. 11, 13, and 15 are block diagrams of the CRT controller, and FIG.

FIG. 17, FIG. 18, FIG. 19, and FIG. 20 are flowcharts showing the image editing processing procedure.

Claims (11)

[Claims] (1) In an image editing processing device that is equipped with an image input device and an output device that outputs a processed image, and edits and processes one image from multiple images, the image data format is a plurality of pixel data. An image editing processing device that has an image memory that holds multiple pages of randomly accessible image data that has been collected and encoded. (2) The image editing processing device according to item 1, wherein the image memory includes at least two pages, one before editing and one after editing. (3) An image editing processing device according to item 1, wherein the image memory also serves as a video memory for outputting to a display. (4) In item 3, the image editing processing device includes an affine transformation arithmetic unit that takes in unedited data from an image memory by random access and outputs processed data in the form of raster data. (5) An image editing processing device according to item 4, wherein a plurality of outputs of the affine transformation computing unit are collected, encoded, and stored in an edited image memory. (6) In item 5, the encoded image data is a luminance signal (
An image editing processing device consisting of color difference signals (I, Q) and color difference signals (I, Q). (7) In item 5, the image editing processing device wherein the encoded data form of the image data has average value data and rotation data of m×m pixels in the code. (8) In paragraph 6, the Y, I, Q signals are Y signal and I,
An image editing processing device in which the constituent block size differs from that of the Q signal. (9) In item 8, the image editing processing device has different code formats for the Y signal and the I and Q signals. (10) In item 1, the image editing processing device includes a decoder for decoding encoded image data when transferring data in the image memory to the output device. (11) In item 10, the image editing processing device includes a converter for converting decoded image data into printer signals.