JPS62140176A - Image editing processor - Google Patents

Abstract

PURPOSE:To attain a compact design of an image editing processor together with a high-speed editing operation and high performance, by using color image data as coding data and using an image memory which is capable of random access. CONSTITUTION:Data on images R, G and B given from a reader 1 are converted into signals Y, I and Q by a converter 11 and stored in a disk memory 3 via a compressor 2. The data of the memory 3 is transferred to an image memory 5 by a pipeline processor 4 and also edited and developed on a memory 5 by a raster operation. The data of the memory 5 is processed with correction by a CPU 8. Thus the data is given to a decoder 6 from the memory 5 and turned into the original image data. This image data is converted into color signals by a converter 12 and supplied to a color printer 7. Here the signals I and Q represents color information with the mean value of the (mXm) blocks. While the signal Y performs the compression of data with a block coding operation or the vector quantization of the (mXm) picture elements.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to an image editing device that can edit high-density images at high speed.

(11) Prior Art Conventionally, this type of apparatus had the drawbacks of being extremely expensive, large-sized, and requiring a long processing time, and was only used as a printing system. For example, Cytex's Renbonsu 300 series or Crossfield's 5TUD
It was a device costing hundreds of millions of yen, like the IO-800 series page make-up system.

(II+) Objective The present invention eliminates the drawbacks of the conventional systems described above and provides a compact, low-cost device capable of high-speed processing. A feature of the present invention is that the huge amount of image data generated when reading an image at high resolution is compressed in a format that is easy to edit, reducing the image data to a fraction of the original size, and reducing the amount of image data required during actual editing work. It corrects and edits the images, and outputs the results in high resolution and high gradation.

Overview In general, an image editing device requires the above two editing functions. The former is generally referred to as a hardware pipeline processor, and in this device executes certain image editing functions that require high speed. Regarding the latter, processing by the CPU is performed interactively with humans (
(It may take some time).

That is, the former pipeline O processor, for example, performs affine transformation (enlargement/reduction/movement/rotation) that determines the image layout, spatial filter processing (image enhancement/smoothing, etc.), and color processing using the 100kup table (I, UT). Mainly performs sequential image processing such as conversion processing.

The latter processing by the CPU generally performs complicated processing and processing that is difficult to implement in hardware. Here, it refers to processing such as cutting out an image into an arbitrary shape, copying the cut out image to another location, and modifying a part of the image. These processes are generally creative processes created by the operator, and can be tolerated even if they take a certain amount of time.

However, this function needs to be highly functional.

In order to implement the above two editing processing functions with maximum performance, it is necessary to consider the system architecture of the editing device.

In other words, in order to be able to perform both processes with sufficient functionality and high speed, it is necessary to consider the structure of the system, the format of the image data to be handled, the flow of signals, the analysis of functions, etc. .

As a result of various studies, the following conclusions regarding the system architecture for a (color) image editing device were obtained.

(1) To perform image editing, image data must be stored as compressed data.

(2) As a compression method, vector quantization using m×m blocks as one code is preferable.

In (1), in order to perform high resolution/high gradation image editing processing, the image data capacity is extremely large. For example, A4. lpage 16 p e 1/mm
When reading in color, the data capacity for three colors R, G, and B is approximately 48 Mbytes. In order to perform the above-mentioned image editing in an interactive and highly functional manner, an important technique is to compress the color image data and make it easier to edit. It was concluded that the vector quantization method (2) is optimal for this purpose.

The present invention is based on the above conclusion, and the system architecture is
By determining this, we were able to realize a high-quality, high-performance, high-speed image editing processing device.

The present invention will be described in detail below based on an embodiment in which the present invention is applied to color processing.

(IV) Embodiment FIG. 1 is a block diagram of an image editing apparatus showing an embodiment of the present invention. Image data read by reader 1 (
For example, R, G, and B 8-bit digital data) are converted into signals by the converter 11 and converted into a luminance (Y) signal and color difference signals (I, Q) used in the NTSC signal. Such conversion can be obtained, for example, by matrix calculation using R, G, and H data. Here, the coefficients of the conversion matrix are modified as appropriate in accordance with the color separation characteristics, γ characteristics, etc. of the reader. These Y, I, and Q signals are compressed by a compressor 2, which will be described later, and stored in a disk memory 3 for image data files. Image data on the disk is read out onto an IC memory called an image memory 5 and processed and edited. Here, in order to perform high-speed processing, the basic processing is performed by the computerized virtual processor 4, which edits and expands the data onto the image memory 5 by a so-called raster operation during the transfer process from the disk to the image memory.

On the other hand, the image data on the image memory 5 is processed and corrected by various processes by the CPU 8. The editing process is displayed on the color CRTIO by the CRT controller 9, and the editing status can be monitored. The edited result is returned to the original image data from the image memory 5 through the decoder 6, and the converter 12 converts this image data into color signals (Yellow, Magenta,
Co1or Pr1
output to inter 7.

Next, a method for compressing image data will be described.

If the spatial frequency of the Y signal, which is luminance data, is well preserved by dividing it into three color signals of luminance and chrominance, such as Y, I, and Q, the spatial frequency of the 1 and Q signals, which are chrominance signals, will be It is known that there is little visual deterioration in image quality (cutting of high frequency components to some extent).

Therefore, a data compression method may be considered in which, for example, the I and Q signals are represented by the average value of m×m blocks (m is an integer), thereby reducing the amount of data of a color image. As for the block size of the I and Q signals, a block size such as 2X2.4X4.6X6 is selected depending on the required image quality7 and the allowable memory capacity. For example, if the block size is 4X4,
@As mentioned, A4. lpage memory capacity 48MB
yte is Y signal 16MByte e+I, Q signal 2M
Byte = 18 MB in total, resulting in a compression ratio of approximately 2.7.

On the other hand, for the Y signal, unlike the compression of the I and Q signals, a compression method that leaves sufficient resolution data is required.

The first method is a block encoding method.

This method calculates the average value and standard deviation σ of pixel data X within an mXm block. Next, gradation information for each pixel is expressed in approximately several bits.

For example, this can be realized by requantizing the calculated value of (XX)/σ. This compressed data format is shown in Figure 2 (
As shown in a), the average value and the standard parrot deviation are followed by the shading information of each pixel, and the 1lllli order of this shading + PJ information is made to correspond one-to-one to the positions of both vehicles within the block. Therefore, by changing the order of this grayscale information, it is possible to rotate pixels within a block.

The second method is an mXm pixel vector quantization technique.

This method calculates the average value of pixel data in m×m blocks by 1
Data compression is measured by expressing the standard deviation σ, a code representing the rotation of the image, and a code representing the pattern of the image. This compressed data format is as shown in FIG. 2(b). Here, the code representing rotation is, for example, an image pattern in a block of mXm, 90 degrees,
This is the code that represents this angle in the vector quantization method that uses the same pattern code as the one rotated by 180' and 2700 degrees. 0°, 90°, 18 on the wood flow side
0°.

It is represented by 2700 4 patterns and 2 bits.

In this method, pixels within a block can be rotated by manipulating a rotation code.

Next, affine transformation will be explained.

In affine transformation, images are enlarged, reduced, moved, and rotated.

The address on the input memory of the input image is (χs,
ys), the main scanning direction magnification is α, the sub-scanning direction is β, the rotation angle is φ, and the rotation center coordinates are (χC,!/
C), when the amount of movement in the main scanning direction is Xm and the amount of movement in the sub-scanning direction is Ym, the address in the output memory (χ0.
y0), the following relational expression holds true.

@ O □ Po Test ←1 To Hayabusa KI Toya Ichi-) When χS and yS are given to m, χo and yo are found according to ■ and ■. This can be realized, for example, with a configuration as shown in FIG. The explanation will be given below according to FIG. When calculating χS according to formula (2), the initial value offset (DC component) is set in the register 31 as an initial value. Further, a sub-scanning synchronization increment value and a main-scanning synchronization increment value are respectively set in the current ai registers 32 and 37. Setting of this series of values is executed by the CPU according to the reduction ratio and rotation angle. FIG. 4 is a timing chart showing the relationship among the page synchronization signal, sub-scanning synchronization signal, and main-scanning period signal of the circuit of FIG. 3. When the page synchronization signal falls, generation of sub-scanning synchronization signals is started and is generated for the number of scanning lines existing in the page. A main scanning synchronizing signal is generated at the fall of the sub-scanning synchronizing signal, and is generated for the number of data existing in the scanning line. These signals are generated by a synchronization signal generation circuit (not shown). While the page synchronization signal is at Low level, the selector 33 is
The value held in the initial value register 31 is output. The 34 adders execute addition at the falling edge of the sub-scanning synchronization signal. The output of 34 is latched to 35 by sub-scan latch synchronization. Further, 36 outputs the output of 35 while the sub-scanning synchronization signal is at a low level. Adder 38 adds the output of 36 and the main scanning synchronization increment value of 37 at the falling edge of the main scanning synchronizing signal, and its output is latched in 39 at the rising edge of the main scanning synchronizing signal. The latch 35 holds the output side address to which the data at the beginning of the scanning line corresponds, and the latch 39 provides the output side address to which each data in the scanning line corresponds. yo can also be determined in exactly the same way according to the 0 formula.

The address thus obtained is COSφ.

Since sinφ etc. are generally irrational numbers, they are irrational numbers. On a real machine, it will be a decimal number with a sufficient number of bits. An integer address near this decimal address is determined as an output address.

(χD, :YD) in the main scanning direction
inφl+IcosφI), β(ls
Inverse conversion is performed on each integer address existing within an area having a width of inφl+1cosφ1). If this integer address is (Xo, Yo), then (XD, Yo)
The address on the input data side corresponding to (Xs.

Ys) @　　　　　　　　[phase] The following relational expression holds true.

The above equations are successively determined using the circuit shown in FIG.

FIG. 6 is a timing chart of the signals in FIG.

The initial value offset (DC component), main scanning synchronization increment value, and sub-scanning synchronization increment value are each set to 5 by the CPU in advance.
7, 51, and 52 are set in registers. In addition, when there is a change in XD and YD, a circuit (not shown) (for example, composed of a register that holds the value l clocks ago and a comparator that compares the value of the current clock) is used to detect changes in XD and YD, respectively. The gate signal for turning on and off the gate 54 becomes Low. At this time, the gates each independently output values of 51 and 52, and otherwise output a Low level, that is, 50. The adder 55 executes addition upon the falling edge of the main scanning synchronizing signal, and its output is latched into the adder 56 upon the rising edge of the main scanning synchronizing signal. Further, while the sub-scanning synchronization signal is at a low level, the register 59 outputs the value held in the register 57. If not, 58
Outputs the value of the adder. The latch 50 holds the output of 59 at the rising edge of main scanning synchronization, and the adder 658 holds the value held by 50 and 56 at the falling edge of main scanning synchronization.
It performs addition with the value held by .

The thus obtained xs, ys are χo, y.

Similarly, it is generally an irrational number and is expressed as a decimal in real machines. The value obtained by rounding off this value is used as the input side address of the data to be output. FIGS. 7 and 8 show the correspondence between addresses on the source side and the destination side. A square grid indicates the address grid on the destination side, and the center of the square is an integer address. A parallelogram grid represents the address grid on the source side, and the center of the parallelogram is an integer address.

The rectangle given by sentence 9m in FIG. 7 is the area centered on χo and yo, and A and B are the destination addresses to be output. As shown in Figure 8, sea urchin a is
It is determined as the output of A. Here, the circuits shown in FIG. 5 exist as many as the maximum number of output grids that can fit within the area of uXm, and each circuit operates in parallel. Furthermore, as shown in FIG. 9, the input side has four scanning line buffers, and while data is being input to one buffer, the above processing is performed using data that has already been input to the other three buffers. The encoded data described above is input as scan data, and the input addresses are determined in the order of the data. In this way, input and output addresses are associated, and affine transformation is realized.

As mentioned above, the affine transformation algorithm in this embodiment inputs the raster data on the source side (in this case, there are readings from the file, reading from the league, and reading from the image memory), and inputs the raster data from the destination memory (
In this case, it is stored in the image memory (image memory) through random access. Therefore, since the affine transformation/\-ware is pipelined, it sequentially obtains output for sequential input data, and is executed during the process of data transfer from the file to the image memory, making it possible to perform extremely high-speed conversion. I can do it. Here, the image data refers to the aforementioned compressed data, and the address point refers to the coordinates in the address space of the compressed data.

Once the address of the encoded data after affine transformation is determined, the arrangement of the image data within the block is then exchanged.

The embodiment will be explained below using 2×2 blocks.

Figure 10(a) shows four blocks (A, B) that form the original picture.
, C, D) are shown.

90°, 180' to this block.

When an address is generated by the rotation process described above for each block of 2700, recorded in the destination memory, and played back, the results are as shown in (b), (c), () in the same figure.
d). As is clear from the figure, the original image is not faithfully reproduced, so a method is adopted in which the pixels inside the block are rotated according to the rotation angle. Figures (e) and (f)
, (g) shows pixels in the block at 90°, 180°, 2
This is an example of rotating the image by 70 degrees, which increases the fidelity to the original image. This rotation operation is performed using the code shown in Figure 2(b).

This can be done without changing the pattern code by rewriting the 2-bit rotation code.

Regarding rotation of arbitrary angles, the rotation angle within the block is divided into 90" units. Figure 7 shows rotation angles of 315° to 4.
5°, 45° to 135°.

Divided into four regions: 135° to 225°, 225° to 315°, and rotated within the block by 00°, 90°, 180°, 2
70' is shown.

FIG. 12 shows an embodiment in which the block encoding data format shown in FIG. 2(a) is replaced and reformatted according to the rotation angle within the block. (a) O' (b
)90' (c) 180° (d) 270° is shown.
Ma and σ are not changed by rotation, but the order of subsequent grayscale data is changed. (a) When the data format of 0° is ABCD, (b) 90° is BDACl (
c) 180° is DCBA.

(d) 270° becomes CADB.

FIG. 13 is an example of an intra-block data format conversion circuit. The input signals are X and σ to the buffer 80,
Buffer the remaining 4 grayscale data 81.82.83.8
4 are held separately. Selector 85.86, 87.8
A select signal corresponding to the rotation angle is sent from a controller (not shown) to 9.0 For example, rotation angle within the block Q 0°90'
, 180°, and 270° correspond to 0°1.2.3, respectively, resulting in a 2-bit select signal. Buffer 8
1, 82, 83.84 as A, B, C, D, selector 85° 86.87.88 (7) input terminals x, y,
z, w+,: Connected in different correspondences. When there is one select signal, if Y of the input terminal is output from the output terminal of each selector, the buffer 85
．． B, D, A, and C are output from 86, 87, and 88, respectively.

When this output value is recombined with ma and σ in the buffer 90, a data format as shown in FIG. 12 is completed and is output as an output signal of the buffer 90.

The above are examples of block rotation and intra-block rotation of encoded data. That is, in the present invention, AF with rotation
When FINE conversion is performed, a rotation operation is performed using mXm compressed data as one data, and a rotation operation is performed within the mXm compressed data. This is accompanied by some image quality deterioration, so in order to minimize this, a small matrix (m
□Xm0) performs block encoding or vector quantization.

■ For the color difference signal (1, Q), a large matrix (m
lXml: ml>no) with block encoding, vector quantization, or direct average data.

It is necessary to pay attention to the above two points.

Next, the CRT controller 9 will be explained.

FIG. 14 is a diagram showing the functions of the CRT controller 9.
5 is compressed image memory, 9 is CRT controller, 10 is color CRT, 8 is CPU, 356 is CPU
This is a parameter register set from . In the present invention, memory addresses are treated as two-dimensional (X and Y), but it is also possible to convert these addresses into one-dimensional addresses. The function of the CRT controller shown in FIG. 14 is as follows: χw, ! / W) make a rectangular area T
It is to display and output on a CRT with resolution of O dots and horizontal xo dots. Arbitrary values χo, yo, χW.

In addition to the range, yW can also be constrained to be a multiple of 2 or 4. Figure 15 shows an example of this CRT controller, which took 10 steps.

102, 103, 104 are parameter registers, 105
, 106 is an adder, 107, 108 is a selector, 109
, 110 are address latches or registers. 11
2 is a CRT synchronization circuit, 121 is a horizontal synchronization signal, 122 is a vertical synchronization signal, and 123 is a pixel clock. 111 is a data latch, 128 is a color signal read from the memory, 124 is a color signal to the CRT, 125 is a horizontal address (X), and 126 is a vertical address (Y).

A vertical synchronization signal 122 is generated by a CRT synchronization circuit 112, and a horizontal synchronization signal 121 and a pixel clock 123 are also generated.
is generated. Y Arles Latch 110 by 121
Since the opening price yo102 is selected by 108 while 122 is ON, the address taken in is yO. Further, the address taken into the X address check 109 by 123 becomes χ0 since the opening price χ0101 is selected by 107 while 121 is ON.

In other cases, the X address check 109 is 1 clock (=
1 dot) increases by χw/Xp, the memory address is updated, and the scan in the Then, the X address switch 109 is reset to χO. Further, the Y address launch 110 increases by yw/YD every horizontal opening period, and the memory address is updated.
A scan will be performed in the X direction.

Figure 12 shows a CR that allows rectangular composition on a CRT.
It is a figure showing the function of T controller. Rectangular images 130 and 131 displayed on the CRTIO are images stored as areas 132 and 133 on the memory 5.

Currently, the image 130 is superimposed on the image 131, and the portion of the image 131 where the image 130 is placed is not displayed. This can be obtained by expanding the configuration shown in FIG. FIG. 17 shows an example of its configuration. In FIG. 17, reference numerals 134, 135, 136, and 137 denote intra-area address generation modules, all of which have the same internal configuration. 134 is a horizontal address generation module for the area with the highest priority; 135 is also a vertical address generation module; 13
6 is a horizontal address generation module for the area having the second priority, and 137 is also a vertical address generation module. 148 is a horizontal display address counter, 1
49 is a vertical display address counter and each horizontal display address 150. Outputs vertical display address 151. Next, the address generation module will be explained.

Inside 134, 138 is a register that holds the display start address, 139 is a register that holds the display end display address, 152 and 140 are comparators,
A logic circuit 141 determines whether the signal 150 is included in the register 138 and register 139 area. If it is included in the area, this address generation module has the right to output the memory address. However, this is only when both X and Y are established, and address output by this module 134 and 135 becomes possible when both signals 153 and 154 become true, and the output is enabled by the logic circuit 159. Signal 155 is generated to enable output buffer 147 and output the contents of address register 146 onto memory horizontal address bus 125. Similarly, an address is output from module 135 to memory vertical address bus 126. Modules 134, .
135, i.e. 153 or 1
54 becomes false, the output of the logic circuit 159 also becomes false,
The outputs of modules 134 and 135 are disabled. At this time, if the intra-region signals 156 and 157 of the modules 136 and 137 having the second priority are true, the output of the logic circuit 160 becomes true.

The address outputs of modules 136.137 are output on memory address bus 125.126. logic circuit 160
When the output becomes false, the module with the third priority is tested, and the address output tank is subsequently shifted to modules with lower priorities one after another. Of course, when a module with a higher priority than itself acquires the address output tank, that higher module will output the address. On the other hand, the output address will be explained. In the module 134, a register 143 is a register 142 that holds the read start memory address.
is a register that holds the address increment value.

145 is the address register 146 while 153 is false
A selector 144 is configured such that the output of the register 143 is input to the register 146;
This is an adder that adds the contents of 2. When signal 153 goes true, register 146 is incremented by the contents of register 142 every clock. As described above, rectangular composition on the CRT screen shown in FIG. 16 can be performed with the configuration shown in FIG. 17.

FIG. 18 is a diagram showing the functions of the CRT controller, which enables arbitrary free-form images to be synthesized and output on the CRT. In FIG. 18, 306 is a mask shape memory, and in the case of the example in FIG.
A mask area 162 is defined corresponding to 3, a mask area 161 is defined corresponding to the image area 132, and a mask area 161 is defined corresponding to the image area 132.
A heart-shaped mask is written on it. At this time, as shown on the CRT in FIG. 18, the image area 132 is cut out into a heart shape and displayed superimposed on the image area 133.

The CRT controller 9 performs such processing by pre-reading the mask shape memory 306 before reading out the image memory 5. For example, in this embodiment, a line one line ahead in the vertical address direction is read out to control the mask. When the mask image data to be displayed at the vertical address y in CRTIO in FIG. 18 is a mask that is advanced by yo from the head in area 133 and yl from the head in area 132, the mask area 162 on the mask shape notation tα306 is on the line y. .

+1, the area 161 makes it possible to read each line y1+1 and prepare it for the vertical address y+1 of the next CRTIO. FIG. 19 shows an embodiment of the CRT controller. Figure 19 shows the pair of horizontal and
Compatible with vertical modules. In Figure 19, 1
61.162, 167.168 are registers that hold display addresses, and as in the previous embodiment, the rectangular area on the display specified by these registers is controlled by this module. A 2-line mask data buffer 173 is capable of holding two masks, and is a feature of this embodiment. The mask data read ahead by l vertical 7197 minutes is addressed by the counter 174 and input to the logic circuit 176. logic circuit 17
6 performs true output when addresses Xo and Yo on the display generated by a counter (not shown) are included within the rectangular area to be handled by this module and the mask data is ON. This signal is logic circuit 1
77, and when the signal PRI OR from a module with a higher priority than this module is true, data address buffers 179 and 178 are driven to output memory addresses XDAT and YDAT. The mask data MSKDT continues to be read into the mask data buffer 173 even while the data to be displayed is being transferred. The mask data to be used is read from the mask shape memory 306, but since it is necessary to read it before the display data address, it is output from the mask address register 165.171 that holds an address that is one timing ahead of the data address register 166.172. Ru. At this time, when there are multiple modules, masks may be read from different modules at the same time, but collisions are prevented by giving permission to use the mask address in a time-sharing manner using the ENMSK signal. .

As described above, according to this embodiment, it is possible to display images of arbitrary shapes in a superimposed manner on a display at high speed and with high definition. It is characterized by the fact that it can be processed in no time.

Next, we will discuss the functions and operations of image editing.

Table 1 shows various image editing functions in this device.

FIG. 20 is a schematic flow of editing operations.

Now assume that you want to edit and combine multiple images.

Image input processing 200 means the operation and processing of reading the plurality of images and storing them in a memory for image files. At this time, the aforementioned compressed data is used to reduce the file capacity. Thereafter, in step 204, it is selected whether to perform component processing or layout processing. Parts processing 201
is a process that performs processing such as correction and conversion within one image.
-Items in Table A generally apply. Layout processing 2
02 is a process for determining the layout of a plurality of image data as completed parts, and performs affine transformation for processing images such as rotation, scaling, and movement, and compositing processing. This corresponds to item B in Table 1.

Here, component processing requires direct conversion of image data, but layout processing requires layout parameter information (
For example, it is only necessary to memorize the variable magnification, the position after rotation angle movement, etc.). Therefore, for layout processing, it is sufficient to thin out the image data, display it on the display, and extract the parameters.

Once this processing is completed, the actual image data 203
I do. This combines and edits the completed part data onto the image e-memory under the layout competition parameters. After this processing is completed, the data in the image memory is transferred to the printer and output to the printer 206 is performed.

FIG. 21 shows a detailed explanation of the image input process 200. First, the league reads the manuscript 207, compresses the data using the compressor described above (208), and then registers it as a file on, for example, a hard drive or disk. This operation is repeated as long as there are originals, and ends when there are no more originals to read (210).

FIG. 22 shows the contents of component processing. First, a processing item is selected 211 to determine what to do.

First, color correction 212 saves the image data to a file (File).
Since the image memory also serves as the display's video memory, the data is immediately output to the display. ), perform color correction while looking at the display. This operation does not change the image data in the image memory and outputs it to the display (CRT) (7)
Look up Ta b 1 e (LUT)
(216). The LUT used when the image becomes a desired image is memorized (220).

Contour correction 213 similarly places a spatial filter calculator on the cable that outputs to the CRT, and does not modify the actual image data. Information about the spatial filter (for example, the kernel or coefficients of the well-known Laplacian) is stored (221).

Next, the cutout mask 214 rewrites a 1-bit plane mask memory placed in parallel with the image memory. This is for determining the image area and does not modify the actual image data (21B). Other processing is called actual data correction 215. This rewrites the real image data written on the image memory by directly accessing it from the CPU, and writes, erases, or copies image data to the real image data.

When the above processing is completed, the actual data and mask data are registered as files on the hard disk 222.

FIG. 23 describes layout processing.

First, image data is written from the file to the image memory (223). At this time, as described above, a plurality of image data may be taken into the image memory using thinned data. The plurality of image data are synthesized and scaled (225) by a CRT controller and output on a display. At this time, the rotation of the image is performed using a raster operation (R
OP) can be rewritten (224). On the other hand, variable magnification is CRT
Since the controller can only perform integer scaling, the affine transformer 4 similarly performs arbitrary scaling. Data creation 226 for a mask memory that limits the output image area is then performed. The above operations are performed on each image, and layout parameters are extracted (227).

In FIG. 24, final image data is formed based on the above component data and layout parameters. This process can be completely automated. First, the image component data that is superimposed on the bottom is processed first. The layout parameters and mask data of the first image are pipeline A.
The FFINE conversion register, LUT, mask memory (this is a 1-bit memory placed in parallel with the image memory), etc. are set.

Data from the file is then transferred to the image memory through these pipeline processors. The result is processed by a raster m-operation (ROF).

This processing is equal to the number of parts data (only nmaX)
The image memory is repeatedly overwritten (2
30,231).

Next, we will discuss output to the printer.

The image data resulting from editing is created on the image memory and transferred to the printer side. The state of output from the image memory differs depending on the output method of the printer, for example, whether it is field sequential, line sequential, or dot sequential. Such conversion is performed in converter 12 of FIG. Prior to that, the compressed data is decoded into normal pixel data by a decoder 6.

Usually, one printer 7 is connected. However, by connecting multiple printers, faster output is possible, which is especially important in the publishing and printing fields, which require a large amount of output.

The image data is stored in this image memory by compressing the density data and returning it back to density data, so there may be hue discrepancies that occur when connecting to multiple printers (
This varies depending on the performance of each printer) from one density data to another density data.
The conversion number can be corrected using the kUp Table (LUT).

(This is usually difficult if the image memory is stored in a binarized state.) The converter 12 includes an adjustment mechanism for individual printers using such a LUT.

The color printer 7 outputs an image based on the corrected image data using a normal method such as a dither method.

(V) Effects As described above, the present invention provides image editing using compressed data and a system architecture suitable for high-speed editing.
By taking these steps, it was possible to perform image editing at high speed and with high functionality.

[Brief explanation of drawings]

Figure 1 is an overall block diagram of the color editing processing device on the Kinomi style side, Figure 2 is a diagram showing the data format of encoded data, and Figure 3 is a diagram showing the data format of encoded data.
The figure is a block diagram of the address generation section of the affine transformer, and FIG. 4 is a diagram showing a timing chart of the address generation section.
Figure 5 is a block diagram of the address generation unit, Figure 6 is a timing chart of the address generation unit, Figures 7 and 8 are diagrams showing address correspondence between the original image and the processed image, and Figure 9 is affine transformation. Fig. 10 is a conceptual diagram of block rotation and intra-block rotation, Fig. 11 is a diagram showing intra-block rotation, Fig. 12 is a diagram showing the processing that a code undergoes due to rotation, Fig. 13 The figure is a block diagram of rotation, Figure 14. 16 and 18 are conceptual diagrams of the CRT controller, FIGS. 15, 17, and 19 are block diagrams of the CRT controller, and FIGS. 20, 21, 22, 23, and FIG. 24 is a flowchart showing the editing processing procedure.

Claims (7)

[Claims] (1) In an image editing processing device that is equipped with a device that inputs original image data and an output device that outputs a processed image, and that edits and processes one image from multiple images, the color image data that is handled includes pixel data. An image editing processing device comprising encoded data collected from a plurality of pieces and having a randomly accessible image memory. (2) The image editing processing device according to item 1, wherein the image memory also serves as a video memory for outputting images to a display device. (3) The image editing processing device according to item 1, wherein image editing processing is performed on the encoded data. (4) The image editing processing device according to item 1, further comprising an affine transformation calculation path for storing input raster data in the image memory by random access during image editing processing. (5) In Section 4, the rotation operation in the affine transformation is performed by a combination of performing it for each block of encoded data and performing it inside the block. An image editing processing device characterized by: (6) The image editing processing device according to item 1, wherein the encoded data consists of three color signals: a luminance signal and two color difference signals. (7) The image editing processing device according to item 1, wherein the encoded data has average value data and rotation data of m×m pixels in the code.