JPS62115785A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62115785A JPS62115785A JP60255681A JP25568185A JPS62115785A JP S62115785 A JPS62115785 A JP S62115785A JP 60255681 A JP60255681 A JP 60255681A JP 25568185 A JP25568185 A JP 25568185A JP S62115785 A JPS62115785 A JP S62115785A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- dopant
- type layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 239000002019 doping agent Substances 0.000 claims abstract description 40
- 230000000737 periodic effect Effects 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- 229910052733 gallium Inorganic materials 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 229910052716 thallium Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- 238000005286 illumination Methods 0.000 abstract 2
- 238000009826 distribution Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000254158 Lampyridae Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910017817 a-Ge Inorganic materials 0.000 description 1
- CBGUOGMQLZIXBE-XGQKBEPLSA-N clobetasol propionate Chemical compound C1CC2=CC(=O)C=C[C@]2(C)[C@]2(F)[C@@H]1[C@@H]1C[C@H](C)[C@@](C(=O)CCl)(OC(=O)CC)[C@@]1(C)C[C@@H]2O CBGUOGMQLZIXBE-XGQKBEPLSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 229940112877 olux Drugs 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
非晶質半導体層を含む太陽電池などの半導体装置の材料
として、ａ−９ｔ：ＩＩ、 ａ−８ｉＣ：Ｈ。a-9t:II and a-8iC:H as materials for semiconductor devices such as solar cells containing an amorphous semiconductor layer.
ａ−３ＩＧｅ：ｉｔ、 ａ−８ＩＮ：Ｈ、ａ−３ｌ：Ｐ
：Ｈ，ａ−Ｇｅ：Ｈなどや、これらに微結晶相を含む半
導体が用いられている。a-3IGe:it, a-8IN:H, a-3l:P
:H, a-Ge:H, etc., and semiconductors containing microcrystalline phases in these are used.
従来の太陽電池は、前記材料をｐｉｎあるいはｎ１ｐの
順に同種の非晶質半導体あるいはドープ層のみ広い禁止
帯幅を有する異種の非晶質半導体を順次堆積した構造で
あり、ｐ型層あるいはｎ型層のドーパントの密度は素子
作製時および作製後の熱拡散による分布を除けば、層の
厚さ方向にわたって一様で、通常０．Ｏ１〜５ａｔａ＋
％である。Conventional solar cells have a structure in which amorphous semiconductors of the same type or different types of amorphous semiconductors in which only the doped layer has a wide bandgap are sequentially deposited in the order of pin or n1p, and the p-type layer or n-type The density of the dopant in the layer is uniform throughout the thickness of the layer, except for distribution due to thermal diffusion during and after device fabrication, and is usually 0. O1~5ata+
%.
しかし、この構造の半導体装置は素子内部の内蔵電界が
弱く、光照射時、とくに低照度光照射時の開放電圧Ｖｏ
ｃが充分に大きくないという問題がある。とくに上記半
導体装置を光起電力素子として乾電池の代替電源に用い
るばあい、直列接続の段数を多くとらなければならず、
素子構成上の問題となっている。However, a semiconductor device with this structure has a weak built-in electric field inside the element, and the open circuit voltage Vo when irradiated with light, especially when irradiated with low-intensity light, is
There is a problem that c is not large enough. In particular, when the semiconductor device described above is used as a photovoltaic element as an alternative power source to dry batteries, a large number of series connections must be provided.
This is a problem in terms of element configuration.
本発明はこのような問題を解決するためになされたもの
である。The present invention has been made to solve such problems.
本発明はｐｉｎ型またはｎｉｐ型の非晶質を含む半導体
層と少なくとも２つの電極とを有する半導体装置におい
て、ｐ型層またはｎ型層のドーパントのｍがｐ／Ｉまた
はｎ／ｉ接合界面でもっとも少なく、前記界面からｐ／
組電極たはｎ／電極接合界面に向かって段階的に増加し
ている部分をｐ型層またはｎ型層の少なくとも１つに設
けたことを特徴とする半導体装置に関する。The present invention provides a semiconductor device having a pin-type or nip-type amorphous-containing semiconductor layer and at least two electrodes, in which m of the dopant in the p-type layer or n-type layer is at the p/I or n/i junction interface. The least p/
The present invention relates to a semiconductor device characterized in that at least one of a p-type layer or an n-type layer is provided with a portion that increases stepwise toward a group electrode or an n/electrode junction interface.
本発明に用いるｐｉｎ型またはｎｉｐ型の非晶質を含む
半導体層を構成するｉ型層としては、たとえばａ−８ｔ
：ＩＩ、ａ−９ＩＧｅ：ｌｌ５ａ−Ｇｅ：ＩＩ、 ａ−
３ｉ：Ｆ：Ｉｔ。As the i-type layer constituting the pin-type or nip-type amorphous semiconductor layer used in the present invention, for example, a-8t
:II, a-9IGe:ll5a-Ge:II, a-
3i:F:It.
ａ−８ＩＮ：ＩＩ ５ａ−８ｉＳｎ：ＩＩなどや、それ
らにホウ素やリンを微量ドープしたものなどから形成さ
れた厚さ２５００〜９０００人程度の層、ｐ型層として
は・たとえばａ−３ｊＣ：ＩＩ 、 ｐ ｃ−８ｌ：ｌ
１％ａ−８ｔ：ＩＩなどにｎ型用ドーパントである周期
律表ｍａ族の元素をドープしたものなどから形成された
厚さ８０〜３００人程度の層、ｎ型層としては、たとえ
ばａ−８ｉ：Ｉｆ、 ｐ ｃ−３［：ＩＩ、ａ−８ｉＣ
：ＩＩなどにｎ型用ドーパントである周期律表Ｖａ族の
元素をドープしたものなどから形成された厚さ８０〜３
００人程度の層があげられるが、これらに限定されるも
のではない。A layer with a thickness of about 2,500 to 9,000 layers formed from a-8IN:II, 5a-8iSn:II, etc., or those doped with a small amount of boron or phosphorus.As a p-type layer, for example, a-3jC:II , p c-8l:l
A layer with a thickness of about 80 to 300 layers formed of 1% A-8T:II or the like doped with an element of the Ma group of the periodic table, which is an n-type dopant. 8i:If, p c-3[:II, a-8iC
：II doped with an element of group Va of the periodic table, which is an n-type dopant, and has a thickness of 80 to 3.
An example is a layer of about 00 people, but it is not limited to this.
前記ｐ型層のうちでは、ａ−３ＩＣ：ＩＩ 、ａ−８ｉ
：Ｉｆにｍａ族の元素をドープした層が、活性化エネル
ギーが小さい、光吸収ロスが少ないなどの点から好まし
く、また前記ｎ型層のうちでは、ａ−８ｉＣ：Ｉｔ ％
、ｃｚｃ−］：］ＩｆＸａ−３ｔ：ＩにＶａ族の元素
をドープした層が、活性化エネルギーが小さい、導電率
が高いなどの点から好ましい。Among the p-type layers, a-3IC:II, a-8i
:If doped with a Ma group element is preferable from the viewpoints of low activation energy and low light absorption loss, and among the n-type layers, a-8iC:It%
, czc-]:]IfXa-3t:I is preferably doped with a Va group element in terms of low activation energy and high conductivity.
前記説明ににおいては、ｎ型用ドーパントとして周期律
表ｍａ族の元素、すなわちＢ、Ｖ。In the above description, elements of the Ma group of the periodic table, ie, B and V, are used as n-type dopants.
Ｇａｓ Ｉｎｑ ＴＬ ｎ型用ドーパントとして周期律
表のＶａ族の元素、すなわちＮ１Ｐ １ＡＳ％ Ｓｂ、
Ｔｅ。Gas Inq TL As a dopant for n-type, an element of the Va group of the periodic table, that is, N1P 1AS% Sb,
Te.
Ｐａをあげたが、ドーピングすることにより半導体をｐ
型あるいはｎ型の導電タイプを示すものにするものであ
れば、これらに限定されるものでない。Although the Pa is raised, the semiconductor can be made p by doping.
It is not limited to these as long as it exhibits conductivity type of type or n type.
本明細書にいう非晶質を含む半導体層とは、非晶質半導
体、非晶質半導体に微結晶状半導体が微結晶粒状に分布
するもの、大きな結晶粒の結晶半導体の間を非晶質半導
体がうめるように分布するものなどがら形成された層状
の半導体のことである。The semiconductor layer containing amorphous as used herein refers to an amorphous semiconductor, an amorphous semiconductor in which microcrystalline semiconductor is distributed in the form of microcrystalline grains, and a semiconductor layer containing an amorphous semiconductor between large crystal grains. It is a layered semiconductor that is formed by distributing the semiconductor in such a way that it fills the layer.
本発明におけるｐｉｎ型またはｎＩｐ型半導体層におい
ては、ｐ型層またはｎ型層のドーパントの量かｐ／ｉま
たはｎ／Ｉ接合界面で最も少なく、該界面からｐ／組電
極たはｎ／電極接合界面に向って段階的に増加している
部分がｐ！！層またはｎ型層の少なくとも１つに設けら
れている。In the pin-type or nIp-type semiconductor layer of the present invention, the amount of dopant in the p-type layer or n-type layer is the smallest at the p/i or n/I junction interface, and from the interface the p/set electrode or the n/electrode. The part that gradually increases toward the bonding interface is p! ! or n-type layer.
第１図は本発明の半導体装置の一実施態様を示す説明図
であり、透明電極（２）を白゛するガラス基板（１）上
に、ｐ／Ｉ接合界面でのドーパントの量が最も少なくな
るようにｎ型半導体層（３）が設けられ、その上にｉ型
半導体層（４）、ついでｎ型半導体層（５）が設けられ
、さらに裏面電極（６）が設けられていることを示す図
である。FIG. 1 is an explanatory diagram showing one embodiment of the semiconductor device of the present invention, in which a transparent electrode (2) is formed on a glass substrate (1) with the least amount of dopant at the p/I junction interface. An n-type semiconductor layer (3) is provided on top of it, an i-type semiconductor layer (4), an n-type semiconductor layer (5), and a back electrode (6). FIG.
第１図の半導体装置では、ｐ／ｉ接合界面でのドーパン
トの量が最も少なくなるようにされているが、ｎ型半導
体層中のドーパントがｎ型半導体層（８）全体に均一に
なるように含まれていて、ｎ！８！半導体層がｎ／ｌ接
合界面でのドーパントの量が最も少なくなるように形成
されていてもよく、ｎ型半導体層およびｎ型半導体層の
両方のドーパントがそれぞれｐ／ｉ 、 ｎ／ｌ接合界
面で最低になるようにされていてもよい。また、第１図
においてはｐ型層側から光（刀が入るようになっている
が、光がｎ型層側から入ってもよい。In the semiconductor device shown in FIG. 1, the amount of dopant is minimized at the p/i junction interface, but the amount of dopant in the n-type semiconductor layer is made uniform throughout the n-type semiconductor layer (8). Contained in n! 8! The semiconductor layer may be formed such that the amount of dopant is minimized at the n/l junction interface, and the dopants in both the n-type semiconductor layer and the n-type semiconductor layer are at the p/i and n/l junction interfaces, respectively. may be set to the lowest value. Furthermore, in FIG. 1, the light (sword) enters from the p-type layer side, but the light may enter from the n-type layer side.
さらにはｐｉｎ層は、１層である必要もなく、２〜５層
かさねて設けてもよい。この際、２層目以上の層も上記
のようにｉ層との接合界面のドーパント量を最も少なく
するようにしてもよく、第２図のような通常のｐｉｎ層
を設けてもよい。Furthermore, the pin layer does not need to be one layer, and may be provided in two to five layers. At this time, the second and higher layers may also have the lowest amount of dopant at the bonding interface with the i-layer as described above, or may be provided with a normal pin layer as shown in FIG.
なお第２図の（８）は通常のｐ型層である。Note that (8) in FIG. 2 is a normal p-type layer.
ｐ型層あるいはｎ型層のドーパントの量としては、通常
０．Ｏ１〜５ ａｔｍ％程度であるが、ドーパントの量
が最も少ないｐ／ｌ接合界面あるいはｎｉｌ接合界面付
近、好ましくは該界面から少なくとも２０〜３０人、さ
らに好ましくは少なくとも １００人までの部分のドー
パントの量は０．０１ａｔ−％以下が好ましく、０．０
０１ａｔｍ％以下がさらに好ましい。これらのことは本
発明者らによる半導体装置試作の結果から明らかにされ
ている。The amount of dopant in the p-type layer or n-type layer is usually 0. The amount of dopant is about 1 to 5 atm%, but the amount of dopant is near the p/l junction interface or nil junction interface where the amount of dopant is the smallest, preferably at least 20 to 30 atoms from the interface, more preferably at least 100 atoms. The amount is preferably 0.01 at-% or less, and 0.0
More preferably, it is 0.01 atm% or less. These matters have been made clear from the results of semiconductor device prototype production by the present inventors.
ドーパントの分布はｐｌｉ接合界而あ面いは口／Ｉ接合
界面からｐ／電極あるいはｎ／電極接合界面に向って段
階的に増加している必要があり、このような構成にする
ことにより、ｉ層へのドーパントの侵入が少なくなる、
ｉＪＩとドーパント層の間の界面が改善されるなどの理
由により、結果的に開放電圧が増加するという効果かえ
られる。The distribution of the dopant must increase stepwise from the pli junction or the mouth/I junction interface to the p/electrode or n/electrode junction interface, and by adopting such a configuration, Intrusion of dopants into the i-layer is reduced.
Due to the improvement of the interface between the iJI and the dopant layer, the effect of increasing the open circuit voltage can be obtained.
本明細書にいう段階的に増加しているとは、通常のドー
ピング層から熱拡散によって生ずるしみだしにより自然
に生ずる増加ではなく、ドーパントの量を調整すること
によりえられる連続的な増加や階段状の増加などを意味
する。The term "stepwise increase" as used herein refers to a continuous increase or step-like increase obtained by adjusting the amount of dopant, rather than an increase that naturally occurs due to seepage caused by thermal diffusion from a normal doped layer. It means an increase in the number of people.
第３図はｐ６層がａ−８ＩＣ：ＩＩ Ｓｉ型層がａ−３
ｔ：ＩＩ。In Figure 3, the p6 layer is a-8IC:II and the Si type layer is a-3.
t: II.
ｎ型層がａ−９［：Ｉｆである本発明の半導体装置のド
ーパントの分布の一実施態様に関する説明図である。第
３図において、（９）はｎ型半導体層中のｐ！！ドーパ
ントの分布を示すグラフ、（１０）はｎ型半導体層中の
ｎ型ドーパントの分布を示すグラフ、０１）、（１２１
は従来の半導体装置のｐ型ドーパント、ｎ型ドーパント
の分布を示すグラフである。FIG. 4 is an explanatory diagram regarding one embodiment of the dopant distribution of the semiconductor device of the present invention in which the n-type layer is a-9[:If. In FIG. 3, (9) represents p! in the n-type semiconductor layer. ! Graph showing the distribution of dopants, (10) is a graph showing the distribution of n-type dopants in the n-type semiconductor layer, 01), (121)
is a graph showing the distribution of p-type dopants and n-type dopants in a conventional semiconductor device.
ドーパントの分布は、第３図に示すようにｐ型層内また
はｎ型層内に分布すればよいが、かならずしも図の形に
限定されるものではない。The dopant may be distributed within the p-type layer or the n-type layer as shown in FIG. 3, but is not necessarily limited to the shape shown in the figure.
要するにｐ型層またはｎ型層中のドーパントの分布がｐ
／ｌまたはｎ／ｌ接合界面で最も少なくなるようにすれ
ばよい。In short, the dopant distribution in the p-type layer or n-type layer is p
It is sufficient that the amount is minimized at the /l or n/l junction interface.
ａ−８ｊＣ：ＩＩをドープ層として用いて本発明の半導
体装置を製造しようとすると、ドープなしのａ−８ｉＣ
：ＩＩの絶縁層がｐ／ｉまたはｎ／ｌ接合界面に存在す
ることになるが、このような構造でもよい。When attempting to manufacture the semiconductor device of the present invention using a-8jC:II as a doped layer, undoped a-8iC
:II insulating layer is present at the p/i or n/l junction interface, but such a structure may be used.
本発明に用いる電極にはとくに制限はなく、通常太陽電
池の作製に用いられるような透明電極、金属電極、シリ
サイド電極あるいはこれらの材料を多層構造にした電極
のごとき電極であれば用いうる。There are no particular limitations on the electrodes used in the present invention, and any electrodes such as transparent electrodes, metal electrodes, silicide electrodes, or electrodes with a multilayer structure of these materials that are normally used in the production of solar cells can be used.
本発明における半導体を作製する装置としては、平行平
板容量結合型プラズマＣＶＤ装置、誘導結合型プラズマ
ＣＶＤ装置、熱ＣＶＤ装置、ＥＣＲプラズマＣＶＤ装置
、光ＣＶＤ装置、励起種Ｃ’ＶＤ装置などがあげられる
が、これらに限定されるものではない。またその製造方
法、原料などにもとくに限定はない。Examples of the apparatus for manufacturing a semiconductor in the present invention include a parallel plate capacitively coupled plasma CVD apparatus, an inductively coupled plasma CVD apparatus, a thermal CVD apparatus, an ECR plasma CVD apparatus, an optical CVD apparatus, an excited species C'VD apparatus, etc. However, it is not limited to these. Furthermore, there are no particular limitations on the manufacturing method, raw materials, etc.
本発明におけるｐｉｎ構造や、ｎｉｐ構造は非晶質半導
体系の光起電力素子やフォトダイオードなどで一般的に
用いられている構造である。The pin structure and nip structure in the present invention are structures commonly used in amorphous semiconductor photovoltaic elements, photodiodes, and the like.
以下、本発明の半導体装置を実施例に基づき説明する。EMBODIMENT OF THE INVENTION Hereinafter, the semiconductor device of this invention is demonstrated based on an Example.
実施例１および比較例１ 第１図に示す構造の太陽電池を試作した。Example 1 and Comparative Example 1 A solar cell with the structure shown in Figure 1 was prototyped.
基板としてはガラス上に透明電極としてＳＬ ０２をス
パッタ法にて８００人の厚さに蒸着したものを用いた。The substrate used was glass on which SL 02 was deposited as a transparent electrode to a thickness of 800 mm by sputtering.
この基板上にプラズマＣＶＤ法によりｐ型層−ＳＬＣ：
Ｈ膜を１５０人堆積させた。ｐ型層−ＳＬＣ：ＩＩの原
料ガスとして５ＬＨ４、ＣＨ４、Ｂ２）Ｉｓ （Ｈ２
で１０００ｐｐｆｉｌに希釈したもの）を用い、３つの
ガスの流量をそれぞれ１Ｏｓｅｃ＋ｍｓ ３０ｓｅｃｍ
、２００ｓｃｃａ＋として一定のまま７０人堆積し、グ
ロー放電を維持したまま、Ｂ２）１ａの量のみを徐々に
減少させて、残りの８０人を堆積するようにし、ｐ層堆
積完了の時点では１３２Ｈｓの流量が０ｓｃｃａ＋にな
るようにした。A p-type layer-SLC is formed on this substrate by plasma CVD method:
150 people deposited H films. 5LH4, CH4, B2) Is (H2
diluted to 1000 ppfil), and the flow rates of the three gases were set to 1Osec+ms and 30sec, respectively.
, 70 layers were deposited at a constant value of 200scca+, and while maintaining the glow discharge, only the amount of B2) 1a was gradually decreased to deposit the remaining 80 layers, and at the time of completion of p layer deposition, 132Hs. The flow rate was set to 0scca+.
続いて５Ｌ）１４をグロー放電分解してｉ型層−ＳＬ：
Ｈ層を約７０００人、さらにＳＬ ８４２０ｓｅｃｍ、
Ｈ２でＨ０００ｐｐに希釈したＰＩ＋３１０１００５ｅ
の混合ガスをグロー放電分解して３００人堆積させたの
ち、裏面の金属電極としてＮを１０００人真空蒸着法に
て蒸着し、１ ｃＪの素子を作製した。Subsequently, 5L) 14 was decomposed by glow discharge to i-type layer-SL:
Approximately 7000 people in the H layer, and SL 8420sec,
PI+3101005e diluted to H000pp with H2
The mixed gas was decomposed by glow discharge to deposit 300 layers, and then N was deposited as a metal electrode on the back surface by a 1000 layer vacuum evaporation method to fabricate a 1 cJ element.
Ｂ２Ｈｓを一定量流したときのｐ型層のドーパント量は
２ａｔａ＋％であった。When a constant amount of B2Hs was flowed, the amount of dopant in the p-type layer was 2ata+%.
ｐ型層−ＳＬＣ：Ｈを上記一定流量にて１５０人堆積し
た他は、上記と同様にして比較のために従来と同じ型の
太陽電池を作製した。For comparison, a solar cell of the same type as the conventional one was fabricated in the same manner as described above, except that 150 p-type layers -SLC:H were deposited at the above-mentioned constant flow rate.
えられた２種の太陽電池の螢−光灯２０Ｏｌｕｘ下での
Ｖ−１特性を／ｌ−１定した結果を第４図に示す。FIG. 4 shows the results of determining the V-1 characteristics of the two types of solar cells obtained under a firefly light lamp of 20 Olux at /l-1.
比較例１の太陽電池の開放電圧が０．６ｖ程度であるの
に対し、実施例１の太陽電池の開放電圧は０．７０Ｖで
あった。また電流、ＰＩ’にも若干の向上が見られた。The open-circuit voltage of the solar cell of Comparative Example 1 was about 0.6V, whereas the open-circuit voltage of the solar cell of Example 1 was 0.70V. A slight improvement was also observed in the current and PI'.
本発明の半導体装置は従来の半導体装置に比較して、光
照射下、とくに低照度完工において高い開放電圧を示す
。Compared to conventional semiconductor devices, the semiconductor device of the present invention exhibits a higher open circuit voltage under light irradiation, particularly when completed at low illuminance.
第１図は本発明の半導体装置の一実施態様に関する説明
図、第２図は従来の半導体装置の一実施態様に関する説
明図、第３図は本発明に用いるｐｉｎ型半導体層中にお
けるドーパントの分布の一例と、従来のｐｉｎ型半導体
層中におけるドーパントの分布の一例とに関する説明図
、第４図は実施例１および比較例１でえられた太陽電池
のＶ−Ｉ特性を示すグラフである。
（図面の主要符号）
（２）：透明電極
（３Ｊ＝ｐ型層
（４）：ｉ型層
（５） ： ｎ型層
（６）：裏面電極FIG. 1 is an explanatory diagram of one embodiment of the semiconductor device of the present invention, FIG. 2 is an explanatory diagram of one embodiment of the conventional semiconductor device, and FIG. 3 is the distribution of dopants in the pin type semiconductor layer used in the present invention. FIG. 4 is a graph showing the VI characteristics of the solar cells obtained in Example 1 and Comparative Example 1. (Main symbols in the drawing) (2): Transparent electrode (3J = p-type layer (4): i-type layer (5): n-type layer (6): back electrode
Claims (1)
少なくとも２つの電極とを有する半導体装置において、
ｐ型層またはｎ型層のドーパントの量がｐ／ｉまたはｎ
／ｉ接合界面でもっとも少なく、その界面からｐ／電極
またはｎ／電極接合界面に向かって段階的に増加してい
る部分をｐ型層またはｎ型層の少なくとも１つに設けた
ことを特徴とする半導体装置。 ２ 前記ｐ型層またはｎ型層がａ−ＳｉＣ：Ｈ層である
特許請求の範囲第１項記載の半導体装置。 ３ 前記ｐ型層またはｎ型層がａ−Ｓｉ：Ｈ層である特
許請求の範囲第１項記載の半導体装置。 ４ 前記ｐ型層またはｎ型層のｐ／ｉまたはｎ／ｉ接合
界面から少なくとも２０Åまでの厚さの部分において、
前記界面からｐ／電極またはｎ／電極接合界面に向けて
ドーパントの量が段階的に増加している特許請求の範囲
第１項記載の半導体装置。 ５ 前記ｐ型層またはｎ型層のｐ／ｉまたはｎ／ｉ接合
界面から少なくとも １００Åまでの厚さの部分におい
て、前記界面からｐ／電極またはｎ／電極接合界面に向
けてドーパントの量が段階的に増加している特許請求の
範囲第１項記載の半導体装置。 ６ 前記ｐ型層のドーパントが周期律表IIIａ族に属す
る元素（Ｂ、Ａｌ、Ｇａ、Ｉｎ、Ｔｌ）である特許請求
の範囲第１項、第４項または第５項記載の半導体装置。 ７ 前記ｎ型層のドーパントが周期律表Ｖａ族に属する
元素（Ｎ、Ｐ、Ａｓ、Ｓｂ、Ｔｅ、Ｐｏ）である特許請
求の範囲第１項、第４項または第５項記載の半導体装置
。[Claims] 1. A semiconductor device having a pin-type or nip-type amorphous semiconductor layer and at least two electrodes,
The amount of dopant in the p-type layer or n-type layer is p/i or n
A feature is that at least one of the p-type layer or the n-type layer is provided with a portion that is smallest at the /i junction interface and increases stepwise from that interface toward the p/electrode or n/electrode junction interface. semiconductor devices. 2. The semiconductor device according to claim 1, wherein the p-type layer or the n-type layer is an a-SiC:H layer. 3. The semiconductor device according to claim 1, wherein the p-type layer or the n-type layer is an a-Si:H layer. 4. In a portion of the p-type layer or n-type layer having a thickness of at least 20 Å from the p/i or n/i junction interface,
2. The semiconductor device according to claim 1, wherein the amount of dopant increases stepwise from the interface toward the p/electrode or n/electrode junction interface. 5. In a portion of the p-type layer or n-type layer up to a thickness of at least 100 Å from the p/i or n/i junction interface, the amount of dopant is graduated from the interface to the p/electrode or n/electrode junction interface. A semiconductor device according to claim 1, which is increasing in number. 6. The semiconductor device according to claim 1, 4, or 5, wherein the dopant of the p-type layer is an element (B, Al, Ga, In, Tl) belonging to group IIIa of the periodic table. 7. The semiconductor device according to claim 1, 4, or 5, wherein the dopant of the n-type layer is an element (N, P, As, Sb, Te, Po) belonging to group Va of the periodic table. .
Priority Applications (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255681A JP2545066B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor device |
| CA000521602A CA1321660C (en) | 1985-11-05 | 1986-10-28 | Amorphous-containing semiconductor device with high resistivity interlayer or with highly doped interlayer |
| AU64619/86A AU600453B2 (en) | 1985-11-05 | 1986-10-31 | Semiconductor device |
| EP86115170A EP0221523B1 (en) | 1985-11-05 | 1986-11-01 | Semiconductor device |
| DE3650712T DE3650712T2 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| DE3650012T DE3650012T2 (en) | 1985-11-05 | 1986-11-01 | Semiconductor device. |
| EP92104628A EP0494088B1 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| EP19920104633 EP0494090A3 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| KR860009364A KR870005477A (en) | 1985-11-05 | 1986-11-05 | Semiconductor devices |
| CN86106353A CN1036817C (en) | 1985-11-05 | 1986-11-05 | Semiconductor device |
| US07/477,138 US5032884A (en) | 1985-11-05 | 1990-02-07 | Semiconductor pin device with interlayer or dopant gradient |
| AU65966/90A AU636677B2 (en) | 1985-11-05 | 1990-11-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255681A JP2545066B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62115785A true JPS62115785A (en) | 1987-05-27 |
| JP2545066B2 JP2545066B2 (en) | 1996-10-16 |
Family
ID=17282146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60255681A Expired - Lifetime JP2545066B2 (en) | 1985-11-05 | 1985-11-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2545066B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012134541A (en) * | 2009-02-17 | 2012-07-12 | Korea Inst Of Industrial Technology | Solar cell manufacturing method making use of inductive coupling plasma chemical vapor deposition method |
| JP2013125891A (en) * | 2011-12-15 | 2013-06-24 | Sharp Corp | Photoelectric conversion element and manufacturing method of the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56150876A (en) * | 1980-04-24 | 1981-11-21 | Sanyo Electric Co Ltd | Photovoltaic device |
| JPS5914679A (en) * | 1982-07-16 | 1984-01-25 | Toshiba Corp | Photovoltaic device |
| JPS5996775A (en) * | 1982-11-25 | 1984-06-04 | Agency Of Ind Science & Technol | Amorphous silicon photoelectric conversion device |
| JPS6050973A (en) * | 1983-08-31 | 1985-03-22 | Agency Of Ind Science & Technol | Semiconductor device |
-
1985
- 1985-11-14 JP JP60255681A patent/JP2545066B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56150876A (en) * | 1980-04-24 | 1981-11-21 | Sanyo Electric Co Ltd | Photovoltaic device |
| JPS5914679A (en) * | 1982-07-16 | 1984-01-25 | Toshiba Corp | Photovoltaic device |
| JPS5996775A (en) * | 1982-11-25 | 1984-06-04 | Agency Of Ind Science & Technol | Amorphous silicon photoelectric conversion device |
| JPS6050973A (en) * | 1983-08-31 | 1985-03-22 | Agency Of Ind Science & Technol | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012134541A (en) * | 2009-02-17 | 2012-07-12 | Korea Inst Of Industrial Technology | Solar cell manufacturing method making use of inductive coupling plasma chemical vapor deposition method |
| JP2013125891A (en) * | 2011-12-15 | 2013-06-24 | Sharp Corp | Photoelectric conversion element and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2545066B2 (en) | 1996-10-16 |
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