JPS6197963A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stably sustain the charge representing any data by a method wherein resistance elements are deposited on gate electrodes of MISFET comprising flip-flop circuit of memory cell. CONSTITUTION:A resistance element 14B comprising resistance elements R1, R2 deposited on conductive layers 7C or 7D are extendedly provided in the almost similar row direction through the intermediary of insulating films i.e. constituting a MIS type structure utilizing the conductive layers 7C or 7D as a gate electrode likewise the insulating films 12 as insulators and the resistance element 14B as a semiconductor. Through these procedures, any resistance elements 14B (R1, R2) may change resistance values in terms of data (voltage) written in memory cell to supply current in the direction discriminating the voltage difference in '1' and '0' to stably sustain the charge representing the data.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device equipped with a static random access memory [hereinafter referred to as technology effective when applied to SRA]. It is something.

[Background Art] In order to reduce the area occupied, memory cells of SRAMs tend to be constructed of resistive elements formed of polycrystalline silicon films instead of load MISFETs.

This resistor element is formed by using a mask for impurity introduction into the same polycrystalline silicon film as the power supply voltage wiring to which a high potential is applied, without introducing impurities to reduce the resistance value, and then performing predetermined patterning. do.

Therefore, variations in the resistance value of the resistance element of the memory cell are likely to occur due to variations in the impurity introduction mask, impurity diffusion state, patterning, and other processing.

As a result of studies on this technology, the inventor of the present invention has found that the electrical reliability of SRAM cannot be improved due to the following reasons. In other words, since the current value supplied from the resistor element differs from the information (voltage) written in the memory cell, it is not possible to stably hold information, and the operating margin in the information read operation becomes small. It is from.

Note that as a technique for controlling the resistance value of a resistance element constituting a memory cell of an SRAM, for example, Japanese Patent Laid-Open No. 54-563
There is a publication No. 57.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the electrical reliability of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technology capable of stably retaining information written in memory cells in an SRAM and improving its electrical reliability.

Another object of the present invention is to provide a technology capable of improving the controllability of the resistance values of conductive layers and resistive elements used in semiconductor integrated circuit devices, and improving the electrical reliability thereof. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

In other words, the SR has a memory cell that constitutes a flip-flop circuit with two resistance elements and two MISFETs.
In AM, the gate electrode of the MISFET and the resistor element are overlapped.

This allows the information (voltage) written to the memory cell to
, the resistance value of the resistance element is changed to 1′″,′″0
Current can be supplied in the direction that makes the voltage difference clear (self-bias), so information can be stably retained. As a result, the operating margin for information read operations can be increased. Therefore, the electrical reliability of the SRAM can be improved.

Hereinafter, the configuration of the present invention will be explained using an SRAM in which a memory cell flip-flop circuit is configured with two resistance elements and two MrSFETs.

[Embodiment FIG. 1 shows an SRAM for explaining one embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a memory cell of FIG.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 1, word lines WL extend in one row direction, and a plurality of word lines are provided in the column direction (hereinafter, the direction in which the word lines extend will be referred to as the row direction).

The word line WL is for controlling a switch MISFET which will be described later.

DL and DL are data lines extending in one column direction, and a plurality of data lines are provided in the row direction (hereinafter, the direction in which the data lines extend will be referred to as the column direction). The data lines DL, DL are for transmitting charges serving as information between a memory cell and a write circuit or a read circuit, which will be described later.

Ql and Q2 are MISFETs, one end of which is connected to power supply voltage wiring Vcc (for example, 5.0
[V]), the other (DMr 5FETQ2).

Q, is connected to the gate electrode and switch MISFET, and the other end is connected to the reference voltage distribution fiVss (for example,
0 [V]).

R1 and R2 are resistance elements. These resistance elements R1, R2
controls the amount of current flowing from the power supply voltage wiring Vcc,
This is to stably hold the written information.

Resistance elements R1 and R2 are designed to be self-biased, as will be described later.

A flip-flop circuit with a pair of input and output terminals is
Two MISFETQI, Q2 and resistance element R! , R2. This flip-flop circuit is for storing information '1'', -II OII transmitted from the data lines DL, DL.

QSl and QSl are switch MISFETs, one end of which is connected to the data lines DL and DL, and the other end connected to a pair of input/output terminals of the flip-flop circuit. The switching M I S FETs Qs□ and QS2 are controlled by the word line WL and serve as a switch between the flip-flop circuit and the data lines DL and DL.

C is an information storage capacitor (parasitic capacitance), which mainly connects the gate electrode of one MI 5FETQ+, Q2 and the semiconductor region of one of MI 5FETQ2, Q+ (
source region or drain region). This information storage capacitor C is for storing charge that becomes information of the memory cell.

An SRAM memory cell consists of a flip-flop circuit having a pair of input/output terminals and a switch MISFET Qsr.
, Q82 are configured with a switch MISFET. A plurality of memory cells are arranged at predetermined intersections between the word line WL and the data aDL, DL, forming a memory cell array.

Next, a specific configuration of this embodiment will be explained.

FIG. 2 shows an SRAM for explaining one embodiment of the present invention.
Figure 3 is a plan view of the main part showing the memory cell in Figure 2.
It is a sectional view taken along the -■ cutting line.

Note that the plan views shown in FIG. 2 and FIGS. 4 to 6 described later are one insulating film other than the field insulating film provided between each conductive layer to make it easier to understand the structure of this embodiment. do not.

In FIGS. 2 and 3, reference numeral 1 denotes an n-type semiconductor substrate made of single crystal silicon. This semiconductor substrate 1 is made of S
This is for configuring RAM.

Reference numeral 2 denotes a p-type well region, which is provided on a predetermined main surface portion of the semiconductor substrate 1. This well region 2 is for configuring a complementary MISFET.

A field insulating film 3 is provided on the main surface of the semiconductor substrate 1 and the well region 2 between the semiconductor element forming regions. This field insulating film 3.

This is for electrically isolating semiconductor elements.

M I S FETQ+, Q2 that constitutes the memory cell
The switch MISFETs Qs+ and QS2 are surrounded and defined by a field insulating film 3. The MISFET Q 2 and the MISFET QS 2 for Suinochi are integrally defined by a field insulating film 3 in order to perform cross-coupling. MISFET Q1 and MISFETQs+ for switch are the MISFETQs+ mentioned above.
E T Q 2 and M I S F E T for switch
It is separated and defined by a field insulating film 3 at a position intersecting with Q s 2. MISF
E T Q s and MI S F E T for switch
Q s r is cross-coupled by a conductive layer provided on the field insulating film 3 .

A p-type channel stopper region 4 is provided on the main surface of the well region 2 under the field insulating film 3.

This channel stopper region 4 is for preventing a parasitic MISFET and further electrically isolating semiconductor elements.

Reference numeral 5 denotes an insulating film, which is provided above the main surfaces of the semiconductor substrate 1 and the well region 2, which serve as semiconductor element formation regions. This '#@ edge film 5 is mainly used to constitute a gate insulating film of the MISFET.

Reference numeral 6 denotes a connection hole, which is provided by removing a predetermined portion of the insulating film 5. This connection hole 6 is connected to a semiconductor element (semiconductor region).
and wiring (a conductive layer used as a mask for introducing impurities to form a semiconductor region).

Conductive layers 7A to 7D are provided extending over a predetermined upper portion of the field insulating film 3 or the insulating film 5.

The conductive layer 7A is a switch M I S F E T Q
s r and Q S are provided above the insulating film 5 in the 2 forming region, and are provided extending above the field insulating film 3 in the row direction. This conductive layer 7A is a switch MISFET.
QS1. The QS2 forming region constitutes a gate electrode, and the other portion constitutes a word line WL.

The conductive layer 7B is provided so as to be electrically connected to one semiconductor region of the MISFETQs, Q2 constituting the flip-flop circuit through the connection hole 6, and similarly to the conductive layer 7A, it is connected to the field insulating film 3. The upper part extends in the row direction. The conductive conductor M 7 B is for configuring a reference voltage wiring Vss connected to one semiconductor region of each of a plurality of memory cells arranged in the row direction.

The electrocardiogram layer 7A and the conductive layer 7B are made of the same conductive material and are provided on the same conductive layer, and are made of the same conductive material so that they do not intersect.
They are spaced apart from each other and are provided substantially parallel to each other.

The conductive layer 7C has one end electrically connected to the semiconductor region of the switch MISFET Qs through the connection hole 6, and the other end connected to the field insulating film 3 and one MISFET Qs. Extends the upper part of the insulating film 5 in the E T Q 2 formation region and connects the other MISFET Q□ through the connection hole 6.
It is provided so as to be electrically connected to the semiconductor region of. This conductive layer 7C has M T S F on the upper part of the insulating film 5
constitutes a gate electrode of E T Q 2, and.

This is for cross-coupling the MI SFE T Q s 1 for switch and the other MI SFE T Q +.

The conductive layer 7D has one end electrically connected to the semiconductor region of the switch MISFET QS 2 through the contact hole 6, and the other end connected to the field insulating film 3 and the other MISFET QS 2. Insulating film 5 in E T Q + formation region
It is provided so as to extend from the top. This conductive layer 7D
is for configuring the gate electrode of M I S F E T Q + above the insulating film 5. M for switch
I S F E T Q S 2 and M I S F E
As described above, T Q 2 is an integrated semiconductor region, so there is no need for cross-coupling with this conductive layer.

In addition, M I S F E T Q S 2 for the switch
and MISFE TQ 2 means MIS for switch.
F E T Q s I and M I S F E T
Similar to the cross-coupling of QI, the conductive layer 7D may be formed into a predetermined shape for cross-coupling.

The conductive layers 7A to 7D are made of polycide (MoSi, Ti5i2゜TaSi2. WSi2
/polysi). The conductive layers 7A to 7D are conductive materials.

Silicide (MoSi2.TiSi2.Ta5iz,
WSi2), high melting point metals (Mo, Ti, Ta, W), etc. may be used.

The conductors R7A to 7D are made of a conductive material such as polycide, silicide, high melting point metal, etc., so that the resistance of several [Ω/
The resistance value can be set to approximately 1000 yen. by this,
The resistance value of the conductive layer 7B (reference voltage wiring Vss) is reduced by about one order of magnitude compared to a case where it is formed of a semiconductor region, and in particular, the area occupied in the row direction of the memory cell array can be significantly reduced. Furthermore, it is necessary to run aluminum wiring between predetermined memory cells and connect it to the conductive layer 7B to suppress fluctuations in its potential. However, the conductive layer 7B has a low resistance value, and the aluminum wiring Since the number can be reduced, the degree of integration in the column direction in the memory cell array can be particularly improved.

Furthermore, since the conductive layer 7B has a low resistance value, it is possible to suppress fluctuations in its potential caused by current flowing through the memory cell. This makes it possible to increase the margin in information writing and reading operations, thereby making it possible to prevent malfunctions.

Further, by extending the conductive layer 7C having a low resistance value and cross-coupling the flip-flop circuit, a conductive layer for cross-coupling may be provided between the conductive layer 7C and the conductive layer 7D, either the same conductive layer or a different conductive layer. Since there is no need to provide a conductive layer, the distance between them (the pitch between the gate electrodes of MISFETQs and Q2 can be reduced). As a result, the area occupied by the flip-flop circuit, that is, the memory cell, can be reduced, and the degree of integration in the column direction of the memory cell array can be particularly improved.

The conductive layers 7A to 7D are formed by a first conductive layer forming step in the manufacturing process.

8 is an n-type semiconductor region, MI 5F for switch
ETQst, QS2, MI 5FETQI, provided on both sides of the conductive layers 7A and 7C17D, which are the Q2 formation regions, and on the main surface of the well region 2 (between the source region or drain region and the region where the channel is formed). . This semiconductor region 8 is an LDD (LDD)
ddanrain) This is for constructing fFJ structure.

This semiconductor region 8 has a lower impurity concentration than a semiconductor region that becomes a substantial source region or drain region, which will be described later. As a result, the electric field strength at the pn junction between the semiconductor region 8 and the well region can be relaxed.
TSFET pn junction breakdown voltage (source or drain breakdown voltage)
can be improved.

In addition, since the semiconductor region 8 is formed with a shallow junction depth xj), the lower part of the gate electrode (the region where the channel is formed)
It is possible to reduce the amount of wraparound. Thereby, short channel effects can be suppressed.

The semiconductor region 8 is mainly formed by ion implantation using the conductive layers 7A and 7C17D as a mask for impurity introduction, and is self-aligned with the conductive layers M7A and 7C17D.

Reference numeral 9 denotes a mask for impurity introduction, which is provided on both sides of the conductive layers 7A to 7D in self-alignment with them. This impurity introduction mask 9 is used to constitute a substantial source region or drain region, and is mainly used to construct L D D 41 il. Note that the impurity introduction mask 9 is removed after forming an n+ type semiconductor region and a P+ type semiconductor region, which will be described later, and does not need to be present when the SRAM is completed.

10 is an n+ type semiconductor region, and conductive layers 7A, 7C1
The main surface of the well region 2 via the insulating film 5 on both sides of 7D,
Alternatively, it is provided on the main surface of the well region 2 in the connection hole 6 portion under the conductive layers 7B and 7C17D. This semiconductor region 1
0 is for configuring the substantial source region or drain region of the MI S FET, or the cross-coupling wiring of the flip-flop circuit.

The semiconductor region 10 is formed using the impurity introduction mask 9,
Since they are formed by introducing impurities using ion implantation technology, they are self-aligned with the impurity introduction mask 9 or the S conductive layers 7A to 7D.

11 is a P+ type semiconductor region, and a predetermined semiconductor region 1
It is provided on the main surface of the well region 2 below the semiconductor region j or 10 in contact with the semiconductor region j or 10.

In particular, this semiconductor region 11 is the lower part of the semiconductor region 10 of the MISFET Q+ and Q2 of the flip-flop circuit, and the lower part of the semiconductor region 10 of one of the MISFETs QSI and Qs2 for the switch (indicated as 1i(p'' in FIG. 2)). In other words, the semiconductor region 11 is provided in a portion that contributes to increasing the amount of charge that is stored as information in the memory cell. The semiconductor region 11 is a pn junction with a higher impurity concentration than the pn junction between the well region 2 and the semiconductor region 10, increasing the junction capacitance and accumulating charges that serve as information in the information storage capacitor C. By increasing the amount of accumulated charge that serves as information, it is possible to prevent soft errors caused by alpha (hereinafter referred to as α) rays. Since the impurity concentration is higher than that of the impurity concentration, it is possible to enhance the barrier effect of suppressing unnecessary invasion of minority carriers generated by α rays, and it is possible to prevent soft errors as described above.

Further, since the semiconductor region 11 is formed by introducing impurities by ion implantation technique using the impurity introduction mask 9, it is configured so that it does not reach the region where the channel is formed, and the impurity introduction mask 9 or , self-aligned to conductive M7C17D. This eliminates the need for mask alignment allowance in the manufacturing process for configuring the semiconductor region 11, so that the degree of integration of the SRAM can be improved.

In addition, since the impurities (for example, boron ions) constituting the semiconductor region 11 have a faster diffusion rate than the impurities (for example, arsenic ions) constituting the semiconductor region 10, and the same impurity introduction mask 9 is used, The semiconductor region 11 is
It is provided along the semiconductor region 10 or so as to wrap around the semiconductor region 10 . By this, the semiconductor value jtll
Since the pn junction area between the semiconductor region 10 and the semiconductor region 10 can be increased, the junction capacitance can be further increased or the barrier effect can be further enhanced.

Further, the semiconductor region 11 is provided at least under the semiconductor region 8, that is, in a portion that suppresses a depletion region extending from the pn junction between the semiconductor region 10 and the well region 2 to a region where a channel is formed. This can prevent coupling of the depletion region between the semiconductor regions 10 between the source region and the drain region, thereby preventing punch-through. By preventing this punch-through, the short channel effect can be reduced.

Note that the semiconductor region 11 may be used simply to enhance the barrier effect, and in that case, it is appropriately separated from the semiconductor region 10.

In addition, grooves are formed in the semiconductor region 10 using 7A to 7C as impurity introduction masks, and the semiconductor region 11 is used as an impurity introduction mask 9.
The semiconductor region 8 may be omitted.

MISFETQ's for switches 1. Q
S2 mainly includes the well region 2, the insulating film 5, the conductive layer 7A, the pair of semiconductor regions 8, and the pair of semiconductor values f! J,i
o and a semiconductor region 11.

M I S F E T Q + mainly includes a well region 2, an insulating film 5, a conductive layer 7D, a pair of semiconductor regions 8,
It is composed of a pair of semiconductor regions 10 and 11.

M I S F E T Q 2 mainly includes a well region 2, an insulating film 5, a pair of conductive layers 7C1, and a pair of semiconductor regions 8.
It is composed of a pair of semiconductor regions 10 and 11.

An insulating film 12 is provided to cover the conductive layers 7A to 7D, the semiconductor region 10, and the like. This insulating film 12 is for electrically separating the conductive layers 7A to 7D, the semiconductor region 10, and the like from the conductive layer provided thereabove.

Further, the insulating film 12 is used as a gate insulating film for configuring an MIS type JM structure for self-biasing the resistance elements R1 and R2, and further as an insulating film for configuring the information storage capacitor C. The semiconductor region 11 includes an insulating film 1
2 may be formed.

13 is a connection hole, which is provided by removing a predetermined conductive layer 7C17D and the insulating film 12 above the semiconductor region 10. This connection hole 13 is for electrically connecting a predetermined conductive layer 7C17D and semiconductor region 10 to a conductive layer provided thereabove.

14A is a conductive layer, and conductive layer 7B (reference voltage wiring V
s s ), and extends above the insulating film 12 in substantially the same row direction as the conductive layer 7B. This conductive layer 14A is for configuring a power supply voltage wiring Vcc connected to each of the memory cells arranged in the row direction.

Conductive layer 14A (power supply voltage wiring Vce) and conductive layer 7B (
By overlapping the reference voltage wiring Vss) with the insulating film 12 interposed, the amount of charge stored as information in the information storage capacitor C can be increased. The increase in the storage amount of the information storage capacitor C is made larger because the thickness of the insulating film is thinner than that in the case where the conductive layer 14A and the reference voltage wiring made up of the semiconductor region are superimposed. be able to. By increasing the storage amount of the information storage capacity C, soft errors caused by α rays can be prevented.

Further, a predetermined portion of the conductive layer 7B is configured to have a larger area than other portions, a predetermined portion of the conductive layer 14A is configured to have a larger area than the other portion, and the predetermined portion of the conductive layer 7B and the conductive layer 14A are configured to have a predetermined portion larger than the other portions. The storage amount of the information storage capacity C may be further increased by overlapping a predetermined portion of the information storage capacity C.

14B is a resistance element, one end of which is electrically connected to the conductive layer 14A, and the other end of which is connected to the conductive layer 14A through the connection hole 6.13.
7G, semiconductor region 10 or conductive layer 7D, semiconductor region 10
electrically connected to.

This resistance element 14B is for configuring resistance elements R1 and R2.

The resistance element 14B is connected to the conductive F17C via the insulating film 12.
Alternatively, it is provided so as to overlap the conductive layer 7D and extend in substantially the same column direction. That is, the conductive layer 7C or the conductive layer 7D is used as a gate electrode, the insulating film 12 is used as an insulator, and the resistive element 14 is used as a gate electrode.
It constitutes an MIS type structure in which B is a semiconductor. This is the conductive layer 7D (gate electrode) of M I S FET Ql.
is applied to a “High” level potential, and M I S
The conductive layer 7C (gate electrode) of FETQ2 is tr
When a potential at the Lo, HP level is applied, the current from the power supply voltage wiring Vcc easily flows through the resistance element 14B (R2), and the resistance element 14B (R□) is connected to the power supply voltage wiring Vcc. Current from Vcc becomes difficult to flow (self-bias).

That is, the resistance element 14B (R>, R2) is
The resistance value can be changed depending on the information (voltage) written in the memory cell, and current can be supplied in a direction that makes the voltage difference between II II II and rr On clear.
Charges that serve as information can be stably held.

The conductive layer 14A and the resistance element 14B are formed by a second conductive layer forming step in the manufacturing process, for example,
It is made of polycrystalline silicon formed by chemical vapor deposition (hereinafter referred to as CVD) technology.

The conductive layer 14A is formed by introducing an impurity into polycrystalline silicon to reduce the resistance value, and the resistance element 14B is formed by using polycrystalline silicon as it is or by introducing a moderate amount of impurity into it that is smaller than that of the conductive layer 14A. Form. The impurity constituting the conductive layer 14A is introduced by ion implantation using, for example, arsenic ions. Since the introduction of impurities by ion implantation technology has no dependence on impurity concentration, the controllability of the resistance value of the conductive layer 14A is much better than that by thermal diffusion technology.

Also, the introduction of impurities through ion implantation technology.

Compared to the thermal diffusion technique, since the amount of the impurity introduced into the lower part of the mask is smaller, the allowance for processing dimensions can be reduced, and the resistance element 14B can be reduced in size or the resistance element 14B can be made sufficiently long.

In addition, in the process of forming the second conductive layer, there is no need to configure wiring such as cross-coupling of the flip-flop circuit, and it is only necessary to consider the margin for mask alignment between the conductive layer 14A and the resistive element 14B. The resistance element 14B can be reduced or the resistance element 14B can be configured to be sufficiently long between the conductive layer 14A and the connection hole 13.

By configuring the resistive element 14B to be sufficiently long,
Its resistance value can be increased, and the standby current flowing from resistive element 14B can be reduced in order to retain information.

Further, by configuring the resistive element 14B to be sufficiently long, the junction between the resistive element 14B and the conductive layer 14A, the resistive element 14B and the semiconductor region 10, the conductive layer 7C17D
It is possible to prevent coupling between the depletion region formed inside the resistance element 14B from the junction with the resistor element 14B. by this,
Punch-through in the resistance element 14B can be prevented.

The introduction of impurities by ion implantation allows for good controllability of the resistance value, so it may be used in the configuration of resistive elements in one peripheral circuit, for example, an input protection circuit. Same manufacturing process as layer 14A and same degree
It may be configured with a resistance value of about

15 is an M edge film, which includes a conductive layer 14A and a resistive element 14B.
It is located at the top. This insulating film 15 is a conductive layer 14
This is for electrically separating the conductive layer A and the resistive element 14B from the conductive layer provided thereon.

16 is a connection hole, MISFET Q s for switch
1. It is provided by removing the insulating film 5, 12, 15 above one semiconductor region 10 of Q S 2.

This connection hole 16 is for electrically connecting the semiconductor region 10 and a conductive layer provided on the insulating film 15 .

A conductive layer 17 is electrically connected to a predetermined semiconductor region 10 through a contact hole 16, and the upper part of the insulating film 15 is connected to the conductive layer 7.
It extends in the column direction so as to intersect with A, 7B, and 14B, and is provided to overlap with the conductive layer 7C17D and the resistive element 14B. This conductive layer 17 includes data lines, L, DL.
It is for configuring. And conductive layer 7G, 1
7. By overlapping the resistive element 14B or the conductive Ji 17D, 17, and the resistive element 14B, the planar area can be reduced, so the degree of integration of the S RAM can be improved.

The conductive layer 17 is formed by a third conductive layer forming step in the manufacturing process.

A plurality of memory cells configured in this manner are arranged in the row direction in line symmetry with respect to the Xa-Xa line or the xb-xb line,
A plurality of cells are arranged in the column direction with rotational symmetry with a rotation angle of about 180[deg.] in Ya or Yb, forming a memory cell array.

Next, the manufacturing method of this example will be explained.

4 to 10 are diagrams showing SRAM memory cells in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention, and FIGS. 4 to 6 show the main parts thereof. The plan view and FIGS. 7 to 10 are sectional views thereof. In addition, FIG. 7 shows a cross section taken along the section line ■--■ in FIG. 4, and FIG. A cross section at the IX cutting step is shown, and FIG. 10 shows a cross section at the line xx#J of FIG. 6.

First, an n-type semiconductor substrate 1 made of single crystal silicon is prepared. A p-type well region Wi2 is formed in a predetermined main surface portion of this semiconductor substrate 1.

The well region 2 has, for example, 2×1012 [aIZo
ms/cm” B F2 iodine at 60[KeV
] is introduced by an ion implantation technique with an energy of about 100%, and is formed by stretching and diffusing.

Then, a field insulating film 3 is formed on a predetermined main surface of the semiconductor substrate 1 and the well region 2, and a p-type channel stopper region 4 is formed on a predetermined main surface of the well region 2.

The field insulating film 3 is a silicon oxide film formed by selective thermal oxidation technology.

The channel stopper region 4 is 1, for example, 3×10” [ato
ms/cm About 2 B F 2 ions at 60 [
It is introduced by an ion implantation technique with an energy of about 'KeV, and is formed by stretching and diffusing the field isolation film 3 by a thermal oxidation technique.

Next, as shown in FIGS. 4 and 7, an insulating film 5 is formed on the main surfaces of the semiconductor substrate 1 and the well region 2, which will be the semiconductor element formation region.

The insulating film 5 is made of, for example, a silicon oxide film formed by thermal oxidation technology, and has a film thickness of 200 to 300 [ongest stromal (hereinafter referred to as A) film] so as to constitute the gate insulating film of the M'l5FET. to form.

After the step of forming the insulating film 5 shown in FIGS. 4 and 7, a predetermined portion of the insulating film 5 is removed to form a connection hole 6.

Then, conductive conductors m7A to 7D are formed so as to be connected to the main surface of a predetermined well region 2 through the upper part of the field insulating film 3, the upper part of the insulating film 5, or the contact hole 6.

The conductive layers 7A to 7D are formed by, for example, a polycrystalline silicon film 7a formed by CVD technology and having phosphorus ions diffused therein to reduce resistance, and a molybdenum silicide film 7b formed by sputtering technology on top of the polycrystalline silicon film 7a. . The thickness of the polycrystalline silicon film 7a is, for example, about 2000 [A], and the thickness of the molybdenum silicide film 7b is, for example, about 300 [A].
It may be formed with approximately 0 [A1.

Leads ff1ff7A to 7D are molybdenum silicide 7
Since it is made up of a, its resistance value can be set to about several [Ω/mouth].

Although not shown, the main surface of the well region 2 connected to the conductive layer 7B, 7C, or 7D through the connection hole 6 is an n-type semiconductor region where phosphorus ions introduced into the polycrystalline silicon film 7a are diffused. is starting to form.

Next, as shown in FIG.
A, L on the main surface of the well region 2 on both sides of 7C17D.
In order to configure the DD structure, an n-type semiconductor region 8 is formed.

The semiconductor region 8 is formed by using the conductive layers 7A, 7C17D and the field insulating film 3 as a mask for impurity introduction, for example.
Phosphorus ions of approximately I Xl01'' [at, oms/cjn2] are implanted into grooves using an ion implantation technique with an energy of approximately 50 [KeV], and stretched and diffused to form the grooves.

After the step of forming semiconductor region 8 shown in FIG. 8, impurity introduction masks 9 are formed on both sides of conductive layers 7A to 7D in self-alignment.

This impurity introduction mask 9 is formed, for example, by applying an anisotropic etching technique to a silicon oxide film formed by a CVD technique. Also, as the mask 9 for impurity introduction, CVD
A polycrystalline silicon film formed by a technique may also be used.

Then, using the impurity introduction mask 9, an n+ type semiconductor region 10 is formed in a predetermined main surface portion of the well region 2 in self-alignment with the impurity introduction mask 9 or the conductive layers 7A to 7D.

This semiconductor region 10 is, for example, 1 x
Arsenic ions of about 1O"'[ajoms/cm' are introduced by an ion implantation technique with an energy of about 80 [K e V ], and are formed by stretching and diffusion.

Thereafter, an impurity introduction mask (not shown) is formed mainly to introduce p+ type impurities that increase the amount of accumulated charge serving as information.

Then, as shown in FIGS. 5 and 9, using this impurity introduction mask and the impurity introduction mask 9, a predetermined shape is self-aligned with respect to the impurity introduction mask 9 or the conductive layers 7C and 7D. A p+ type semiconductor region 11 is formed on the main surface of the upper and lower well regions 2 of the semiconductor region IO.

The semiconductor region 11 is, for example, L
mS/. Boron ions of about 2] are introduced by an ion implantation technique with an energy of about 50 [KeV1, and stretched and diffused.

In FIG. 5, impurities forming the semiconductor region 11 are introduced into the main surface of the well region 2 through the insulating film 5 in the region surrounded by the dotted line indicated by 11 (p''). A dotted line 11 (p'') indicates the pattern of the impurity introduction mask.

At this time, the conductive layers 7A to 7D, the semiconductor regions 8, and 1O are formed in the same manufacturing process as that of the MISFET forming the peripheral circuit, and the semiconductor region 11 is formed as a predetermined n+ type semiconductor region. The lower portion 1 may be formed, for example, below the source region and drain region of a MISFET constituting the input protection circuit.

After the step of forming the semiconductor region 11 shown in FIGS. 5 and 9, an insulating film 12 is formed. This insulating film 12 is formed using, for example, a silicon oxide film formed by CVD technology, and has a thickness of about 1000 to 2000 [A].

Then, a predetermined conductive layer 7C17D and the insulating film 12 above the semiconductor region 10 are removed to form a connection hole 13.

After that, in order to form power supply voltage wiring and a resistance element, connection is made to a predetermined semiconductor region 10 through a connection hole 13,
A polycrystalline silicon film is formed to cover the upper part of the insulating film 12. This polycrystalline silicon film may be formed by, for example, CVD technology, and the film thickness may be approximately 1000 to 2000 [A].

Then, an impurity for reducing the resistance value is introduced into the polycrystalline silicon area which is the power supply voltage wiring formation area other than the resistance element formation area. This impurity uses arsenic ions,
It is introduced by ion implantation technology and diffused by thermal diffusion technology.

Thereafter, as shown in FIGS. 6 and 10, the polycrystalline silicon film is patterned, and the power supply voltage wiring V
Conductive layer 14A and resistance element R used as c c
1, a resistance element 14B used as R2 is formed.

Note that impurities introduced to form the conductive layers 14A and 14B are introduced into the polycrystalline silicon film outside the region surrounded by the dotted line 14B in FIG.

Conductive layer 14A and resistance element 1 shown in FIGS. 6 and 10
After the step of forming 4B, an insulating film 15 is formed. This insulating film 15 uses, for example, a phosphor silicate glass film formed by CVD technology, and has a film thickness of 30 mm.
What is necessary is just to form it to about 00-4000 [A].

Then, the insulating film 5.12.
15 is removed to form a connection hole 16.

After this, as shown in FIGS. 2 and 3, the connection hole 1
The conductive layer 17 is electrically connected to a predetermined semiconductor region 10 through the conductive layer 6 and extends in the column direction so as to cross the conductive layer 7A on the upper part of the insulating film 15.

For the conductive layer 17, for example, an aluminum film formed by sputter deposition technology is used.

Through these series of manufacturing steps, the SRAM of this embodiment is completed. Note that, after this, a treatment process such as a protective film may be performed.

[Effects] As explained above, according to the novel technical means disclosed by the present application, the following effects can be obtained.

(1) M forming the flip-flop circuit of the memory cell
By overlapping the gate electrode of the ISFET and the resistive element, the resistive element can be self-biased, so that charges serving as information can be stably held.

(2) Due to (1) above, the operating margin in the information read operation can be increased, so the SRAM
It is possible to improve the electrical reliability of the

(3) By introducing impurities that reduce the resistance value of the conductive layer made of polycrystalline silicon using ion implantation technology, there is no dependence on impurity concentration compared to thermal diffusion technology, so the resistance value can be controlled better. It can be done.

(4) According to the above (3), the controllability of the resistance value of the conductive layer or the resistance element can be improved, so the electrical reliability of the SRAM can be improved.

(5) By introducing impurities that reduce the resistance value of the conductive layer made of polycrystalline silicon using ion implantation technology, it is possible to reduce the amount of impurities entering the lower part of the impurity introduction mask that forms the resistance element. , it is possible to reduce the margin of processing dimensions of the resistance element.

(6) According to (5) above, it is possible to reduce the margin of processing dimensions of the resistor element, so the area occupied by the resistor element can be reduced, and the degree of integration of the SRAM can be improved.

(7) According to (5) above, it is possible to reduce the margin of machining dimension of the resistance element, so that the resistance element can be configured to be sufficiently long.

(8) According to (7) above, the resistance element can be configured to be sufficiently long, so that the standby current flowing from the resistance element can be reduced.

(9) According to the above (7), it is possible to prevent coupling between the depletion regions extending inside the resistance element, and therefore, it is possible to prevent inch-through in the resistance element.

(10) By overlapping the gate electrode of the MISFET that constitutes the memory cell, the resistance element, and the data line connected to the memory cell, the planar area can be reduced, so the degree of integration of the SRAM can be improved. Can be done.

(11) Since the reference voltage wiring connected to the memory cells is formed of a conductive layer with a low resistance value such as polycide, silicide, or high melting point metal, the area occupied by the reference voltage wiring in the memory cell array can be reduced. Can be done.

(12) Since the reference voltage wiring connected to the memory cell is made of the same conductive material as the gate electrode of the MISFET with low resistance that constitutes the memory cell, the area occupied by the reference voltage wiring in the memory cell array is reduced. Can be reduced.

(13) Due to (11) and (12) above, it is possible to reduce the number of aluminum wires connected to the reference voltage wire at a given time, reducing the area occupied by the aluminum wires in the memory cell array. can do.

(14) According to (11) to (13) above, the area occupied by the reference voltage wiring or aluminum wiring in the memory cell array can be reduced, so the degree of integration of the SRAM can be improved.

(15) Due to (11) and (2) above, it is possible to reduce the resistance value of the reference voltage wiring and improve the stability of its potential, thereby increasing the margin for information writing and reading operations. Can be made larger.

(16) According to (15) above, malfunctions in information writing and reading operations can be suppressed, so
The electrical reliability of SRAM can be improved.

(17) Reference voltage wiring V s s and power supply voltage wiring V
Since the capacitors cc and cc are superimposed, it is possible to increase the amount of charge stored, which becomes the information of the information storage capacitor of the memory cell.

(18) According to the above (17), it is possible to increase the amount of accumulated charge serving as information, so that soft errors caused by α rays can be prevented.

(19) According to (17) and (18) above, the amount of accumulated charge serving as information can be increased and soft errors can be prevented, so that the area occupied by the memory cell can be reduced.

(20) According to the above (19), the area occupied by the memory cell can be reduced, so the degree of integration of the SRAM can be improved.

(21) According to the above (17), the amount of accumulated charge serving as information can be increased, so that the reliability of the information read operation can be improved.

(22) By extending the gate electrode of one MISFET of a flip-flop circuit composed of two MISFETs and performing cross-coupling, there is no need to provide wiring for cross-coupling between the gate TtI poles. The pitch between gate electrodes can be reduced.

(23) According to the above (22), the area occupied by the memory cell can be reduced, so the degree of integration of the SRAM can be improved.

(24) An impurity introduction mask is provided in self-alignment on the side of the gate electrode of a predetermined MTSFET constituting a memory cell, and a first impurity introduction mask that becomes a source region or a drain region is self-aligned with respect to the impurity introduction mask. By providing a semiconductor region and a second semiconductor region of an opposite conductivity type below the semiconductor region, there is no need for a margin for mask alignment between the gate electrode and the second semiconductor region, thereby improving the degree of integration of the SRAM. be able to.

(25) According to (24) above, it is possible to form the second semiconductor region with the impurity introduction mask and prevent the channel region from entering the second semiconductor region.
Fluctuations in the threshold voltage of the FET and increases in the substrate effect constant can be prevented.

(26) According to (24) and (25) above, the degree of integration and electrical reliability of the SRAM can be improved.

(27) By providing the second semiconductor region along and below the first semiconductor region, the pn junction capacitance between the first semiconductor region and the second semiconductor region can be increased, so information storage It is possible to increase the amount of charge accumulated, which serves as information on the capacity used.

(28) By providing the second semiconductor region along and below the first semi-conductor region, it is possible to increase the opposing area of the first semiconductor region and the second semiconductor region, thereby improving the barrier effect. can be increased.

(29) According to the above (27), the amount of charge stored as information in the information storage capacitor can be increased, so that soft errors caused by α rays can be prevented.

(30) According to the above (29), the area occupied by the memory cell can be reduced, so the degree of integration of the SRAM can be improved.

(31) By providing the second semiconductor region in a portion that suppresses the depletion region extending to the region where the channel is formed, it is possible to prevent the depletion region from coupling between the source region and the drain region. can be prevented.

(32) According to (31) above, punch-through can be prevented, so the short channel effect can be reduced.

(33) According to the above (32), the short channel effect can be reduced, so the degree of integration of the SRAM can be improved.

Although the invention made by the present inventor has been specifically explained in the examples above, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention. Of course you can get it.

For example, in the above embodiment, an example was explained in which an M I S FET constituting a flip-flop circuit and a switching element was formed on a semiconductor substrate. I
An S FET may also be configured.

Furthermore, although the above embodiment has been described as an example applied to an SRAM having a resistive element and a MISFET, the present invention may also be applied to other semiconductor integrated circuit devices having a resistive element and a MISFET.

[Brief explanation of the drawing]

FIG. 1 shows an SRAM for explaining one embodiment of the present invention.
2 is a cross-sectional view of a main part of an SRAM memory cell for explaining an embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the section line ■-■ in FIG. 2. 4 to 10 are diagrams showing an SRAM memory cell in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention. 4 to 6 are plan views of the main parts thereof. FIGS. 7 to 10 are cross-sectional views thereof. In the figure, 1... semiconductor substrate, 2... well region, 3...
...Field insulating film, 4...Channel stopper region. 5.12.15... Insulating film, 6.13.16... Connection hole, 7A to 7D, 14A, 17... Conductive layer, 8°10.11... Semiconductor region, 9... Impurity introduction mask, 14B...resistance element, DL, DL...data line. WL...word line, Q+, Q2, Qs 1. Qs
2... MISFET, R□, R2... Resistance element, C
...Capacity for information storage, Vss...Wiring for reference voltage,
VcC: Electric g voltage wiring.

Claims (1)

[Claims] 1. A flip-flop circuit configured with two resistance elements and two MISFETs and having a pair of input/output terminals, and a switch MISFET connected to each input/output terminal of the flip-flop circuit. What is claimed is: 1. A semiconductor integrated circuit device having a memory cell comprising: a gate electrode of a MISFET of the flip-flop circuit; and a resistor element stacked on top of each other. 2. The gate electrode is made of polycrystalline silicon, a high melting point metal with a low resistance value, silicide which is a compound of a high melting point metal and silicon, polycide in which silicide is provided on top of polycrystalline silicon, etc. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the resistive element is made of polycrystalline silicon or polycrystalline silicon into which impurities are appropriately introduced. 4. Each of the semiconductor integrated circuit devices according to claims 1 to 3, wherein the gate electrode and the resistance element are overlapped with an insulating film interposed therebetween. 5. The resistive element overlapped with the gate electrode,
Claims 1 to 4, characterized in that one end thereof is electrically connected to one semiconductor region of the MISFET having the gate electrode, and the other end is connected to power supply voltage wiring. Each semiconductor integrated circuit device described in . 6. A flip-flop circuit composed of two first resistance elements and two MISFETs connected to power supply voltage wiring and having a pair of input/output terminals, and connected to each input/output terminal of the flip-flop circuit. 1. A semiconductor integrated circuit device having a memory cell configured with a switch MISFET, wherein the power supply voltage wiring and a first
a second resistance element different from the first resistance element in a region other than the memory cell; A semiconductor integrated circuit device, characterized in that it is formed by the same manufacturing process as the power supply voltage wiring. 7. The semiconductor integrated circuit device according to claim 6, wherein the impurity is an arsenic ion. 8. The semiconductor integrated circuit device according to claim 6 or 7, wherein the second resistance element constitutes a resistance element of an input protection circuit. 9. Claim No. 9, characterized in that the second resistance element has a sheet resistance value that is approximately the same as that of the power supply voltage wiring.