JPS6177193A - Dynamic memory - Google Patents

Abstract

PURPOSE:To increase a quantity of a signal read from a memory cell by connecting a plate electrode of a memorizing capacitor to a bit line connected to a sense amplifier in a differential pair with a bit line to which the memory cell is connected. CONSTITUTION:At an intersecting position of a bit line BLi and a word line WLj, a memory cell MCij is disposed. The memory cell MCij is comprise of a transferring MOSFET11 and a memorizing capacitor 12. A plate electrode 12a of a memorizing capacitor 12 is connected to the bit line BLi connected to a sense amplifier 14 in a differential pair with the bit line BLi to which the memory cell MCij is connected. Thereby, during an information reading operation from the memory cell, an electric potential of a pair of bit lines is changed in the opposite directions by the same quantity, so that an equivalent reading signal quantity can be duplicated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic memory, and particularly to the structure of a memory cell thereof.

[Technical background of the invention and its problems]

Generally, a memory cell of a dynamic memory is configured as shown in FIG. 3, for example.

In the figure, BL is a bit line, WLj is a word line,
A memory cell MC,j is provided at the intersection of the bit line BL and the word condensed milk. This memory cell M
C1j is composed of one transfer MO3FET 11 and one storage capacitor 12, and
The bit line BL is connected to one end of the 8FET 11, and one electrode of the capacitor 12 is connected to the other end. Further, the above-mentioned condensed milk is connected to the dart of the MO8FET 11, and the plate voltage source 13 is connected to the other electrode (plate electrode) of the above-mentioned capacitor 12.

When the memory cell MC is selected by the word condensed milk and the bit line BL, the potential of the bit line BL changes according to the charge accumulated in the capacitor 12, and information is read out. .

FIG. 4 shows an example of the structure of the memory cell MCtJ. The semiconductor substrate 74 is provided with impurity diffusion regions 15K, 15. of the conductivity type opposite to that of the substrate 14 as source and drain regions of the MOSFET 11. are formed at predetermined intervals. This impurity diffusion region 15. ．． 15. A dirt electrode 17 is formed on the semiconductor substrate 14 in between with a gate insulating film 16 interposed therebetween. Further, the semiconductor substrate 14
An impurity diffusion region 18 having the same conductivity type as this region 152 is formed in a fused state with the impurity diffusion region 15□. Then, an oxide film 1 is formed on this impurity diffusion region 18.
An electrode 20 is formed through the MOS gear
2 is formed.

Note that 21 is a field oxide film.

The readout signal amount of the memory cell in the above configuration will be explained with reference to FIG. 5, which is a model of FIG. 3. The switch 5WII corresponds to the MOSFET I1, and the capacitor C8 is the capacitance of the bit line BL. Now switch 5WII is open (MOS
FET 7 z is off), the potential of node Na is set to V
If the potential of the ccl node PNb is v8, the potential of the plate voltage source I3 is vP, and the potential of the nodes Na and Nb after closing the switch SW is vx, then since the charge is conserved, c8(vg- v, )+c, vcC=
c, (vx-v,)+c,vx・(i), and the above formula (
1), vX ” vCC-CB (vCC-vIri/CCB+C
[1) "'(2). Therefore, the read signal amount ΔV is Δv" vcc −"x −1−(
3), and by substituting the above equation (2) into the above equation (3), Δv
"Cs (vcc - VB)/ (1-1+C++
)...(4).

As described above, the amount of signals read from the memory cells is small, and there is a drawback that it becomes difficult to prevent soft errors and to ensure the S-r ratio for the sensing operation of the sense amplifier, especially when the integration is highly integrated.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a dynamic memory that can increase the amount of read signals from memory cells.

[Summary of the invention]

That is, in order to achieve the above object, the present invention provides a dynamic memory in which memory cells each consisting of one transfer transistor and one writing capacitor are arranged in a matrix. The plate electrodes of the storage gear 9 are connected to the bit line connected to the sense amplifier forming a differential pair with the bit line connected to the memory cell.
During the information read operation from the memory cell, the potentials of the bit line pair change by the same amount in opposite directions, so the read signal amount can be equivalently doubled.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 3 are given the same reference numerals and their explanations will be omitted. That is, the plate electrode 12h of the storage capacitor 12 is connected to the bit line BL1 connected to the sense amplifier 14 forming a differential pair with the bit #1iBL1 to which the memory cell MC1j is connected.

In the above configuration, the amount of signal read from the storage capacitor 12 is calculated using FIG. 2, which is a model of the circuit shown in FIG. 1.

Note that C3 is the parasitic capacitance of the bit line BLl, and C, / is the parasitic container of the bit line BL. First, switch 5
Assume that W11 is open (MOSFET JZ is off), and the potential of node N1 in this state is vcc
Node Nbf)i! The position is set to v8. Then, when the switch SWI1 is closed, the potential of the storage capacitor 12 becomes v2, and the potential of the nodes Nb and Nc becomes vl.
Assuming that, since the charge is conserved, ...(6). From the above formulas (5) and (6), the memory gear 9
This is because the signal amount ΔV' read out from the bit line 12 is the difference between the paired bit lines. Therefore, two times the signal amount of both equations (4) can be obtained,
It becomes easy to prevent soft errors in the case of high integration and to secure the S-ratio for sensing operation of the sense amplifier.

〔Effect of the invention〕

As explained above, according to the present invention, a dynamic memory that can increase the amount of read signals from memory cells can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a memory cell of a dynamic memory according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a model of the circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing a memory cell of a conventional dynamic memory, FIG. 4 is a cross-sectional view showing an example of the structure of the memory cell shown in FIG. 3, and FIG. 5 is a model of the circuit shown in FIG. 3 above. FIG. 11...MOSFET (transfer transistor), 1
2...1 self-memory register, 13...plate voltage source, 14...sense amplifier, MC1'...memory cell, BL, , BL...bit line, WIg-word line .

Claims (1)

[Claims] In a dynamic memory configured by memory cells each consisting of one transfer transistor and one storage capacitor arranged in a matrix, the plate electrode of the storage capacitor is connected to the memory cell. A dynamic memory characterized by being connected to a bit line that forms a differential pair with a bit line and is connected to a sense amplifier.