JPS60258794A - Dynamic type semiconductor memory - Google Patents

Abstract

PURPOSE:To enlarge the degree of freedom of pattern designing of a large scale memory element by providing a memory cell structure made by connecting the first diffusion area and the fourth wiring means by a contact hole and using the third and fourth wiring means in common to plural memory cells. CONSTITUTION:The first - third wiring means are made of ordinary polycrystalline silicon, silicide or high melting point metal etc., and the fourth wiring means is made of aluminum etc. The fourth wiring means 51 and the third wiring means 39 are used in common for plural memory cells and constitute complementary bit lines. Different wiring means are formed in multi-layer structure in the complementary bit lines, and the area of memory cell can be made small compared with conventional system that forms complementary bit lines by the same wiring means. As the area of the diffusion areas 34 and 35 is sufficient if it is enough to form contact windows 36 and 50, diffusion area in the memory cell is smaller than conventional system. alpha rays resisting strength is increased and stable memory element can be realized.

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention relates to improvement of a dynamic semiconductor memory device.
More specifically, the present invention relates to a dynamic semiconductor memory device having a novel configuration that enables high-performance dynamic devices.

<Technical background of the invention and its problems> In the memory cell configuration of a conventional dynamic memory element, the operating margin deteriorates due to manufacturing variations in the load capacitance of complementary bit lines used for inputting and outputting information. There was a problem.

That is, the circuit of a conventionally used N-channel MOS dynamic memory element is configured as shown in FIG. 9, for example.

'In Figure 9, S is Sense Ambucciari, ■ and 2
are complementary bit lines. Further, 3 and 3' are memory cells, and 4 and 4' are dummy cells. W, and W
j is a word line, WDo and WD are dummy word lines, and φ is a precharge signal.

5 and 5' are storage capacitors, and 6 and 6' are transfer gates for selecting desired storage capacitors 5 and 5' and electrically connecting them to bit lines 1 and 2.

Here, the capacitance values of 5 and 5' are assumed to be Cs.

7 and 7' are dummy storage capacitors, whose capacitance values are CD
shall be.

8 and 8' are transfer gates for selectively connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2, and 9 and 9' are transfer gates for connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2 during the precharge period.
This is a gate for initializing 7' and 7'.

10 and 10' are bit line capacitances, and their capacitance values are expressed as C
Let it be B.

FIG. 10 is a timing diagram for explaining the operation of FIG. 9.

In FIG. 9, when the memory cell on the bit line 1 side is selected, the dummy cell 4' on the bit line 2 side is selected;
Furthermore, when the memory cell on the bit line 2 side is selected, the dummy cell 4 on the bit line 1 side is selected.

Here, a word line W and a dummy word line wD.

A case will be described in which (2) becomes a high potential and the memory cell 3 and dummy cell 4' are selected.

Here, it is assumed that a voltage boosted to a power supply voltage (Vcc) or higher is applied to the word line w1 and the dummy word line wDo. It is assumed that bit lines 1 and 2 are precharged with power supply voltage (Vcc) i during the precharge period when the short precharge signal φ1 is at a high potential. For convenience of explanation, bit line 1 is assumed to be B, bit line 2 is assumed to be W, and the logic of B: high potential and B: low potential is set to 11'', and B:
Low potential and B: High potential is set to logic 10''.

■ When the ground potential (GND) is stored in the storage capacitor 5 of the memory cell 3, the precharge signal φ2 falls to a low potential and enters the active period, and when the word line signal is input at time t, the bit line 1
The potential VB□ on the side becomes as follows.

On the other hand, the potential of the bit line 2 on the dummy cell side becomes VB2.

Therefore, it becomes a differential potential input to the sense amplifier S.

(2) When the power supply potential (Vcc) is stored in the storage capacitor 5 of the memory cell 3 In this case, the potential VB□ on the bit line 1 side does not change, and V Bt = V cc .

On the other hand, the potential VB2 of the bit line 2 on the dummy cell side is as follows.

Therefore, the differential potential ΔV2 input to the sense-up S is becomes.

Here, in both cases of ■ and ■ above, if the storage capacitance value CD of the dummy cell is determined so that the differential potential input to the sense amplifier S is the same, then the differential potential input to the sense amplifier become.

The above differential potential is amplified to a desired value by activating the sense amplifier S after time t2. In such a conventional system, the load capacitance balance of bit lines 1 and 2 is very important. However, due to manufacturing variations, it is difficult to maintain the capacitance balance between bit lines 1 and 2, resulting in a disadvantage that the operating margin deteriorates.

Attempts are still being made to realize large-scale memory devices with recent advances in microfabrication technology, but the memory cell area inevitably becomes smaller, and therefore the storage capacity within the memory cell tends to decrease even further. A new problem has arisen: the differential voltage necessary to drive the amplifier is no longer available.

In addition, as the memory cell area is reduced, the bit line pitch becomes smaller, and it becomes possible to accommodate the control circuits, sense amplifiers, etc. belonging to such bit lines within the above bit line pitch while maintaining the capacitance balance. It's becoming impossible.

<Objects and Structure of the Invention> The present invention has been made in view of the above points, and the present invention improves the differential voltage input to the sense amplifier compared to the conventional method even when the same storage capacitor as the conventional method is used. or the memory cell area can be configured very small to obtain the same differential voltage as the conventional method, and the stray capacitance balance of complementary bit lines required in the conventional method can be In contrast, it is an object of the present invention to provide a dynamic semiconductor memory device which has the advantage that the conventional method does not require careful consideration, and therefore the degree of freedom in designing patterns of large-scale memory elements is greatly increased. In order to achieve this object, the dynamic semiconductor memory device of the present invention includes complementary bit lines for inputting and outputting information, storage capacitor means for storing information, and selection means for specifying the storage capacitor means. one end of the storage capacitor means is connected to one of the complementary bit lines, and the other end of the storage capacitor means is connected to the other of the complementary bit lines via the selection means. A dynamic semiconductor memory device having a memory cell structure, wherein the selection means has a first diffusion region and a second diffusion region different from each other on the surface of the semiconductor substrate, and the first wiring means is gated. It is constituted by an MO8 field effect transistor serving as an electrode, and one end of the storage capacitor means is constituted by a second wiring means and is connected to the second diffusion region by a buried contact hole. The other end is constituted by a third wiring means, a desired storage capacitance is formed by a thin film region between the second wiring means and the third wiring means, and a desired storage capacitance is formed between the first diffusion region and the fourth wiring means. A memory cell structure is provided in which wiring means are connected by contact holes, and the complementary focus line is configured by sharing the third wiring means and the fourth wiring means for a plurality of memory cells. It is made to do so.

<Embodiments of the invention> A detailed description will be given below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of an embodiment of a dynamic semiconductor memory device according to the present invention, and is composed of an N-channel MO8 circuit.

In FIG. 1, S is a sense amplifier, 1 and 2 are complementary bit lines similar to those in FIG. 9, and 11 and 11 are complementary bit lines.
' is a characteristic memory cell in the present invention.

Wi and Wj are word lines to which signals having an amplitude equal to or higher than the power supply voltage (Vcc) are applied.

12 and 12' are storage capacitors, one end of which is connected to the complementary bit line 2, and the other end connected to the complementary pinto line 2 through the source-drain path of the transfer gate 13 or 13' that selects a desired memory cell. Connected to bit line 1 on the opposite side.

The gate of the above transfer gate 13 is word mW.
, and the gate of the transfer gate 13' is connected to the word line Wj.

14 and 15 are stray capacitances of bit lines 1 and 2.

Here, the storage capacitance value of the storage capacitors 12 and 12' of the memory cell is set to 03, the capacitance value on the bit line 1 side is set as CB□, and the capacitance value on the bit line 2 side is set as CB2. Capacity value CB of the octopus
,, CB2 are assumed to have different capacitance values (CB1':CB2) in order to make the features of the present invention clearer.

16 is a dummy storage capacitor, one end of which is connected to bit line 1.
The other end is connected to the dummy control signal φ9.

17 and 18 are sense input terminals of the sense amplifier S,
19 is MO8 field effect transistor (hereinafter MO8FE)
The source-drain path of the MO8FET 19 is interposed between the bit line 2 and the sense input terminal 18, and the voltage of the bit line 2 is controlled by the second control signal φT2 to one input terminal of the sense amplifier S. 020 is a MOSFET that electrically connects the bit line 2 and the input terminal 18 of the sense amplifier only during the period of input to the sense amplifier 18, and the source-drain path of the MO8FET 20 is interposed between the bit line 2 and the power supply Vcc. The bit line 2 is held at the power supply potential (Vcc) by the second precharge signal φP2 during the precharge period, the write period, or the active period of the sense amplifier S.

Reference numeral 21 denotes a conventionally used MO8FET for bit line precharging, and the source/drain path of this MO8FET 21 is interposed between the bit line 1 and the power supply Vcc, and the first precharge signal φ1□ is used during the recharging period. Bit line 1 is held at power supply potential (Vcc). 2
2 and 23 are conventionally used transfer gates between the bit line and the sense amplifier, and the first control signal φT1 temporarily disconnects the bit line and the sense amplifier at the beginning of driving the sense amplifier, increasing the sense sensitivity. There is a function to do that.

24 and 25 are column selection MO8FETs for selecting a desired complementary bit line, and by electrically connecting a desired bit line pair and data buses D and D by a column selection signal C, information can be input. Perform output.

Here, for convenience, a case will be described in which the bit line 1 is set to B and the bit line 2, and B: low potential and B: high potential are set to logic NO, and the memory cell 11 is selected.

(2) Writing of logic lit 1-rjl or logic XXO FIG. 2 shows a timing diagram for writing in the embodiment of the present invention.

When the precharge period ends, the first and second precharge signals φP1 and φP2 fall, and then the word line Wi
increases to 1 above the power supply voltage (Vcc) and a read operation is started, but if the current active period is a write cycle, the data to be written is output onto the data bus D.

Second precharge signal φ2. is again the power supply voltage (Vcc
), the MO8FET20 turns on and the bit line 2 is fixed at the power supply potential (Vcc), and the second control signal φ,2 still falls to the ground potential (G, ND) and the MO8FET20 turns on.
After the 8F'ET19 is turned off and the bit line 2 and sense amplifier S are disconnected, the column selection signal C1 rises to a potential higher than the power supply voltage (Vcc), and the MOS FET24
and 25 are turned on. At this point, data bus D
and bit line 1 are electrically connected.

As a result, the write data on data bus D is output onto bit line 1 and stored in node 26 of memory cell 11 via transfer gate 13.

In the case of writing logic 11, the power supply potential is output onto the data bus D, and therefore the power supply potential (Vcc) is stored in the node 26 of the memory cell 11. on the other hand,
In the case of writing the logic SS□//, the ground potential is output on the data bus D, and therefore the ground potential (GND) is stored in the node 26 of the memory cell 11.

Here, the other data bus D and bit line 2 are MO8FE
Since T19 is in the off state, it is electrically disconnected, so the information on data bus 5 is not involved in writing to the memory cell.

(2) Reading of logic signal 1/' A timing diagram for reading in the embodiment of the present invention is shown in FIG.

When the precharge period ends, the first precharge signal φ2□ goes to the ground potential (GND), and the second precharge signal φ2. falls to a predetermined potential that can sufficiently turn off the MOS and FET 20, and the bit lines 1 and 2 are disconnected from the power supply (Vcc) and become floating.

Next, the dummy drive signals φ are raised to the power supply potential (Vcc), and due to capacitive coupling of the dummy storage capacitor 16, the potential on the bit line 1 side is slightly raised above the power supply voltage (Vcc).

Next, a selection signal higher than the power supply voltage (Vcc) is input to the word line W 2 , and the bit lines 1 and 2 are capacitively coupled by the storage capacitor 12 via the transfer gate 13 .

Since the power supply potential (Vcc) was previously held at the node 26 of the memory cell 11, the potentials of the bit lines I and 2 only slightly change toward the lower potential side, and the potentials of the bit lines I and 2 No reversal of potential occurs.

The differential voltage between bit lines 1 and 2 in this case is Δ
v1, ...(Equation 2) The differential voltage ΔV1 is input to the input terminals 17 and 18 of the sense amplifier S.

Next, the first control signal φT1 drops to a predetermined potential and disconnects the sense amplifier S and bit lines 1 and 2, and then
Second control signal φ. , falls at the ground potential (GND) t, and the second precharge signal φ2. is again the supply voltage (
By increasing the potential to the power supply potential (Vcc) or higher and turning on the MO3FET 20, the bit line 2 is set to the power supply potential (Vcc).
Fixed to.

Next, the sense amplifier drive signal φ3 falls to the ground potential,
The differential voltage input to the sense amplifier S is amplified to a desired voltage. In this case, node 2 of memory cell 11
6 holds a high potential and there is no need to rewrite it.

(2) Reading of logic 'XO〃 A timing diagram of the bit line and sense input signal in reading of logic \\0'' is also shown in FIG.

The operation until the selection signal is input to the word line W1 is the same as reading the logic ``1''.Reading the logic IXO〃,
In this case, the ground potential (GND) is held in advance at the node 2G of the memory cell 11, so when the transfer gate 13 is turned on by the selection signal, the potential of the bit line I decreases, and conversely, the potential of the bit line I decreases. The potential of increases,
The potentials of bit line 1 and bit line 2 are reversed.

The differential voltage between bit lines 1 and 2 in this case is Δ
V2, then the differential voltage ΔV2 is input to the input terminals 17 and 18 of the sense amplifier S.

Next, the first control signal φ1 is activated in the same way as the logic ■1.
After □ falls to a predetermined potential and disconnects the sense amplifier S and bit lines 1 and 2, the second control signals φ and 2 fall to the ground potential (GND), and the second precharge signal φP2 The bit line 2 is fixed at the power supply potential (Vcc) by increasing the potential again to the power supply potential (Vcc) and turning on the MO8FET 20.

Next, the sense amplifier 1 drive signal φ falls to the ground potential, amplifies the differential voltage input to the sense amplifier S to a desired voltage, and discharges the bit line 1 to the ground potential via the MO8FET 22. Then, the ground potential (GND) is rewritten to the node 26 of the memory cell 11.

Here, if the dummy storage capacitance value CD is set so that the differential voltages ΔV and Δv2 between the bit lines when reading the logic N1" and the logic IQ" are both equal, the dummy storage capacitance value CD is as follows. , (Equation 2) and (Equation 3) eventually become ΔV=ΔV□=Δv2.

Here, in order to clarify the features of this method when compared with the conventional method, the differential signal voltage input to the sense amplifier under the condition of CB1 + CB2 - 2CB is calculated from (Equation 4) and (Equation 1). The results are shown in FIGS. 4 and 5.

FIG. 4 shows the relationship between the differential signal voltage and the stray capacitance ratio CB□/CB2 of bit line 1 and bit line 2 in the embodiment according to the present invention when CB/C8-10.

As is clear from the graph shown in Figure 4,
According to the present invention, if the sum of stray capacitances CB□ and CB2 of complementary bit lines 1 and 2 is constant, CB and CB
The differential signal voltage increases as the difference between bit lines 2 and 2 increases. Therefore, in order to make maximum use of the features of the present invention, it is necessary to minimize the stray capacitance of one bit line as much as possible. Therefore, a larger differential signal voltage can be obtained.

This is a very significant feature of the present invention, and completely eliminates the restriction that complementary bit lines must have the same stray capacitance as in conventional systems.
The degree of freedom in pattern design is greatly increased.

FIG. 5 shows CB/C for the conventional method and the embodiment according to the present invention under the condition that CB□10CB2-2CB.
8 shows differential signal voltage characteristics when changing the ratio.

28 is the differential signal voltage characteristic of the conventional system obtained by formula (1), and 27 is the differential signal voltage characteristic obtained by formula (4) in the embodiment according to the present invention.

In the embodiment according to the present invention, from FIG. 4, c81/CB
It has been shown that the differential signal voltage is the smallest when the value of 2 is around 1.0, but even in such a worst case, as shown in graph 28 in
A differential signal voltage that is about twice as high as that shown in graph 2 can be obtained, and by further devising the distribution of the bit line stray capacitance mentioned above.
9 or 30 characteristics can be realized.

This means that by adopting the method of the present invention, the differential signal voltage can be increased without changing the storage capacity of the memory cell, which is very effective as a means for realizing a large-scale memory element.

FIGS. 6 and 7 are diagrams each showing an embodiment of a memory cell structure related to the present invention of the dynamic semiconductor memory device shown in FIG. 1 above.

FIG. 6 shows a cross-sectional structure taken along line AA' in FIG. 7.

FIG. 7 is a pattern diagram for four memory cells (Mo□''-M3), and in an actual memory element, this pattern is repeatedly arranged as many times as necessary.

Next, the structure of a memory cell according to an embodiment of the present invention will be described with reference to FIG. 6, assuming an N-channel MOS process.

First, an element isolation region 32 is created on the surface of a P-type silicon substrate 31 by selective oxidation or the like, and then a portion 33 forming a word line and a transfer gate of a memory cell is formed by a first wiring means.

Next, diffusion regions 34 and 35 which will become the source and drain of the MOSFET are formed by ion implantation or the like.

Next, after opening a buried contact window 36 in the drain portion 34 of the transfer gate portion, one electrode 37 of the storage capacitor is formed by a second wiring means, and connected to the drain portion 34 of the transfer gate portion through the buried contact window 36. do.

Here, the electrode 37 formed by the second wiring means can also be formed on the upper surface of the first wiring means 33, contributing to an increase in the storage capacity of the memory cell. After forming a thin insulating film 38 for forming a storage capacitor on the upper surface of the second wiring means, the other electrode of the storage capacitor is formed by the third wiring means 39, and then an insulating film 40 is formed.

Next, after opening a normal contact window 50, a fourth wiring means 51 is formed, and the contact window 50 is connected to the source region 35 of the transfer gate portion. is generally made of ordinary polysilicon, oxide, or a high-melting point metal, and the fourth wiring means is generally made of aluminum or the like.

The fourth wiring means 51 and the third wiring means 39 are shared by a plurality of memory cells and constitute complementary bit lines. In other words, in the memory cell structure according to an embodiment of the present invention, complementary bit lines are formed with different wiring means in a multilayer structure, and therefore the conventional method in which complementary bit lines are formed with the same wiring means The memory cell area can be reduced compared to Also, diffusion area 3
Since the area of 4 and 35 is sufficient to form contact windows 36 and 50, the diffusion area in the memory cell is smaller than in the conventional method, and the resistance to alpha rays is increased, resulting in a stable memory element. can. FIG. 8 is a diagram showing an example of the arrangement of a memory cell array according to the above memory cell structure.

It has already been mentioned that according to the memory cell configuration according to the present invention, the memory cell area can be significantly reduced. but,
Along with this, the control circuits, sense amplifiers, etc. for the bit line pairs to which the memory cells are connected require a relatively larger area than the memory cells, and the above circuits are installed within the repeating bit line pitch mentioned above. A problem arises in that it becomes difficult to store.

This problem can be solved by arranging the control circuits, sense amplifiers, etc. that belong to a single bit line pair or a plurality of bit line pairs at both ends of each bit line pair.

In FIG. 8, Co "□ C63 is a complementary bit line pair, and K o = K63 is a control circuit, sense amplifier, etc. belonging to each complementary bit line pair co-063, and each bit M pair is An example in which they are arranged alternately at both ends is shown.In order to explain the present invention, an N-channel MOS process was used in the above embodiment, but the present invention does not limit the manufacturing process of the element. It can be applied to P-channel MOS process, CMOS process, SOI process, etc.

<Effects of the Invention> As described above, according to the present invention, the semiconductor substrate has a first diffusion region (source) and a second diffusion region (drain) which are different on the surface, and the first wiring means is the gate electrode. A MO8 field effect transistor constitutes a selection means for specifying the storage capacitance means, and one end of this storage capacitance means is constituted by a second wiring means, and is connected to the second diffusion region (drain) by a buried contact hole. , and the other end of the storage capacitor means is constituted by a third wiring means,
A memory cell structure is constructed in which a desired storage capacity is ensured in the thin film region between the second wiring means and the third wiring means, and the first diffusion region and the fourth wiring means are connected by a contact hole. Since the third wiring means and the fourth wiring means are shared by a plurality of memory cells to form complementary bit lines, the memory cell area can be reduced compared to the conventional one. In addition, the area of the above-mentioned diffusion region is sufficient as long as it is large enough to form a contact window, so the diffusion region in the memory cell is smaller than that of conventional memory cells, and the durability is improved. The α-ray intensity increases, and a stable semiconductor memory device can be obtained.

According to the present invention, the memory cell area can be made extremely small while maintaining a sufficient operating margin, and therefore it can greatly contribute to the realization of large-scale dynamic memory devices.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration of an embodiment according to the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment according to the present invention during a write cycle, and FIG. 3 is a diagram showing the circuit configuration of an embodiment according to the present invention. FIG. 4 is a timing diagram in a read cycle for explaining the operation of the embodiment. FIG. Mai II showing the relationship between
Figure 5 is a graph comparing differential signal voltages between complementary bit lines in a conventional system and an embodiment according to the present invention, and Figure 6 is a cross-sectional view of a memory cell structure in an embodiment according to the present invention. , FIG. 7 is a plan view of a memory cell structure according to an embodiment of the present invention, and FIG. 8 is a diagram illustrating an example of the arrangement of complementary bit lines, control circuits, sense amplifiers, etc. in an embodiment of a device according to the present invention. 9 is a circuit diagram of a dynamic memory element in the conventional method, and FIG. 10 is a timing chart for explaining the operation in the conventional method. wj, wj-word line, WDo, WD line, dummy word line, φ, precharge signal, φ, 1, first precharge signal, φ2. Second precharge signal, φゎ・
・Dummy control signal, φ0e ・First control signal, φT ・Second control signal, φ8...Sense drive signal, C1・
・Column selection signal, D, I) ・Data bus, CB + C
B□ICB2 - Bit line capacitance value, C8... Storage capacitance value of memory cell, CD... Storage capacitance value for dummy, ]. 2, B, B bit line, S... sense amplifier, 3゜3
', ] L 1 ]' ・Memory Seven Nope 4,4'
... Dummy cell, 12.12' ... Storage capacity of memory cell, 13.13' Transfer gate, 16... Storage capacity for dummy, 32 - Element isolation region, 34.35
Diffusion region, 36 Buried contact window, 33 - 1st
wiring layer, 37.. second wiring layer, 39.. third wiring layer, 51.. fourth wiring layer, 38.. thin insulating film, 5o..
Contact window, Co-C63...complementary bit line pair,
63 to KO~ Control circuits, sense amplifiers, etc. belonging to complementary bit line pairs. Agent Patent attorney Aihiko Fuku (and 2 others) 5 6 7
θ 9 10 II /2 /3 /4Ca/Cs Misfortune Figure 5

Claims (1)

[Scope of Claims] 1. Complementary bit lines for inputting and outputting information, storage capacitor means for storing information, and selection means for specifying the storage capacitor means; A dynamic semiconductor memory device having a memory cell structure in which one end of the storage capacitor means is connected and the other end of the storage capacitor means is connected to the other complementary bit line via the selection means. The selection means has a first diffusion region and a second diffusion region different from each other on the surface of the semiconductor substrate, and is constituted by an MO8 field effect transistor with the first wiring means as a gate electrode, and the storage capacitance means One end is constituted by a second wiring means and connected to the second diffusion region by a buried contact hole, and the other end of the storage capacitor means is constituted by a third wiring means, and the second wiring means and the A memory cell structure is provided in which a desired storage capacitance is formed by a thin film region between the third wiring means, and the first diffusion region and the fourth wiring means are connected by a contact hole, and the third wiring means and a dynamic semiconductor memory device, characterized in that the fourth wiring means is shared by a plurality of memory cells to form the complementary bit lines.