JPS61290753A - Complementary type mis semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve radiation resistance by forming a shielding plate electrode and a groove electrode in an element isolation region in a complementary type MISIC. CONSTITUTION:n<+> diffusion layers 12 are shaped in an element forming region 1 in p-type silicon while a gate electrode 6 is formed through a gate oxide film 3 as the surface. p<+> diffusion layers 13 are shaped in an element forming region 2 in n-type silicon while a gate electrode 7 is formed through the gate oxide film 3 as the surface. Shielding plate electrodes 4, 5 are shaped in the element isolation regions, and predetermined voltage V2, V1 is each applied. Groove electrodes 9 are formed to the lower sections of the electrodes 5, and connected to the electrodes 5. Accordingly, total-dose resistance by radiation exposure can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a highly radiation-resistant complementary MIS (Metal
-In5ulator -Sem1conducto
r) It relates to semiconductor integrated circuits.

[Prior art and its problems]

Conventionally, in this type of semiconductor integrated circuit, a thick field oxide film has been used to isolate elements.

However, when such a device is irradiated with radiation such as an electron beam, the flat band voltage fluctuates significantly due to the charges in the oxide film generated by the radiation irradiation and the interface state between the oxide film and the semiconductor substrate. This has the disadvantage that the element isolation function is significantly impaired, resulting in a lower so-called total dose tolerance.

Furthermore, in the space environment, high-energy heavy particles exist, and when these heavy particles enter a semiconductor integrated circuit, they generate a large number of electron-hole pairs within the semiconductor region. In circuits, this generated charge acts as a trigger and causes latch-up, resulting in loss of circuit function.

There is a problem that the element may be damaged.

In order to prevent the above latch-up, it is necessary to provide sufficient distance between the diffusion layer and the well. Therefore, increasing the latch-up resistance makes it difficult to increase the integration density.
Therefore, it has been difficult to realize a semiconductor integrated circuit with high latch-up resistance and high integration density.

Another possible solution to this problem is to improve latch-up resistance by lowering the parasitic resistance by using a low-resistance substrate and an epitaxial layer grown on it, but the effect is not sufficient, and Even if this method is used, the conventional device isolation technology using a thick field oxide film still has a problem in that the total dose tolerance is still low.

The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to provide a complementary MIS semiconductor integrated circuit with improved total dose tolerance and latch-up tolerance. That is.

[Means to solve the problem]

In order to achieve the above object, in the present invention, the complementary form M
In an IS semiconductor integrated circuit, a gate electrode of a second conductivity type of an MIS structure formed on a semiconductor element formation region of the first conductivity type, and an element isolation region on the semiconductor element formation region of the first conductivity type. a second conductivity type shield plate electrode of the MIS structure formed on the semiconductor element formation region of the second conductivity type and to which the first predetermined voltage is applied; a gate electrode of a conductivity type; and a shield plate electrode of a second conductivity type of the MIS structure formed in an element isolation region on the semiconductor element formation region of the second conductivity type and to which a second predetermined voltage is applied. a trench formed in a predetermined portion of the element isolation region in the semiconductor element forming region; an insulating film provided on the inner wall surface of the trench; and a second trench disposed inside the insulating film. A second conductivity type groove electrode of the MIS structure electrically connected to the conductivity type shield plate electrode, and within at least one of the conductivity type s1 and the second conductivity type semiconductor element formation region. and a second conductivity type diffusion layer formed in a predetermined region around the opening of the groove, and in at least one of the first conductivity type and the second conductivity type semiconductor element formation region. It has a structure in which either one or both of the formed diffusion layers and the shield plate electrode of the second conductivity type are electrically connected.

[Effect]

With the above configuration, the shield plate electrode of the MIS structure formed in the element isolation region on the semiconductor element formation region improves the total dose tolerance, and also reduces the parasitic effects formed between each element. Since the trench is blocked from the transistor and positive feedback between the parasitic transistors is prevented, latch-up resistance can be improved.

In addition, since the above-mentioned groove electrode and the diffusion layer have the same potential, problems caused by the insulation resistance of the insulating film are prevented, and furthermore, positive charges are generated in the insulating film by irradiation with radiation such as electron beams. When an inversion layer is formed around the groove due to charges, this inversion layer and the above-mentioned diffusion layer have the same potential, so that no potential difference occurs in the insulating film sandwiched between the inversion layer and the groove electrode.

This has the effect that problems caused by the insulation resistance of the insulating film in this portion can also be prevented.

A detailed explanation will be given below using the drawings.

〔Example〕

FIG. 1 is a sectional view of the first embodiment of the present invention. In FIG. 1, 1 is a p-type silicon semiconductor element formation region, 2 is an n-type silicon semiconductor element formation region, and 3 is a gate oxidation region. 4 and 5 are n-type polysilicon shield plate electrodes, 6 and 7 are n-type polysilicon gate electrodes, 8
9 is a silicon oxide film, 9 is an n-type polysilicon conductive electrode,
10. 11 and 12 are n+ diffusion layers, 13 is a p+ diffusion layer, and vl, 2 and V2' are respective predetermined voltages.

As shown in the first @, the device isolation region includes shield plate electrodes 4 and 5 made of n-type polysilicon.
It has an IS structure, and a predetermined voltage v2 is applied to the electrode 4, and a predetermined voltage V□ is applied to the electrode 5. The MIS structure allows a p-type semiconductor region and an n
Since it is possible to prevent the shaped semiconductor region from forming the inversion layer 6, the oxide film 3 can be made as thin as several hundred angstroms or less, so that the total dose resistance against radiation can be improved.

In addition, in the configuration shown in FIG. 1, a semiconductor element formation region 2 of n-type silicon and a semiconductor element formation region 1 of p-type silicon are used.
A trench is formed to include the boundary of the trench, a silicon oxide film 8 is formed as an insulating film on the inner wall surface of the trench, and the inside of the silicon oxide film 8 is filled with n-type polysilicon 9 to form an n-type polysilicon. It is electrically connected to a silicon shield plate electrode 5, and a predetermined voltage V□ is applied thereto. In this case, the latch-up problem caused by high-energy heavy particle irradiation can be solved by a parasitic lateral npn transistor formed by the n+ diffusion layer 12, the p-type silicon semiconductor element formation region 1, and the n-type silicon semiconductor element formation region 2. , the p+ diffusion layer 13, the n-type silicon semiconductor element formation region 2+, and the parasitic vertical pnp transistor formed in the p-type silicon semiconductor element formation region 1 are blocked by the groove, so that the positive Feedback action is prevented and latch-up resistance can be improved.

Furthermore, in the configuration of FIG. 1, an n-type diffusion layer 11 formed around the opening of the trench in the n-type silicon semiconductor element formation region 2 and a trench opening in the p-type silicon semiconductor element formation region 1 are formed. The n-type diffusion layer 10 formed around the opening constitutes the conductive electrode 9 of the MIS structure on the inner surface of the trench and the element isolation region on the n-type silicon semiconductor element formation region 2. It is electrically connected to a silicon shield plate electrode 5, and a predetermined voltage v1 is applied thereto. In this embodiment, the n+ diffusion layers 10 and 11 are made of n-type polysilicon without adding any special process such as ion implantation. That is, if a part of the gate oxide film 3 in a predetermined region is removed before forming the shield plate electrode 5, the process of forming the source/drain layer, for example, can be performed after forming the shield plate electrode 5. Through the heat treatment process, n-type impurities are diffused from the n-type polysilicon of the shield plate electrode 5 into the semiconductor element forming regions 1 and 2. By having the n+ diffusion layers 10 and 11, the n1 diffusion layers 10 and 11, the n-type semiconductor element formation region 2, and the conductive electrode 9 have the same potential, so that the conductive electrode 9 and the n
Since no voltage difference occurs between the oxide film 8 sandwiched between the + diffusion layer 10 and the conductive electrode 9 and the oxide film 8 sandwiched between the n-type silicon region 2 and the n+ diffusion layer 11, the insulation resistance of the oxide film in this part is reduced. problems caused by this will be prevented. In addition, positive charges are generated in the oxide film 8 by radiation irradiation such as electron beams, and if an inversion layer is formed around the groove in the p-type semiconductor element forming region 1 due to this charge, this inversion layer Since the n+ diffusion layer 10 in the p-type semiconductor element formation region 1 has the same potential, there is no potential difference between the oxide film 8 sandwiched between the inversion layer and the conductive electrode 9, so the insulation of the oxide film in this part Problems due to resistance are also prevented.

FIG. 2 is a sectional view showing a second embodiment of the invention.

In FIG. 2, 14 is a p-type low resistance silicon substrate;
5 is a p-type epitaxial silicon layer.

This embodiment is a case where the present invention is applied to a p-type epitaxial layer grown on a p++-type substrate as a semiconductor element formation region. In this case, the parasitic resistance is reduced due to the effect of the low resistance substrate 14, and this, together with the trench isolation effect described in the first embodiment, further improves the latch-up resistance. This improvement effect depends on the depth of the groove, and considering the diffusion of impurities from the resistance substrate 14 to the epitaxial growth layer 15 due to heat treatment during the process, the depth of the groove should be at least 40% deeper than the thickness of the epitaxial growth layer. It is necessary to.

FIG. 3 is a sectional view showing a third embodiment of the present invention. In the configuration of this embodiment, the n+ diffusion layer 1 in FIG.
0 is omitted. In other words, if there is no problem with the breakdown voltage of the oxide film 8 on the inner wall of the groove, the n+ diffusion layer 10 in FIG.
can be omitted as shown in FIG. 3, thereby making it possible to form a high-density integrated circuit.

FIG. 4 is a sectional view showing a fourth embodiment of the present invention. Up to now, the groove, which has an oxide film 8 on its inner wall and is filled with n-type polysilicon 9, has been arranged so as to include the boundary between the p-type silicon semiconductor element formation region 1 and the n-type silicon semiconductor element formation region 2. However, in Fig. 4, it is further placed under the other shield plate electrode, and the n inside the groove is
The type polysilicon electrode 9 is electrically connected to the n-type polysilicon shield plate electrode 4, and a predetermined voltage v2 is applied thereto. In this way, the latch-up resistance is further improved by frequently using trench isolation. Also, the fourth
As shown in the figure, in this embodiment as well, such groove separation is provided below the shield plate electrode 5 in the n-type silicon semiconductor element formation region 2, and the conductive electrode 9 is connected to the shield plate electrode 5. Needless to say, this also improves the latch-up resistance since it is electrically connected to the terminal and a predetermined voltage V is applied.

Although the embodiments of the present invention have been shown in the structure using an n-well, it goes without saying that the present invention can also be implemented in a structure using a p-well or a structure using both wells. Furthermore, the low resistance semiconductor region 14 may be of n-type or p-type.
The present invention can also be carried out in this form. Furthermore, the materials used for the gate electrode and shield plate electrode of the MOSFET are designed to reduce resistance.

It is also possible to have a so-called polycide structure in which a metal material is bonded onto polysilicon.

〔Effect of the invention〕

As explained above, according to the present invention, by providing the shield plate electrode, the oxide film can be made thinner, the total dose resistance due to radiation irradiation can be improved, and the grooves in the element isolation region can be made thinner. By providing this, latch-up resistance can be improved.

In addition, a portion of the gate oxide film on the surface of the semiconductor element formation region around the groove is removed, and impurities are diffused from the shield plate electrode member to form a high impurity concentration layer on the surface of the semiconductor element formation region. The resistance of the oxide film inside the trench can be improved.

Furthermore, since the conductivity types of the shield plate electrode and the gate electrode are the same, the process of introducing impurities into the electrode material is simplified.

[Brief explanation of drawings]

1 to 4 are cross-sectional views showing embodiments of the present invention, respectively. 1...p-type silicon semiconductor element formation region 2...n
Semiconductor element formation region 3 of type silicon...gate oxide film 4.5...shield plate electrode of n-type polysilicon 6.7...gate electrode 8 of n-type polysilicon...silicon oxide film 9 ...N-type polysilicon conductive electrode 10.11.12- n+ diffusion layer 13...P+ diffusion layer

Claims (1)

[Claims] In a complementary MIS semiconductor integrated circuit, a second MIS structure formed on a semiconductor element formation region of a first conductivity type
a gate electrode of a conductivity type, and a shield plate of a second conductivity type of the MIS structure formed in an element isolation region on the semiconductor element formation region of the first conductivity type and to which a first predetermined voltage is applied. an electrode, a gate electrode of a second conductivity type of the MIS structure formed on the semiconductor element formation region of the second conductivity type, and an element isolation region formed on the semiconductor element formation region of the second conductivity type. , and a second conductivity type shield plate electrode of the MIS structure to which a second predetermined voltage is applied, a groove formed in a predetermined portion of the element isolation region in the semiconductor element formation region, and an insulating film provided on a wall surface; an MI disposed inside the insulating film and electrically connected to the second conductivity type shield plate electrode;
A groove electrode of a second conductivity type having an S structure and a predetermined area formed in at least one of the semiconductor element formation regions of the first conductivity type and the second conductivity type and around the opening of the groove. and a diffusion layer of a second conductivity type formed in at least one of the semiconductor element formation regions of the first conductivity type and the second conductivity type; A complementary MIS semiconductor integrated circuit having a structure in which a shield plate electrode of a second conductivity type is electrically connected.