JPS61251382A - Solid-state image pickup device for still photographing - Google Patents

Abstract

PURPOSE:To effectively remove blooming without lowering an optical opening efficiency of an element by making a transistor means conductive a little on exposing a photosensitive means, and disposing an electric charge control means for eliminating an excessive electric charge generated on the photosensitive means. CONSTITUTION:From a control circuit not shown, control signals A, B, C are supplied to terminals, 56, 42, 40 at a predetermined timing and pulses HP and VP are fed to terminals 34 and 46. When a light incident to a photosensitive cell 10a is too strong, in a photodiode 2 of the cell 10a, an excessive photoelectrons are generated, a level of a cathode is lowered to a direction of negative to make conductive the diode 12. At this time, an insulating gate field effect transistor IGFET 14 is a little conductive, flows in the diode 12 through an IGFET 38 and the IGFET 14 of the cell 10a from a power source Vref of a terminal 58. Thereby, the excessive electric charge is connected again and eliminated and the generation of blooming is prevented in the reproduced image.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device for still photography having a so-called MO9 structure, which reads out a signal current according to photocharges accumulated in a photosensitive cell.

l】J-maru! Conventionally, solid-state imaging devices have been developed mainly for shooting movies. Therefore, the photocharges that overflow from the photosensitive cell due to irradiation with relatively strong incident light cause blooming in the reproduced image of the video signal read out from the element, so it is necessary to take steps such as discharging this at the same time as it occurs. For this purpose, a charge discharge means for immediately discharging the overflow charge has been spatially arranged with respect to the photosensitive cell. For example, an overflow drain is disposed parallel to the charge readout line from the photosensitive cell array, Some devices were constructed so that photocharges overflowing from the photosensitive cell were discharged into this cell. Since the capacitance of this drain can be designed according to the allowable intensity of the incident light, overflow charges can be effectively discharged, and blooming can be sufficiently suppressed for movie use. However, since the drain must be spatially placed in the plane of the photosensitive cell array.

The drawback is that the optical aperture ratio of the photosensitive area is low and the pixel density is low.

Another measure against blooming is to form a well of the opposite conductivity type in the substrate of the device to drain excess charge to the junction region between the substrate and the well. However, this measure has the drawback that overflow charges may leak to the video signal readout line through the inside of the well, and blooming cannot be completely eliminated.

Objective: The present invention eliminates the drawbacks of the prior art and provides a solid-state imaging device for still photography that can effectively eliminate blooming without reducing the optical aperture ratio of the element or complicating the element structure. The purpose is to

According to the present invention, a photosensitive cell having a photosensitive means for generating and accumulating charges corresponding to incident light and a 10S transistor means for reading out a signal current corresponding to the charges from the photosensitive means is mounted on a semiconductor substrate. The solid-state imaging device for still photography, which is formed on one main surface of the photosensitive device, includes charge control means for slightly conducting the transistor means to eliminate excess charge generated in the photosensitive device during exposure of the photosensitive device. .

11! Next, embodiments of a solid-state imaging device for still photography according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, in a specific embodiment of the solid-state imaging device for still photography according to the present invention, photosensitive cells 10 forming a video signal corresponding to one pixel are arranged in a row and column direction, forming a two-dimensional photosensitive cell array. It consists of In this figure, to avoid complicating the diagram, one photosensitive cell for three horizontal rows and three vertical columns is shown.
Although only 0 is shown, in reality, a large number of photosensitive cells 10 are arranged in both directions so as to obtain sufficient resolution for image reproduction.

Each photosensitive cell 10 includes a photodiode 12 as a photosensitive region that generates a photocharge corresponding to incident light and accumulates it in a junction region thereof, and an insulated gate as a readout gate for reading out a signal current corresponding to the accumulated charge. The cathode 18 of the photodiode 12, including a field effect transistor (ICFET) 14, is connected to the readout signal line 1B through the source-drain path of the IGFET 14 to each ICF in its vertical column.
ET 14 are commonly connected. Anode 20 of diode 12 is connected to a reference potential. Also, I
The gate electrode of GFET 14 is connected to each IGF in its horizontal row.
It is commonly connected to the read drive line 22 for E714.

Referring to FIG. 2, one cell 10 of a photosensitive cell array
The cross-sectional structure of is conceptually shown. In this example, two n medium regions 102 and 104 are formed on one main surface of a p-type silicon substrate 100. One of the n◆ spheres 102 forms a p-n junction with the p-type substrate 100, and forms a photosensitive region, that is, a photodiode 12, which generates and accumulates photoelectric charges in response to the incident light 10B. are doing.

A gate electrode 22 is provided on the substrate surface between both n0 regions 102 and 104 with an insulating layer 11σ of silicon dioxide interposed therebetween. The gate electrode 22 is made of monopolycrystalline silicon in this embodiment. These two n♦ regions 102 and 104. A MOS transistor or IGFET 14 is formed by the insulating layer 108 and the gate electrode 22. In this example, it is an IGFET of n-channel conductivity type. ! + region 102 functions as a source, and n♦ region 104 functions as a drain. The tray 7104 is
For example, it is connected to a video signal readout line 1B made of aluminum or the like.

As will be seen from now on, the photosensitive cell array of this embodiment is not provided with an overflow drain for draining excess charge or a well of a conductivity type opposite to that of the substrate, as seen in the prior art.

Returning to FIG. 1, the readout signal line 18 that commonly connects the source/drain paths of each photosensitive cell 10 in the vertical column is connected to the IGF
It is commonly connected to output line 28 through the source-drain path of ET 24. This output line 26 is.

It is pulled up to another reference voltage Vref through a resistor 28.

The gate 30 of each IGFET 24 is connected to each register stage of a horizontal shift register 32. The horizontal shift register 32 receives a single pulse H applied to an input terminal 34.
P designates a shift register that sequentially shifts each register stage in response to a drive clock HCLK at a terminal 36. This drive clock HCLK is given at the pixel frequency, and functions as a video signal readout drive circuit that selects readout lines in the horizontal direction at this speed and sequentially energizes the gates 24. terminal 3
A single pulse IP of B is provided at the horizontal scanning frequency from the control circuit 120 of FIG.

Read line 18 is also connected to terminal 58 reference voltage Vref through the source-drain path of IGFET 38. The gates 40 of the IGFETs 38 are commonly connected across each vertical column and are provided with a control signal C, described below, from a control circuit 120 shown in FIG.

A control line, ie, a horizontal selection line 22, commonly connects the gate electrodes of the IGFETs 14 of each photosensitive cell 10 in the horizontal row.
are connected to each register stage of vertical shift register 44 through the source and drain paths of IGFET 42. The vertical shift register 44 is a shift register in which a single pulse Vp applied to the input terminal 4B sequentially shifts each register stage in response to the drive clock VCLK of the terminal 48. This drive clock VCLK is.

It functions as a vertical column selection circuit that sequentially drives the selection lines 50 in the vertical direction at a horizontal scanning frequency and simultaneously energizes the gates 14 in the horizontal rows. A single pulse vP at terminal 46 is provided by control circuit 120 at the vertical scan frequency. The gates 52 of the IGFETs 42 are commonly connected across each horizontal row, and include a control circuit 12.
A signal B, which will be described later, is applied from 0 to 0.

Horizontal selection line 22 also connects the source of IGFET 54.
It is connected to a reference voltage Vcc through a drain path.

The gates 58 of the IGFETs 54 are commonly connected across each horizontal row, and are supplied with a signal A, which will be described later, from a control circuit 120.

These control signals A, B and C1 and pulse vP
Approximately HP is supplied from control circuit 120 (FIG. 3). The control circuit 120 receives at a terminal 122 a signal SR instructing photography obtained from, for example, a release button for opening an optical shutter, and outputs control signals A, B, and C to output terminals 56 and 52 at predetermined timing. and 40, respectively, and is a timing generation circuit that generates pulses IP and vP at terminals 34 and 46, respectively. The timing of this occurrence is shown in the waveform diagram of FIG.

The operation will be explained with reference to FIG. The symbols (A), CB) to (F) shown on the left side of the figure indicate signals appearing at positions ^ and B-F in the circuit shown in FIG. 1, respectively. Note that the scale of the vertical axis in the figure is not necessarily the same in each figure.

At time 11, the optical shutter is opened and the photosensitive cell array is exposed to light for a period T1. In synchronization with this, control circuit 1
The photographing signal SR is input to 2.

Therefore, the control circuit 120 generates the signal A at the terminal 5B at time t2. This signal A maintains the level Vcc t- in the idle state of the circuit, maintains the level Vl for a period approximately equal to the exposure period 〒l, and then remains at the ground level (
This is a signal that maintains Ov). This level V1ha, OV
It is advantageous to set the readout ICFET 14 to a level lower than about twice the gate threshold voltage VTH. The period during which level v1 is maintained, that is, time t2
The period from I5 to I5 does not necessarily have to match the exposure period TI.In short, it can be the same as the exposure period 〒1 or shorter, but if it is about the same as that, it will be useful for draining excess charge. It's advantageous.

Before time t1, signal A at level Vcc is applied to each ICFE.
Since it was given to the gate of T54, until then,
Each ICFET 54 is fully conductive so that the voltage V
cc was supplied to each selection line 22 (CD in the same figure)
, @No. A Luheruka V1 Nina! -, each IGFET
The resistance of the source-drain path 54 increases, thereby supplying each selection line 22 with a voltage at level v2, which is the voltage Vcc lowered by the voltage drop. This level v2 is
It is set approximately to the threshold value VTH of ICFET 14. This causes ICFET 14 to become slightly conductive. Conversely, the level v1 of signal A is.

10FE754 is insufficiently conductive, thereby causing the IC
The level is set to such a level that the FET 14 is slightly conductive. At this time, since signal B is not given, each IC
FET 42 is not conducting.

Almost in synchronization with the output of signal A at level Vl, time t
3 to I4, the control circuit 120 outputs the signal C to the terminal 40. This signal C applies the power supply voltage Vcc to IGFET 3B, which causes ICFET 38 to conduct.
As a result, voltage Vref is supplied to each signal read line 18. For example, if we take the upper leftmost photosensitive cell IQa in the photosensitive cell array shown in FIG.
Take. The period from time t3 to I4 in signal C does not necessarily have to match the exposure period 〒1.In short, it can be the same as the exposure period 〒1 or shorter, but as long as it is about the same. This is advantageous in draining excess charge.

In particular, if the control signals A and C are generated so that the fall time t4 of the signal C and the fall time t5 of the signal A coincide with the end of the exposure period TI, it is advantageous for the operation of discharging excess charge.

In this state, for example, if the light incident on the photosensitive cell lea is too strong, excess photoelectrons are generated in the photodiode 12 of that cell 10a, and the level of the cathode tends to decrease in the negative direction. The diode 12 then becomes conductive. On the other hand, since IGFI'T I4 is in a slightly conductive state as described above, the voltage 111Vre of the terminal 58 is
IGFET 38 from f and ICFET 1 of cell tea
4 into its diode 12. This causes the excess charges to recombine and disappear.

Such recombination of excess charges occurs once while signal C is energized or while IGFET 14 remains slightly conductive, ie, while signal A remains at level v1. Preferably, during the exposure period TI,
The ICF for each photosensitive cell IO is maintained at the level of signal A at Vt and the level of signal B at v2.
Since ET 14 is maintained in such a semi-conducting state,
Even if a surplus charge is generated in each cell IO, blooming is prevented from occurring in the reproduced video.

When the exposure period TI has elapsed, the control circuit 120
− Signals A and C are set to low level (Ov). For example, at time ↑4, signal C becomes low level, which causes the IC to
FET 38 shuts off. Further, at time t5, the signal A becomes low level, thereby cutting off the ICFET 54. Therefore, the gate 22 of the ICFET 14 also becomes ground level, and is also cut off.

Thereafter, from time t8, the reading operation of the video signal of each photosensitive cell 10 is started. Control circuit 120 brings signal B to a high level Vcc and generates pulses vP and HP at outputs 34 and 4B, respectively. Thereupon, the shift registers 32 and 44 shift sequentially, and the video signals are sequentially read out by raster scanning the photosensitive cell array.

For example, regarding the photosensitive cell lOa, the selection line 22 in the horizontal row is driven at time t7, and at a certain time t8 during the driving period, the gate 3 of the ICFET 24 in the vertical row is driven.
0 is driven. Therefore, a current of level 140 corresponding to the photocharge accumulated in the photodiode 12 of the cell 10a flows from the power supply Vref to the resistor 28 and the IGF in the vertical column.
flows into diode 12 through the source-drain path of ET 24 and ICFET 14 of cell 10a;
Changes in the voltage of the resistor 28 due to this current are sensed from the output terminal 2B as a video signal by other circuits.

In this way, reading is carried out sequentially from the cells 10 in the horizontal row, and by sequentially reading out the cells 10 in the other horizontal rows, the rask scanning video signal of the l field is output 26.
output in series.

As can be seen from the above explanation, the video signal readout line 18
functions as an excess charge discharge line, ie, an overflow drain, during the exposure period T1. Of course, during the subsequent video signal readout period, it functions as a signal readout line.

In this way, in this embodiment, by taking advantage of the operational characteristics of the imaging device for use in still photography, surplus charges can be effectively eliminated without the need to specifically provide overflow drains or wells in the photosensitive cell array. In this way, since no overflow drain or well is provided, the optical aperture ratio of the device can be increased and the device structure can be simplified. Therefore, blooming can be effectively removed without reducing the optical aperture ratio of the element or complicating the element structure.

As described above, the present invention effectively eliminates excess charge without providing an overflow drain or well in the photosensitive cell array. Therefore, blooming can be effectively removed without reducing the optical aperture ratio of the element or complicating the element structure.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit block diagram showing a specific embodiment of a solid-state imaging device for still photography according to the present invention, and FIG. 2 is a cross-sectional diagram conceptually showing the cross-sectional structure of one cell of the photosensitive cell array shown in FIG. 3 is a block diagram showing an example of a control circuit that generates a signal to control the circuit of the embodiment shown in FIG. 1, and FIG. 4 shows signal waveforms appearing in each part of the embodiment shown in FIG. 1. FIG. io, photosensitive cell 12, photodiode 14, 38, 54. 1CFET 32.44. , , Shift register 120 , , Control circuit Patent applicant Fuji Photo Film Co., Ltd. Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A photosensitive cell having photosensitive means for generating and accumulating charges according to incident light and MOS transistor means for reading out a signal current corresponding to the charges from the photosensitive means is a semiconductor substrate. A solid-state imaging device for still photography, which is formed on one main surface of the photosensitive device, is configured to: When the photosensitive device is exposed to light, the transistor device is made slightly conductive to eliminate excess charge generated in the photosensitive device. 1. A solid-state imaging device for still photography, comprising a charge control means. 2. In the device according to claim 1, the charge control means includes: voltage application means for applying a predetermined voltage to the gate of the transistor means; and supplying current to a signal current output path of the transistor means. the predetermined voltage is set to a value approximately equal to the gate threshold voltage of the transistor means, and when the photosensitive means is exposed to light, the predetermined voltage is applied from the voltage application means to the gate of the transistor means. 1. A solid-state imaging device for still photography, characterized in that a voltage of 1 is applied thereto, thereby enabling current to be supplied from the current supply means to the photosensitive cell means through the transistor means. 3. The device according to claim 2, wherein the photosensitive cells are arranged in a row and column direction to form a two-dimensional array, and the charge control means has gates of the transistor means commonly corresponding to each horizontal row. A solid state for still photography, characterized in that it comprises vertical shift register means connected to a register stage for each vertical column, and horizontal shift register means, the output path of the transistor means being commonly connected for each vertical column to a corresponding register stage. Imaging device.