JPS61236284A - Charcter signal receiver - Google Patents

Abstract

PURPOSE:To decide the switching of a channel by comparing the contents of a code memory in an initial state with those when a vertical synchronous signal is not detected for a certain time and then comparing the position and frequency of superposition of a character signal. CONSTITUTION:While a character signal superposition section gate signal PG is at a low level, the output of an address generating means 25 and the output of a latch circuit 24 are applied to the code memory 32 and an arithmetic control means 30 is not connected. While the PG is at a high level, the output of a data switching circuit 28 and the output of an address switching circuit 29 are switched over to the side of the arithmetic control means 30, so the contents of the code memory 32 can be read in. When a character signal is transmitted, the latch circuit sends out a signal, which is written in the code memory 32. Then when a channel is switched and the character signal is received, the latch circuit 24 outputs the signal and the contents of the code memory 32 are changed. The arithmetic control means 30 reads the contents out of the code memory 32 and they are compared with the contents of an internal memory, so that a channel switching detection signal is outputted from an output terminal 33 since the contents are not coincident.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a character signal receiving device.

Background of the Invention Teletext broadcasting is a broadcasting system that transmits image information such as weather forecasts, news, stock information, etc. consisting of nine characters and graphics using digital data signals. The character signal is transmitted during the tenth horizontal scanning period (10) of the vertical blanking period of the television signal.
H to 21H4) In the next field, 273H to 2
It is superimposed by 84H. Character signals are transmitted in data packets each having one horizontal scanning line as a unit, as shown in FIG. In Figure 6, (a) is the horizontal synchronization signal, (b)
(C) is a data packet consisting of 37 bytes. Of data packet 3, (2) is the first 3 bytes of the synchronization part, and (E) is the remaining 34 bytes of the data part. Furthermore, in the synchronization section 4, (to) is "1010
The two bytes of ``101o1o101010'' are called clock run-in (CRI) and are used for bit synchronization.

Generally, when a teletext receiving device receives a text signal, it extracts a program number from the program being transmitted and stores the extracted program number in a program number memory of the receiving device. Therefore, by displaying the data stored in this program number memory on the screen, the recipient can
You can select the teletext program currently being transmitted.

However, once the data is stored in the program number memory, it is saved until the receiving device is turned off, so if you switch from one teletext channel to another, the previous The teletext program number of the channel remains in the program number memory. For this reason,
After switching channels, the receiver must either turn off the power to the receiver or erase the contents of the program number memory, which is inconvenient in terms of operation.

Conventionally, the detection output of the framing code of the character signal is monitored, and when the disappearance of the detection output is detected for a predetermined period of time,
A method has been proposed to clear the program number memory (
For example, Japanese Patent Laid-Open No. 137376/1983). FIG. 6 shows the main part configuration of a character signal receiving device according to an embodiment of the conventional example. In the figure, a framing code detection pulse (FCD) is connected to one input of a Nant gate circuit 11 via a framing code detection pulse input terminal 1o. Further, the signal gate pulse (CG) is connected to the other input of the Nant gate circuit 11 via the signal gate pulse input terminal 12, and the signal gate pulse (CG) is connected to the other input of the Nant gate circuit 11.
It is also connected to input 3. The output of the Nant gate circuit 11 is connected to the reset input of the counter 13 and also to the reset input of the JK-FF 14. The output of the counter 13 is connected to the clock input of the JK-FF 14, and a clear output signal (
SD) is taken out via the clear output signal terminal 16.

Note that FIG. 7 shows signals of each circuit section in FIG. 6. A clear output signal is produced some time after the framing code detection has disappeared.

Problems to be Solved by the Invention In such conventional circuits, when switching to another channel, if a teletext service is being performed on the switched channel, the framing code detection output is generated as is, and the program number memory is may not be cleared.

The present invention has been made in view of the above points, and provides a teletext receiving device having a function of clearing the program number memory when switching to another channel, regardless of the presence or absence of the teletext service. It is something.

Means for Solving the Problems The present invention provides code detection means for detecting a specific code of a character signal superimposed on a horizontal scanning period, a code memory in which the output of the code detection means is written, and a code detection means for detecting a specific code of a character signal superimposed on a horizontal scanning period; address generating means for counting; means for writing the output of the soot detecting means into the code memory in correspondence with the address set by the output of the address generating means; and means for writing the output of the soot detecting means into the code memory in an initial state. The character signal receiving device has arithmetic control means for reading the data written in the code memory if a vertical synchronizing signal is not detected for a predetermined period of time.

By comparing the contents of the code memory in the initial state with the contents of the code memory at the time when no vertical synchronization signal has been detected for a certain period of time, the channel can be determined by comparing the superimposition position and number of character signals. Determine whether it has been switched.

Embodiment FIG. 1 shows an embodiment of the present invention. In the figure, a clock signal synchronized with a character signal is supplied to the clock input of the code detection stage 2o via a clock signal input terminal 21, and a character signal is supplied to the character signal input of the code detection stage 20. A character signal is supplied via the input terminal 22. The horizontal synchronization pulse is supplied via the horizontal synchronization pulse input terminal 23 to the reset input of the latch circuit 24 and to the count input of the address generation means 25. The vertical synchronizing pulse is supplied to the reset input of the address generating means 25 via the vertical synchronizing pulse input terminal 26, and also to the input of the vertical synchronizing signal missing detection stage 27. The output of the code detection output stage 2o is connected to the input of the latch circuit 24. The output of the latch circuit 24 is connected to one input of a data switching circuit 28. The output of the address generating means 26 is connected to one input of an address switching circuit 29. The other input of the data switching circuit 28 is connected to the data input of the arithmetic control means 3o, and the other input of the address switching circuit 29 is connected to the address output of the arithmetic control means 3o. The character signal (superimposed section gate signal (PG)) is
The signal is supplied to the other input of the data switching circuit 28 via the PG input terminal 31, and is also supplied to the other input of the address switching circuit 29. The data input of the code memory 32 is connected to the output of the data switching circuit 28, and the address input of the code memory 32 is connected to the output of the address switching circuit 29. The output of the vertical synchronization signal loss detection stage 27 is transmitted to the arithmetic control means 3o.
The channel switching detection signal is outputted via the channel switching detection signal output terminal 33.

The operation of this embodiment will be explained below with reference to FIG. In the figure, (G) is supplied through the PG input terminal 31, and (S) is the horizontal synchronizing pulse input terminal 2.
3 is a waveform diagram of a vertical synchronizing pulse supplied through the vertical synchronizing pulse input terminal 26. During the period when pG is at a low level, the output of the address generation means 26 and the output of the latch circuit 24 are applied to the code memory 32, and the code memory 32 is not connected to the arithmetic control means 30. During the period when PG is at a high level, the output of the data switching circuit 28 and the output of the address switching circuit 29 are switched to the arithmetic control means 3o side, so that this arithmetic control means can read the contents of the code memory 32. is possible.

If a character signal is sent in a state like (now),
The latch circuit 24 outputs a signal (a), this output signal is added to the data input of the code memory 32, and the contents as shown in FIG. 3 (2L) are stored in the code memory 32.
written to. Furthermore, while the PG is at a high level, the arithmetic control means 3o reads the contents of the code memory 32 and stores them in the internal memory.

Next, when the channel is switched and the character signal (7) is received, the latch circuit 24 outputs the signal ψ), and the contents of the code memory 32 are changed as shown in FIG. 3(b). change in state. Further, the output of the vertical synchronization signal loss detection stage 27 is applied to the arithmetic control means 3o, and this arithmetic control means 3o reads out the contents of the code memory 32, and reads out the contents of the code memory 32 which have been stored in the internal memory in advance.
Compare with the contents of In this case, since the contents do not match, it is determined that the channel has been switched, and the arithmetic control means 30 outputs a channel switching detection signal from the channel switching detection signal output terminal 33. FIG. 4 shows the procedure of the calculation control means 30 in this embodiment described above.

Effects of the Invention According to the present invention, when switching from a channel with teletext service to a channel without teletext service, even if teletext service is being performed on the switched channel, the text signal cannot be changed. If there is a change in the superimposition position or the number of superimpositions, channel switching is reliably detected. In particular, in an adapter-type teletext receiver that uses a 21-pin multi-connector specified by the Japan Electronics Industry Association, it is not possible to send a channel switching signal. Extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a character signal receiving device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the circuit operation in FIG. 1, and FIG. 3 is a diagram showing the contents of the code memory in FIG. FIG. 4 is a flowchart showing the operation in FIG. 1, FIG. 6 is a configuration diagram of a character signal, FIG. 6 is a circuit configuration diagram of a conventional character signal receiving device, and FIG. 7 is a timing chart for explaining the circuit operation in FIG. 6. FIG. 3...Data packet, 6...Clock run-in, 7...Framing code, 2o
......Code detection stage, 21...Clock signal input terminal, 22...Character signal input terminal,
23...--Horizontal synchronization pass/L' pass input terminal, 24...
... Latch circuit, 25 ... Address generation means, 26 ... Vertical synchronization pulse input terminal, 27
...Vertical synchronization signal missing detection stage, 28...
...Data switching circuit, 29...Address switching circuit, 3゜...Arithmetic control means, 31...
PG input terminal, 32... Code memo, 33.
...Channel switching detection signal output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 (Q) (b) Figure 4 7th Figure 5 Pigeon

Claims (1)

[Claims] code detection means for detecting a specific code of a character signal superimposed on a horizontal scanning period during a vertical blanking period of a television signal; a code memory in which the output of the code detection means is written; and a code memory for counting the horizontal scanning period. address generation means;
means for writing the output of the code detection means into the code memory with respect to the address set by the output of the address generation means; and a vertical synchronization signal for outputting a missing signal if the vertical synchronization signal cannot be detected for a certain period of time. dropout detection means; and arithmetic control means for reading first data written in the code memory in an initial state and reading second data written in the code memory based on the output of the vertical synchronization signal dropout detection means. A character signal receiving device comprising: a character signal receiving device that determines whether or not a channel through which the character signal is being transmitted has been switched by comparing the first data and the second data.