JPH031878B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a mask pulse generation circuit that is effective for use in systems that receive and reproduce television signals containing text information and the like. In a teletext receiver, image information such as characters and figures is transmitted by digital signals, which are sampled by data sampling pulses, and the data necessary for display is stored in a pattern memory and assembled. The contents of the pattern memory are read out in accordance with the synchronization signal of the display device. In teletext broadcasting using television signals, teletext packets are inserted into the vertical retrace period for transmission. Teletext packets include a clock line-in signal, which will be explained in detail later.
Contains framing codes, etc., and digital data to be transmitted. On the receiving side, the data sampling pulse is first synchronized with the clock run-in signal, and data following the clock run-in signal is sampled and temporarily stored in a buffer circuit. The sampled data also includes a framing code, which is used as an indicator to indicate the beginning of data, and when detected, subsequent data begins to be stored in the buffer circuit. As mentioned above, the clock run-in signal and the data sampling pulse are processed in the sampling pulse generation circuit so that they are synchronized, but before that, the clock run-in signal is accurately masked and extracted from the teletext packet. It is important to be taken. Further, the framing code is a predetermined code, and its position is detected by a framing code detection circuit. Therefore, when extracting a framing code from a teletext packet, a mask pulse that covers approximately the position of the framing code is generated at the timing when the framing code is likely to be present, and then introduced into the framing code detection circuit. There is. As mentioned above, when receiving teletext broadcasting,
It is necessary to generate multiple mask pulses to extract the clock run-in signal and framing code. Conventionally, this type of mask pulse is based on a horizontal synchronization signal. for example,
A horizontal synchronizing signal is applied to a monostable multivibrator circuit to create a constant width pulse, which is used as a counter reset signal. This counter counts clock signals, and when the count reaches a certain value, a logic circuit detects this and outputs a mask pulse from the logic circuit. According to this method, when adjusting the generation timing of the mask pulse, it is necessary to adjust the time constant of the monostable multivibrator circuit and shift the reset timing of the counter. However, the insertion position of the teletext packet with respect to the horizontal synchronization signal is not necessarily a fixed position, but may fluctuate depending on various factors such as circuit conditions. For this reason, when mask pulses are generated by the above-mentioned means, there are disadvantages in that data cannot be obtained accurately and the mask pulse generation position must be adjusted frequently. This invention was made in order to deal with the above-mentioned situation, and even if the superimposition position of teletext packets fluctuates within the horizontal scanning period, the clock run-in signal or the pulse for masking the framing code in the teletext packets An object of the present invention is to provide a mask pulse generation circuit that generates a mask pulse by following the superimposed position of a teletext packet. Embodiments of the present invention will be described below with reference to the drawings. First, to explain the format of the television signal handled in teletext broadcasting, the format of the television signal handled in teletext broadcasting is set as shown in FIG. FIGS. 1a and 1b show vertical blanking period portions of the first field and the next field of a composite video signal, and V is a vertical synchronizing signal. Teletext packets 1 and 2 are set at the rear of this vertical retrace period, for example, at the 20th H (H: one horizontal period) after the end of the previous field. The format of this teletext packet is set as shown in FIG. 1c. H is a horizontal synchronization signal, and 5 is a color burst. The teletext packet 2 is formed by a header section 6 and an information section 7. This teletext packet 2
The details are as shown in FIG. 1d. That is, the header section 6 receives the clock run-in signal CRI and the framing code.
It consists of FC, identification code IDC, etc. The types of teletext packets 2 include control packets, color code packets, and pattern data packets. The information part of the control packet contains
Contains data indicating what kind of content will be sent from now on, for example, the first
Program code (program number) as shown in Figure d
Contains PC1, PC2, page numbers PA1, PA2, etc. In addition, the information section of the color code packet and pattern data packet contains color data and pattern data (D-D), as shown in Figure 1e.
etc. are included. In the header section 6, the clock run-in signal
The CRI is a signal for adjusting the phase of the clock pulse necessary for sampling the data in the teletext packet. The framing code FC is a code that indicates the beginning of data. The identification eye code IDC indicates the display format or transmission signal format, and is a code for identifying when a mixture of programs in various display modes is being transmitted. The teletext packets described above are processed, for example, by a system as shown in FIG. 1
Reference numeral 1 denotes an input terminal to which an intermediate frequency of a teletext television signal is input. The signal applied to this input terminal is subjected to image detection by the image detection circuit 12. The video-detected composite video signal is input to a waveform shaping circuit 13 that extracts teletext packets and performs waveform shaping. Further, the composite video signal is input to a synchronization separation circuit 21 that separates a vertical synchronization signal V and a horizontal synchronization signal H. The vertical synchronization signal V and horizontal synchronization signal H separated from the synchronization separation circuit 21 are sent to the vertical position counter 2.
2 is input. This vertical position counter 22 is
It is reset by the vertical synchronizing signal V, and the horizontal synchronizing signal H
By counting the numbers, it is possible to obtain a sampling pulse corresponding to the position where the teletext packet is superimposed. The sampling pulse obtained by the vertical counter 22 is input to the waveform shaping circuit 13. As a result, the waveform shaping circuit 13 extracts the teletext packet described in FIG. 1 and shapes its waveform. The output obtained from this waveform shaping circuit 13 is input to a sampling circuit 14 and also to a clock run-in signal detection circuit 16. The clock run-in signal detection circuit 16 extracts the clock run-in signal CRI shown in FIG.
This clock pulse generating circuit 17 has a function of generating continuous clock pulses in synchronization with the clock run-in signal. Continuous clock pulses output from the clock pulse generating circuit 17 are input to the sampling circuit 14 and used as data sampling pulses. In the sampling circuit 14, various types of data as shown in FIG. The output of the sampling circuit 14 is also input to a framing code detection circuit 18. This framing code detection circuit 18 is
This is detected by a comparison operation between a predetermined framing code and an input code, and a point where the codes completely match is detected and the starting part of the data in the buffer memory is set.
Framing code detection circuit 18 is driven by clock pulses from horizontal position counter 23, for example. The horizontal position counter 23 is reset by the horizontal synchronization signal H from the synchronization separation circuit 21, and counts the clock pulses from the clock pulse generation circuit 17. This horizontal position counter 2
The count information of 3 is also added to the address circuit 24. Further, this address circuit 24 includes:
The previous vertical synchronization signal is also input. This address circuit 24 can generate address data regarding the horizontal and vertical directions of the image obtained by the currently input composite video signal. As mentioned above, when a teletext packet arrives, the buffer memory 15 stores its contents. The data stored in this buffer memory 15 is processed by a microcomputer. Central processing unit (hereinafter referred to as CPU) 30
decodes the data contents of the buffer memory 15. For example, what is the data format?
What the program is like. For example, a case will be explained in which it is desired to display a weather forecast as a teletext broadcast. If it is desired to display the weather forecast, a command signal for processing the weather forecast data can be input by operating the keyboard 40. The weather forecast program is specified by the program code shown in FIG. For example, program code
Assuming that the data from PC1 is sending a weather forecast, this program code PC1 is processed by the CPU 30. As a result, if the data of this program code PC1 matches the data specified from the keyboard 40, it is determined that the data in the buffer memory 15 is data for a weather forecast. A command signal for reproducing the weather forecast specified from the keyboard 35 is stored in a random access memory (hereinafter referred to as RAM). The weather forecast pattern data read out from the buffer memory 15 is finally stored in the pattern memory 33 as character data and symbol data.
The color data is stored in color memory 34. The data read from the buffer memory 15 is itself stored in the pattern memory 33 as character data and symbol data, but if the transmission method is a code transmission method, the data read from the buffer memory 15 is decoded and read. Predetermined character data, that is, characters, symbols, and graphic data may be read out from the only memory (hereinafter referred to as ROM) and stored in the pattern memory 33 or the like. Therefore, furthermore,
A character ROM 39 is prepared. As mentioned above, character, symbol, and graphic data are stored in the pattern memory 33 based on the data derived from the buffer memory 15, but only once a teletext packet in a vertical period is extracted. Not enough data can be obtained for character display. Therefore, each time there is a vertical synchronization period and each time a desired program is detected, the data is sequentially stored in the pattern memory 33. When data is stored in the pattern memory 33 and color memory 34, address designation data specifying the storage address may be input together with the data to determine in which address the data is stored. When the data stored in the pattern memory 33 and color memory 34 are read out and displayed, the data in the pattern memory 33 is sent to the pattern decoder 35, and the data in the color memory 34 is sent to the DC data via the color decoder 36. is converted to
The output interface 37 synthesizes the signals. Then, it is combined with the composite video signal in a combining circuit 38. Pattern memory 33, color memory 34
The data read timing is based on a command signal from the CPU 30. The CPU 30 constantly decodes address data (corresponding to the current screen beam irradiation position) input from the address circuit 24. If this address data matches the desired display specification data set in RAM32,
Read signals corresponding to these address data are applied to the pattern memory 33 and color memory 34. The display data is included in a program stored in the RAM 32, and various display formats can be set according to changes in this display designation data and program switching. The above-mentioned teletext broadcasting signal is processed, and this device is characterized by a means for generating mask pulses for accurately extracting and processing clock line-in signals and framing codes. The characteristic components will be explained below. For the sake of simplicity, a mask pulse generating section for the clock run-in signal will now be described with reference to FIG. In FIG. 3, 41 is the synchronous separation circuit 2
The horizontal synchronizing signal H separated by 1 is added to the counter as a reset signal. This counter 41 is reset by the horizontal synchronizing signal H and counts the data sampling pulse DSP. The data sampling pulse DSP is applied from the previous clock pulse generation circuit 17. The count output of the counter 41 is input to the logic array 42.
This logic array 42 is set so that an output pulse is generated when the count value of the counter 41 reaches a specific value. From the first output terminal 42a of this logic array 42, an output with a pulse width that covers the clock run-in signal is obtained, and its generation position (timing) is predicted to be during the clock run-in signal period. It is set in the correct position. (Hereinafter, the pulse generated at this output terminal 42a will be referred to as the original clock run-in signal mask pulse.
It is called RCRI. ) Also, the logic array 4
A mask pulse corresponding to the position of the framing code is output from the second output terminal 42b of 2, and is a pulse that sufficiently covers the movement range of the framing code as the superimposition position of the teletext packet moves. Set to width. (Hereinafter, the pulse generated at the output terminal 42b will be referred to as the reference mask pulse RFC.) The original clock run-in signal mask pulse and the reference mask pulse can be freely set at their generation positions by changing the logic configuration of the logic array 42. can be changed to On the other hand, the input terminal 43 receives a waveform-shaped serial character multiplex signal. This character multiplex signal is input to a sampling circuit 14 composed of a shift register and converted from serial to parallel. In this sampling circuit 14,
The aforementioned data sampling pulse is used as the clock. The output of this sampling circuit 14 is then transmitted to the framing code detection circuit 1.
8 is input. This framing code detection circuit 18 detects that the data output from the sampling circuit 14 is a framing code (for example, 11100101).
Framing code detection pulse when
It is used to obtain FDP, and the code for data comparison is written in advance. Next, 44 is an AND circuit which inputs the reference mask pulse RFC and the data sampling pulse described above, performs a logical product, and applies an output pulse to the clock input terminal of the shift register 45.
This shift register 45 uses the framing code detection pulse FDP as a data input, and uses the output pulse of the AND circuit 44 as a clock input. The transfer output of this shift register 45 is
The signal is input to the output conversion circuit 46. This output conversion circuit 46 uses a ROM, and a conversion code is written in advance so as to generate an output corresponding to the output of the shift register 45. The converted output of the output conversion circuit 46 is input to a latch circuit 47. This latch circuit 47 is connected to an AND circuit 48 which takes a logical product of the latch pulse from the input terminal 49 and one output of the output conversion circuit 46.
The conversion output of the output conversion circuit 46 is latched by the output of the output conversion circuit 46. Each bit output latched by the latch circuit 47 is applied to one input terminal of each AND circuit 51a to 51h constituting the data selector 50. These AND circuits 51a to 51
Each bit output of the shift register 53 is applied to each other terminal of h. This shift register 5
3 uses the aforementioned original clock run-in signal mask pulse RCRI as a data input, and uses the data sampling pulse DSP as a clock. The output of each AND circuit 51a to 51h is output from an OR circuit 52.
The output of this OR circuit 52 is used as a regular clock run-in signal mask pulse. Next, an example of operation will be explained using timing charts shown in FIGS. 4, 5, and 6. Now, for the sake of simplicity, let us assume that the pulse width of the reference mask pulse RFC, which sufficiently masks the designated timing at which the framing code will be detected, is the width of eight periods of the data sampling pulse DSP. For example, eight pulses are output from the AND circuit 44. First, to explain the signals in each figure, each figure a shows a data sampling pulse DSP, and each figure b shows a character multiplex signal, showing a clock run-in signal CRI and a framing code FC part. Furthermore, each diagram c and d shows the original clock run-in signal mask pulse.
RCRI and reference mask pulse RFC, which are obtained from logic array 42. Each figure e~1 is
These are the outputs of each bit Q ₀ to _{Q 7} of the shift register 53. Next, each figure m is a framing code detection pulse. Furthermore, each figure n to u is a shift register 4.
This is the output of each bit Q ₀ to Q ₇ of 5. Each figure v is the output of the AND circuit 44. Figure 4 shows
This is an example in which the clock run-in signal CRI is significantly delayed in phase from the position of the original clock run-in signal mask pulse RCRI. FIG. 6 is an example in which the phase of the clock run-in signal CRI is advanced compared to the example shown in FIG. 5. The framing code detection pulse FDP is applied to a shift register 45 (for example, 8 bits) whose shift clock is the output pulse PS1 of the AND circuit 44. By operating in this manner, the output of the shift register 45 becomes
It represents the mutual positional relationship between the reference mask pulse RFC and the actual framing code FC. That is, the framing code detection pulse FDP is input from the framing code detection circuit 18 to the data input terminal of the shift register 45.
Further, a clock as shown in FIG. 4V is inputted from the AND circuit 44 to the clock input terminal. The clock in FIG.
It is created from the reference mask pulse RFC and data sampling pulse DSP from The reference mask pulse RFC is a pulse created independently of the framing code detection operation, and is a pulse generated at an ideal position where a framing code is predicted to exist. Therefore, if the actually obtained framing code detection pulse FDP is shifted by the shift register 45 using the clock of this reference mask pulse RFC period, the ideal position of the framing code and the actually arriving framing code can be determined. It is possible to detect the phase shift with respect to the position of . On the other hand, the original clock run-in signal RCRI is input to the shift register 53 and transferred by the data sampling pulse DSP, so each bit Q ₀ to _{Q 7} of the shift register 53 is output for one period of the data sampling pulse. N pieces in different positions (8 in the illustrated example)
) example mask pulses will result. The output of the shift register 45 indicates the positional relationship between the reference mask pulse RFC and the framing code FC. Further, since the reference mask pulse RFC and the original clock run-in signal mask pulse RCRI are unconditionally generated based on the horizontal synchronization signal H, they have a fixed positional relationship. Therefore, by using the phase information obtained by the shift register 45, it is possible to select a mask pulse having an optimal phase (the phase matches the framing code) from among the outputs of the shift register 53. For this purpose, the output of the shift register 45 is transferred to an output conversion circuit 46 in which conversion data is stored in advance.
The signal is inputted to the input terminal, is converted into data, and becomes a control signal for the selector 50. In the example of FIG. 4, if the output _Q7 shown in FIG. 1 is derived from the AND circuit 51h, the clock run-in signal CRI can be effectively masked. In the example of FIG. 5, the output Q ₄ shown in i is derived from the AND circuit 51e, and in the example of FIG. 6, the output Q ₀ shown in e of the diagram is derived from the AND circuit 51a. Good. As described above, according to the present device, first, using the original clock run-in signal mask pulse, a plurality of mask pulses having different phases are generated by the shift register 53 approximately in the phase vicinity of the clock run-in signal, and the clock run-in signal is generated by the shift register 53. The most suitable pulse for masking the signal can be extracted by opening any one of the AND circuits 51a to 51h. To this end, while creating a reference mask pulse, a clock is created using this reference mask pulse and data sampling pulse, and this clock is used to
The framing code from the framing code detection circuit is transferred to the shift register 45, and the output state of the shift register 45 represents the phase position relationship between the framing code and the reference mask pulse, and based on this, the AND circuit 51a
A signal is created to select one of 51h. Here, the transmitted clock run-in signal and the framing code always have a constant relationship, and the original clock run-in signal mask pulse output from the logic array 42 and the reference mask pulse always have a constant relationship. In order to obtain the above operation, the output conversion circuit 46 stores a conversion table as shown in Table 1 below. In Table 1, there is a row in which only A ₀ is "1". This is the case in the timing chart of FIG. 4, and the data of FIG. 4 n is latched,
A state in which “1” is output to the D ₇ terminal of the output conversion circuit 46 is shown. At this time, since the AND circuit 51h is conductive, the shift register 53
The output of _Q7 will be selected as the mask pulse. In the case of the timing chart in Figure 5, Table 1
A row in which A ₃ is “1” is established. At this time, D ₄ of the output conversion circuit 46 becomes "1".
Then, since the AND circuit 51e becomes conductive, the output of _Q4 of the shift register 53 (FIG. 5i) is selected as a mask pulse. In the case of the timing chart shown in Figure 6, Table 1
A row in which A ₇ is “1” is established. At this time, D ₀ of the output conversion circuit 46 becomes "1",
The AND circuit 51a becomes conductive, and the output of _Q0 of the shift register 53 (FIG. 6e) is selected as a mask pulse. As mentioned above, according to this device, even if the superimposition position of a teletext packet fluctuates with respect to the horizontal synchronization signal, the mask pulse for extracting the clock line-in signal within the packet moves to follow it and always Accurate clock run-in signals can be obtained. The above explanation is based on the circuit for creating mask pulses for the clock run-in signal, but if K types of mask pulses are needed,
In addition to the circuit shown in Fig. 3, K data selectors, K
This is possible by providing multiple delay shift registers and logic arrays to generate original pulses for each mask pulse.

[Table] As explained above, even if the superimposition position of the teletext packet fluctuates within the horizontal scanning period, the present invention can control the clock run-in signal or the pulse for masking the framing code in the teletext packet. It is possible to provide a mask pulse generation circuit that can generate a signal by following the position of the signal.

[Brief explanation of drawings]

FIGS. 1a to 1e are explanatory diagrams showing examples of formats of television signals handled in teletext broadcasting,
FIG. 2 is a configuration explanatory diagram showing an embodiment of the present invention;
Figure 3 is a circuit diagram showing the main parts of this invention, Figure 4,
5 and 6 are signal waveform diagrams of various parts shown to explain an example of the operation of the circuit of FIG. 3, respectively. 14...Sampling circuit, 16...Clock run-in signal detection circuit, 17...Clock pulse generation circuit, 18...Framing code detection circuit, 21...Synchronization separation circuit, 41...Counter,
42...Logic array, 44...AND circuit,
45, 53...shift register, 46...output conversion circuit, 47...latch circuit, 50...data selector.

Claims (1)

[Claims] 1. A data packet inserted between synchronization pulses of a predetermined period, in which a clock run-in signal indicating a reference phase of data sampling and a framing code indicating the start of data are arranged in order on the time axis. a counter that is reset by the synchronization pulse and counts data sampling pulses that are synchronized with the clock run-in signal; logic means for generating a clock run-in signal mask pulse at a position corresponding to the framing code and a reference mask pulse at a position corresponding to the framing code; the clock run-in signal mask pulse being supplied to a data input terminal; a first shift register that is supplied to a clock input terminal and outputs a plurality of mask pulses with different phases to a plurality of output terminals; and a first shift register that outputs a plurality of mask pulses having different phases to a plurality of output terminals; a framing code detection means for detecting the framing code from the parallel data and obtaining a detection pulse thereof; and a clock input terminal for supplying the detection pulse obtained by the framing code detection means to a data input terminal; a second shift register into which a pulse obtained by calculating the logical product of the reference mask pulse and the data sampling pulse is input; and an output conversion means for decoding the output of the second shift register according to a predetermined rule. And, depending on the output content of this output conversion means, the above first
1. A mask pulse generation circuit comprising a selector for selecting any one of a plurality of mask pulses output from a shift register and deriving it as a mask pulse for an actual clock run-in signal.