JPS61216524A - Phase lock detecting circuit - Google Patents

Abstract

PURPOSE:To set a phase lock detection range and also to set an adaptive frequency range without any adjustment only by varying the setting of a delay time by solving problems of a conventional analog system by employing a digital system. CONSTITUTION:A frequency phase comparator 1 outputs signals D and U according to the phase relation between an input signal and the output of a VCO. Those outputs D and U are ORed and a signal 10 which is delayed by a time (t) is sampled by flip-flops 7 and 8 with the leading edge of the VCO output. When the phase difference between the input signal and VCO output is smaller than the delay time (t), the signal 10 is '0' at a sampling point of time, so signals 11 and 12 are both '0' and the output of an AND circuit 9 is '1', so that is detected as a phase lock state. When the phase difference is larger than the delay time (t), the input signal is sampled to obtain '0', but the output side of the VCO is sampled to detect '1' as the signal 10, which is not detected as the phase lock state. Namely, the range wherein the phase lock state is detected is determined only by the delay time (t).

Description

[Detailed description of the invention] [Field of application of the invention] In particular, the present invention relates to a circuit system suitable for digitization.

[Background of the invention]

As described in Japanese Unexamined Patent Application Publication No. 57-72430, the conventional circuit compares the control voltage that controls the oscillation frequency of the VCO (voltage controlled oscillation @) that constitutes the PLL with a reference voltage. A method using analog values was used to detect the phase synchronization state. However, with this method,
Because the reference voltage etc. is affected by variations in elements etc.
In order to obtain a detection output with a constant phase relationship, adjustments are often necessary to absorb variations between solids. Furthermore, the vCO control voltage takes on individual voltage ranges depending on the setting of the PLL loop constant and the operating frequency range.

Phase synchronization detection circuits had to be designed individually for each PLL. [Object of the Invention] An object of the present invention is to provide a phase synchronization detection circuit which solves the problems of the conventional method and can be applied stably, without adjustment, and over a wider frequency range.

[Summary of the invention]

The phase synchronization detection circuit of the present invention solves the problems of conventional analog circuits, such as variations in detection timing and the need for adjustment, by adopting a digital system.
The phase synchronization detection range and applicable frequency range can be set stably and without adjustment, and only by changing the delay time setting.

A feature of the present invention is that it can realize a phase synchronization detection circuit.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows the positioning of the implementation circuit in the present invention, and the phase synchronized circuit 4 of the present invention includes a frequency phase comparator 1. Loop filter 2. and a voltage controlled oscillator (VCO) 3. The D, U, and vCo outputs and the input signal are input, and phase synchronization detection is output. Second
The figure shows an example of a circuit configuration, and shows an OR circuit 5. Variable delay circuit 6
．． Edge trigger flip-flop 7°8, AND circuit 9
It consists of Also, FIG. 3 shows the circuit configuration of the frequency phase comparator 1 shown in FIG. 1, and the D and U signals as shown in FIG. Output. 4.5.6 is a timing chart of FIG. 2, and will be used to explain the operation of the circuit of the present invention.

In FIG. 4, the phases of the input signal and vCo output match. Although the PLL is in complete synchronization.

In this state, only whisker-like pulses generated by the delay of the logic gate in the frequency phase comparator 1 are generated in the D and U signals.

The signal 10 is obtained by taking the logical sum (○R) of the U output and further delaying by time t.In the flip-flops 7 and 8, the input signal and vCO
Signal 10 is sampled on the rising edge of the output. In FIG. 4, at this sampling point, the signal 10 is
Since it is "0", both signals 11 and 12 become "01", and the output of the AND circuit 9 becomes "1", which is detected as a phase synchronized state. In addition, in FIG. 5, the input signal and vC
Since there is a phase difference in the o output, the signal becomes "1" by that phase difference, but since the phase difference is smaller than the delay time t,
At the time of sampling, each signal 1o is "0" and is also detected as a phase synchronized state.

On the other hand, in FIG. 6, since the phase difference is larger than the delay time t, II OI is
P, but "1" of signal 10 is detected in sampling on the vCO output side.

It is not detected as a phase synchronized state. In addition, Section 4.5.
In Figure 6, we have explained the case where the phase of the vCQ output is delayed with respect to the input signal, but even in the case of the opposite phase difference, the operation is exactly the same except that the output power i is output to the signal U side. Therefore, there is no change in the detection output.

As described above, in this embodiment, the range in which the phase synchronization state is detected is determined only by the delay time t, and when the one phase difference is within It, the phase synchronization state is detected.

FIG. 7 shows an example in which this embodiment is connected to two PLLs with different synchronization frequencies, and since the ratio of the delay time t to the synchronization frequency is different, the range in which the phase synchronization state is detected is different.

In Fig. 7(a), 2・t/1/f=2ft Fig. 7(b
) is different from 2・t/2/f=ft. As a countermeasure for this, in this embodiment, the delay time can be changed by the variable delay circuit 6. In FIG. 7(b), by setting the delay time to 2t, 2.2t/2/f=2ft, It is possible to have the same detection range as in FIG. 7(a).

FIG. 8 shows another embodiment of the invention, with latch 15.1
6 is a type of element in which the D input is directly output to Q when the GK large input is 11H, and when the CK large input is L7+, the current Q is held.
14, if we create the differential circuit output 17.18 as shown in Fig. 9.

It is possible to hold the value of signal 10, and the same operation as in the embodiment is possible.

[Effects of the Invention] According to the present invention, it is possible to accurately detect that the PLL synchronization is within a certain phase difference without adjustment, and the detection range is limited only by the delay time t of the variable delay circuit. It is easy to set up. Also, PL with different synchronization frequency
There is also an advantage in that it can be dealt with by changing only the delay time t without changing the circuit.

Since the present invention has an entirely digital circuit,
This method is suitable for LSI implementation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the positioning of another embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram of a frequency phase comparator, and FIG. FIG. 8 is a configuration diagram of another embodiment of the present invention, and FIG. 9 is a supplementary explanatory diagram of FIG. 8. 1... Frequency phase comparator, 2... Loop filter. 3... Voltage controlled oscillator, 5... OR gate, 6... Variable delay circuit, 7.8... Edge trigger flip-flop, 9...
AND gate, 13, 14... Differential circuit. Figure 1 Figure 2 Figure height 3 Figure 4 Phase sacrificial silk: Detection Figure 5 Figure 6 Phase P1 stage. □ Gika Figure 7 uL) Figure 9

Claims (1)

[Claims] 1. Use the change point of the input signal as the input, and connect the VCO to the input signal.
In a phase synchronization detection circuit that detects the synchronization state of a PLL (period number phase-locked loop) that synchronizes the output of a voltage controlled oscillator (voltage controlled oscillator) in both frequency and phase, an input signal and a V
a flip-flop or latch that sets the phase error signal polarity of the PLL output in response to a change point of the CO output;
a delay circuit that delays the phase error signal of the PLL output and further allows the delay time to be freely set from the outside;
By digitally detecting the synchronization state and setting the delay time of the delay circuit, it is possible to output a detection output in any phase synchronization state, and at the same time, it is possible to use it in a wide frequency range. Characteristic phase synchronization detection circuit.