JPS6339209A - Synchronous circuit - Google Patents

Abstract

PURPOSE:To stably revise data by detecting the phase difference between a clock on a data side and a clock on a revise side and preventing a revised clock from approaching the changing point of data. CONSTITUTION:A type D flip-flop 5 fetchs a serial data (a) to a clock F. An FF 6 fetches the Q output (g) of the FF 5 with the aid of a clock (the revise side) (c), and outputs a data (h). An exclusive OR circuit 8 detects the phase relation between the clocks (b) and (c) at the same frequency, and outputs it as an output (d). An integration circuit 9 integrates the detected output (d). A comparator 10 with hysteresis outputs a logic signal corresponding to the height of the output voltage (e) of the integration circuit 9. An exclusive OR circuit 7 outputs a clock (f) with a phase the same as or reverse to the clock (b) according as whether the clocks (b) and (c) are of the same phase or reverse with each other. Consequently the clock (c) never approaches the changing point of the data (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital data communication, and more particularly to a serial data synchronization circuit.

[Conventional technology]

Conventionally, this type of synchronous circuit was simply re-flashed with a D-type flip-flop.

[Problem that the invention seeks to solve]

The above-mentioned conventional circuit using only D-type flip-flops has a drawback that the operation becomes unstable when the data change point coincides with the replay clock. This drawback becomes particularly noticeable when there is a delay on the re-coupling side clock or the data side clock.

[Means for solving problems]

The synchronous circuit of the present invention has a first D
A second D-type flip-flop that captures the Q output of the first D-type flip-flop in synchronization with a second clock, and a second D-type flip-flop that captures the Q output of the first D-type flip-flop in synchronization with the serial data and has the same frequency as the second clock. a first gate circuit that takes an exclusive OR or an exclusive NOR between the first clock and the second clock; an integration circuit that integrates the output of the first gate circuit;
A comparator with hysteresis that compares the vL shunt output with a predetermined threshold value, and a first clock and the output of the comparator are input, and the first clock and the second clock are almost in opposite phases. outputs a clock in phase with the first clock to the first D-type flip-flop,
The device includes a second gate circuit that outputs a clock having an opposite phase to the first clock to a second D-type flip-flop when the first clock and the second clock are substantially in phase.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the synchronous circuit of the present invention.

D-type flip-flop 5 receives serial data a using clock f. The D-type flip-flop 6 clocks the Q output g of the D-type flip-flop 5 (on the re-beating side).
Data h, which is the rewritten serial data a, is taken in in synchronization with C and output from the Q output. Exclusive OR circuit 8 detects the phase relationship between clock b and clock C by performing exclusive logic on clock b and clock C, which have the same frequency, and outputs it as output d. Integrating circuit 9 integrates the output of exclusive OR circuit 8. The comparator lO with hysteresis outputs a logic 1 signal when the output voltage e of the integrating circuit 9 is a high voltage and a logic O1 is a low voltage. The exclusive OR circuit 7 has a clock b and a comparator 10.
Enter the output of .

The clock f is output to the D-type flip-flop 5.

FIG. 2 is a diagram showing a waveform when the timing of the replay side clock C is near the center of the serial data a. FIG. 3 is a diagram showing a case where the timing of the replay side clock C is near the change point of the serial data a.

Note that it is assumed that the rise of clock b is slightly ahead of the change point of serial data a.

Figure 2 shows a case where clock b and clock C are almost in opposite phases, and an exclusive OR circuit 8 of both clocks b and C is shown.
When we take the exclusive OR, we get the waveform output d as shown in the figure.
If this is integrated by the integrating circuit 9, a high voltage e is obtained, and the output of the comparator 10 becomes logic O. Therefore, the output f of the exclusive OR circuit 7 is in phase with the clock b.

The serial data a and the output g of the D-type flip-flop 5 are in phase. By beating this output g again with the clock C, the output g can be obtained. Since the clock C rises approximately at the center of the output g, it can be re-beated stably.

Figure 3 shows a case where clock b and clock C are almost in phase, and an exclusive OR circuit 8 of both clocks b and C is shown.
When the exclusive OR is taken, the waveform output d as shown in Figure 1 is obtained.
If this is integrated by the integrating circuit 9, a low voltage e is obtained, and the output of the comparator 10 becomes logic 1. Therefore, the output f of the exclusive OR circuit 7 has a phase opposite to that of the clock b, and the output g of the D-type flip-flop 5 has a waveform shifted by 180 degrees with respect to the serial data a. By beating this output g again with the clock C, the output g can be obtained.

Since the clock C rises approximately at the center of the output g, it can be re-beated stably.

If there is jitter in the clock b or clock C, a jitter component also appears in the output d, but it is absorbed by the integration in the integrating circuit 9 and does not appear in the output of the comparator 10. The waveform of the output g will not deviate by 180 degrees or become 0 degrees, and no fluttering will occur.

〔Effect of the invention〕

As explained above, the present invention detects the phase difference between the data side clock and the re-beating side clock and prevents the re-beating side clock from approaching a data change point, thereby stably resetting the data. There is an effect that can be done.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the synchronous circuit of the present invention, Fig. 2 is a diagram showing waveforms of various parts when the data side clock 2 and the re-synchronization side clock 4 are almost in opposite phases. 3
The figure shows waveforms at various parts when the data-side clock 2 and the re-beating-side clock 4 are approximately in phase. 1...Serial data before retouching, 2...
...Clock synchronized with serial data l, 3...
... Re-beating data, 4... Re-beating side clock with the same frequency as clock 2, 5... D-type flip-flop for shifting serial data 1 by 1800, 6. ...D-type flip-flop to re-flip the data, 7... Exclusive OR circuit that creates a clock to shift by 180 degrees, 8... Data-side clock 2 and Exclusive OR circuit for detecting the phase difference with the correction side clock 4, 9...Integrator circuit, 10...Comparator with hysteresis.

Claims (1)

[Claims] A first D-type flip-flop that takes in serial data; a second D-type flip-flop that takes in the Q output of the first D-type flip-flop in synchronization with a second clock; A first gate circuit that synchronizes with the serial data and takes an exclusive OR or an exclusive NOR between a first clock and a second clock having the same frequency as the second clock; and integrating the output of the first gate circuit. an integrator circuit, a comparator with hysteresis that compares the output of the integrator circuit with a predetermined threshold, a first clock and the output of the comparator are input, and the first clock and the second clock are in almost opposite phase. When the clock is in phase with the first clock, a clock that is in phase with the first clock is output to the first D-type flip-flop, and when the first clock and the second clock are almost in phase, a clock that is in phase with the first clock is output. A synchronous circuit having a second gate circuit that outputs a signal to a first D-type flip-flop.