JPS61216482A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable to write and to erase at a high speed by constructing to have the third polycrystalline silicon layer formed to have a region electrically connected with the first polycrystalline silicon layer for generating a tunnel current through a thin insulating film on a semiconductor substrate. CONSTITUTION:A field oxide film 12 is formed on the surface of a P-type semiconductor substrate 11, and a gate oxide film 14 of a channel region 19 of a memory transistor is formed. Then, the first polycrystalline silicon layer to become a floating gate is formed, patterned, oxidized on the surface as a gate oxide film 17, the second polycrystalline silicon layer is formed, patterned and then oxidized on the surface to form a gate oxide film 21. A contacting hole 26 is opened at the portion of the floating gate 16 projected externally of a control gate 18, the oxide film is removed to expose the surface of the floating gate 16 of the portion, the third polycrystalline silicon layer is formed, and so patterned as to coat the part of a thin gate oxide film 25 and the hole 26 to form an auxiliary floating gate 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device having means for injecting and extracting electrons into and out of a conductive layer by means of a tunnel current through a thin insulating film.

[Conventional technology]

Conventionally, a nonvolatile semiconductor memory device (hereinafter simply referred to as a memory), which has a means for injecting and extracting electrons into and out of a conductive layer using a tunnel current through a thin insulating film, has a planar structure as shown in FIG. was. In order to explain the principle of writing and erasing, FIG. 8 shows a cross-sectional view taken along the line AA' in FIG. 7. In this structure, for example, the field insulating film 2,
A gate insulating film in the channel region 9 and a thin gate insulating film 3 through which tunnel current flows are provided, an n-type diffusion ff1is is provided under the gate insulating film 3, and an even thinner gate insulating film 3 is provided.
floating gate 6, gate insulating film 7, control gate) 8t
-obtained by sequentially stacking them.

When writing/erasing information to this memory, N
A voltage is applied between the type diffusion layer 5 and the control gate 8, and a high electric field is generated in the thin gate insulating film 3 (for example, 8i02 film) due to the capacitive coupling between the intertype diffusion layer 5, floating gate 6, and control gate 8. is applied, and the tunnel current flows in the tunnel current region ``0'', 7 A. (Fowler-Nordhe
im ) ) Y By generating a channel current, electrons are injected into or withdrawn from the floating gate 6 , thereby changing the threshold voltage of the channel region 9 of the memory transistor from the control gate 8 .

[Problem that the invention seeks to solve]

In this case, the speed of writing and erasing information is determined by the voltage applied between each electrode, the thickness of the thin gate insulating film 3, the ratio of capacitance between each electrode, etc. In order to increase the speed, the trap is set by the applied voltage. , and increase the capacitance between the thin gate insulating film 3t (thinner than floating) and the control gate relative to other capacitances (hereinafter referred to as improving the capacitance ratio). are each desirable. However, increasing the applied voltage is limited by the withstand voltage of the memory, and making the gate insulating film thinner is also limited by increased pinhole density, dielectric breakdown, and the like. In order to improve the capacitance ratio, two methods are considered: reducing the thickness of the gate insulating film between the floating gate and the control gate, and increasing the overlap area. An increase in the overlap area leads to an increase in the area of the device and impedes higher integration.

In addition, from the perspective of memory characteristics, as in the conventional method, a floating gate is formed on a diffusion layer via a thin gate insulating film, and then heat treatment is performed at a high temperature of approximately 950°C or higher (for example, forming a source/drain region). Therefore, when arsenic ions are implanted and heat treatment is performed to activate them, the state of the interface between the floating gate and the thin gate insulating film underneath changes, causing the insulating film I! It is known that the amount of charge that can flow into the gate insulating film decreases by the time it reaches . In other words, the formation of a thin gate insulating film that flows through the tunnel and the formation of a floating gate located above it cannot meet these requirements with a process that uses as much post-contact technology as possible in memory fabrication.

An object of the present invention is to increase the overlap area between the floating gate and the control gate without increasing the memory cell area, and without performing high-temperature heat treatment after forming the tunnel insulating film and the floating gate thereon. The object of the present invention is to provide a nonvolatile semiconductor memory device with high integration density, which can realize a simple process, enable high-speed writing and erasing, and provide high reliability.

[Means for solving problems]

The nonvolatile semiconductor memory device of the present invention has a floating gate structure t
- a first polycrystalline silicon layer forming the floating gate formed on the semiconductor substrate via the insulating film; a second polycrystalline silicon layer disposed so as to partially cover the first polycrystalline silicon layer with an insulating film in between; A third polycrystalline silicon layer is disposed so as to cover the semiconductor substrate, is electrically connected to the first polycrystalline silicon layer, and is formed on the semiconductor substrate so as to have a corner region for generating a tunnel current through the thin insulating film. and a crystalline silicon layer.

〔Example〕 .

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing one embodiment of the present invention, and FIGS. 2 to 4 are sectional views taken along line H-B/C-C in FIG. 1, respectively.
/ line sectional view and DD' line sectional view.

This embodiment is formed as follows. First, a field oxide film 12t- is formed on the surface of the P-type semiconductor substrate att using the usual LUCO8 method, and a gate oxide film 4 for the channel region 19 of the memory transistor is formed. Next, after forming and patterning the l-th polycrystalline silicon layer that will become the floating gate 6, the surface is oxidized to form a gate oxide film 1.
7, and after forming and patterning a second polycrystalline silicon layer that will become the control gate 18, the surface is oxidized to form gate oxidation m2Lt. At this time, the control gate ``8'' is formed to cover the floating gate ``6t'', but the floating gate ``6t'' is formed as if it were covered.
A part of the control gate 6 is made to protrude to the outside of the control gate 18 as shown in FIG. Next, in order to form a drain region 23 and a source region 241, arsenic ions are implanted and an appropriate heat treatment is performed, and then a part of the oxide film on the drain region 23 is removed, and a thin gate with a thickness of approximately 100X is formed. Oxide film 2
form 5. Furthermore, a contact hole 26 is opened in a portion of the floating gate 6 that protrudes to the outside K of the control gate 8, and the oxide film is removed to expose the surface of the floating gate 16 in that portion. Thereafter, a third layer of polycrystalline silicon NIt- is formed and patterned to cover at least a portion of the thin gate oxide film 25 and the contact hole 26, thereby forming an auxiliary floating layer 22t-. As a result, the auxiliary floating gate 22 is electrically connected to the floating gate 16 and integrated as a floating gate, and the capacitance between the floating gate and the control gate is increased by using both the upper and lower surfaces of the control gate. Well formed.

After this, an interlayer film is formed and contact holes are opened in the same manner as in the conventional manufacturing method of MO8 type semiconductor devices.

Metal wiring etc. will be done. In other words, after the formation of the thin gate oxide 825 and the subsequent formation of the auxiliary floating gate 22 using the <am-th polycrystalline silicon layer, the interface state between the auxiliary floating gate 22 and the gate oxide film 25 may be adversely affected. This eliminates the need for high-temperature heat treatment. Note that 2° is a tunnel current region where a tunnel current flows.

As is clear from the above description, according to this embodiment, the absolute R film thickness between the floating gate and the control gate is constant, and the memory cell area is also constant at tt. Capacity can be approximately doubled, so
The capacitance ratio can be improved without any loss in device reliability, and the speed of writing and erasing information can be increased.

Furthermore, after forming the thin insulating film through which the tunnel current flows and the auxiliary floating gate on top, it is possible to realize a process that does not require high-temperature heat treatment, greatly improving the lifespan of memory against repeated programming and erasing, and improving its reliability. can be increased.

Examples of such improvements in memory characteristics are shown in FIGS. 5 and 6. Figure 5 compares only the structure with the conventional one, with the insulating film thickness between the floating gate and the control gate, the area of the memory cell, etc. being the same, and the time to obtain the same threshold voltage is approximately 1Ff. You can see that it has been improved.

Figure 6 also shows a device in which floating gates (1) are formed on both the upper and lower surfaces of the control gate as in the present invention, and the capacitance ratio is improved. The same capacitance and the same threshold voltage can be obtained by using the comparative type formed under the gate and the type formed under the auxiliary floating gate of the third polycrystalline silicon layer according to the present invention.
This is a total comparison of the amount of accumulated defective bits generated when programming and erasing are repeated by changing the amount of voltage shift, and it can be seen that the reliability of the memory against repeated programming and erasing is improved by the present invention.

〔Effect of the invention〕

As described above in detail, (1) according to the present invention, the above means are used; (2) thinning of the insulating film between the floating gate and the control gate, which is a problem in terms of memory reliability;

1) Expansion of the floating gate-control gate overlap area, which hinders high-density integration.

However, it is possible to improve the capacitance ratio.Also, all high-temperature heat treatments that adversely affect the interface between the thin insulating film through which the tunnel current flows and the floating gate above it must be performed beforehand. By performing this step, it is possible to improve the reliability of the memory, and as a result, a nonvolatile semiconductor memory device that is capable of high-speed writing and erasing, and has high reliability and high integration density can be obtained.
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[Brief explanation of drawings]

Figure 1 is a plan view showing one embodiment of the present invention, Figures 2 and 3 are
4 is a sectional view taken along the line BB' in FIG. 1. A cross-sectional view taken along the line C-C/, a cross-sectional view taken along the line 1)-17', FIGS. 5 and 6 are characteristic comparison diagrams between the embodiment of the present invention and a conventional example, and FIG. 7 is a plan view showing a conventional example. , FIG. 8 is a thin cross-sectional view taken along the line AA' in FIG. 7. iI...P-type semiconductor base number, 2...Field oxide film, 14...Gate oxide film, 16
..... floating goo), 17 ..... gate oxide film, 18 ..... control gate, 19 ..... channel region, 20 ..... tunnel current area, 2
1...Gate oxide film, 22...Auxiliary floating gate, 23...Drain region, 24...
. . . Source region, 25 . . . Thin gate oxide film, 26 . . . Contact hole. Agent Patent Attorney Susumu Uchihara - Ha Kaya / [3rd fungi 4 Figure 4g (time) → Kaya 5! Ni-1 Oto En

Claims (1)

[Claims] In a nonvolatile semiconductor memory device that has a floating gate structure and electrically writes and erases information by tunneling current through a thin insulating film, the floating gate is formed on a semiconductor substrate with an insulating film interposed therebetween. a first polycrystalline silicon layer, a second polycrystalline silicon layer disposed so as to partially cover the first polycrystalline silicon layer with an insulating film in between, and a second polycrystalline silicon layer with an insulating film in between. a region that is arranged to cover a part of the first polycrystalline silicon layer, is electrically connected to the first polycrystalline silicon layer, and generates a tunnel current on the semiconductor substrate through the thin insulating film. and a third polycrystalline silicon layer formed as described above.