JPS61192099A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate a functional test by providing switching measures to carry out a check-bit-memory cell-array test. CONSTITUTION:A data input switching circuit 11, data output switching circuit 12 and address switching circuit 13 make a data input, data output and address connect to the check-bit-memory cell-array 4 in accordance with respective mode switching signals TE. When a mode switching signal TE theoretical level is 'L', an ordinary operation is carried out and when the above theoretical level is 'H', a test mode is performed as one of the operation modes and a data input signal line 14, data output signal line 15 and address signal line 16 are connected to the check-bit-memory cell-array 4 and then the check-bit- memory cell-array is accessible from an outside. In other words, it is possible for data to perform inputs and outputs to/from the concerned bits in conformity to an input address and also to perform the same functional test as the ordinary data-bit-memory cell-array 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having an error detection and correction (hereinafter referred to as rEccJ) function.

[Conventional technology]

In recent years, as semiconductor memory devices have become more highly integrated, malfunctions of memory cells due to incidence of α particles, ie, soft errors, have become a problem. As a countermeasure to this problem, on-chip ECC is being implemented in which the ECC function is provided on the same semiconductor substrate.

FIG. 5 shows a circuit example of a conventional on-chip FCC semiconductor memory device using a Hamming code as an error correction code. In FIG. 5, ■ is an input terminal into which data bit a is input; 2 is a write check bit generation circuit that generates write check bit b from data bit a;
3 inputs data bit a and inputs new data bit C
4 is a check bit memory cell array that inputs write check bit b and outputs a new write check bit d; 5 is a check bit memory cell array that outputs data bit C; 6 is a syndrome generation circuit that has an exclusive OR function and outputs syndrome f; 7 is a syndrome decoded data g that decodes syndrome f; 8 is a data correction circuit that corrects data bit C and write check bit d using syndrome decode data g and outputs corrected data h and external output data i; 9 is an external circuit that outputs data to the outside. An address decoder selects output data j; 10 is an output terminal for outputting external output data j; A is a data bit memory cell array 3 and a check bit memory cell array 3;
This is a memory cell array composed of a memory cell array 4.

Next, the operation of the device configured as described above will be explained. When writing data bit a of m0 bit input to input terminal 1, write check bit generation circuit 2 writes to multiple bits (referred to as m bits) including data bit a.・Generate check bit (k bit) b, and write check bit b and m bit data bit a to check bit memory cell array 4 and data bit memory cell array 3 write to. This (m+k) bit block is the unit of ECC, and error detection and correction are performed for each block.

When reading data from memory cell array A, bit write/check is performed on m-bit data/bit C.
Bit d is read at the same time, and the read check bit generation circuit 5 generates a read check bit from this m-bit data bit C as a new check bit.
This read check bit e and the memory cell
Write check bit d read from array A
Perform bitwise exclusive OR with . As a result, if all bits are "0", it is determined that there is no error; otherwise, it is determined that there is an error. The fact that all e bits are 0 means that the read check bit e and the write check bit e
This means that bit d matches. The data of the exclusive OR described above is called a syndrome. A syndrome is a data string consisting of bits. The syndrome generation circuit 6 outputs the syndrome f to the syndrome decoder 7.

The syndrome f described above includes position information of error bits, and by decoding this information with the syndrome decoder 7, it is possible to know which bit among the m data bits is an error. Accordingly, in the data correction circuit 8, error bits among the m-bit data bit C and the write check bit d are corrected, that is, inverted. - On the ship, of the m-bit corrected data group, the external data output is mo.
It's a bit. In this case, m0≦m bits. Therefore, the external output data j output from the address decoder 9
is selected according to the address information k input to the address decoder 9 and output. address decoder 9
In many cases, most or all of the access decoder (not shown) can also be used.

Write check bit generation circuit 2. The read check bit generation circuit 5 is a circuit that generates check bits from m-bit data bits according to the configuration of the error detection/correction code, and since the logic operations are the same for both, the same circuit can be used for both. There is also a method. Furthermore, as described above, the syndrome generation circuit 6 generates data in the write check bit generation circuit 5 and the write check bit d read from the memory cell array A.
Newly generated read check pill from bit C
This is a circuit that takes a bit-by-bit exclusive OR with -e. The syndrome decoder 7 converts the k-bit syndrome f into the m-bit data bit C and bit write.
m+ that specifies the error bit among the check bits d
is a decoder that converts the sign of bits to, for example,
Among the bits in m+, an output is obtained in which only the error bit position is "l" and the rest are "0". The data correction circuit 8 is a circuit that performs a bit-by-bit exclusive OR of the syndrome decoded data g output from the syndrome decoder 7, the data bit C to be corrected, and the write check bit d. , the data of only the error bit is inverted, that is, the error is corrected. The error-corrected m10 bits of corrected data h are again stored in the memory cell.
is written to a predetermined location in array A. In addition, the data bits i of the corrected m bits are
The 0-bit data bit is selected by address decoder 9 and becomes external output data j.

[Problem that the invention seeks to solve]

When performing a functional test on a memory chip configured as described above, the data bit memory cell array 3 can be accessed from the outside, but the check bit memory cell array 4 cannot be accessed from the outside. Because I can't
There is a problem in that it is not possible to perform a functional test of only the check bit memory cell array 4.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor memory device in which a functional test of only the check bit memory cell array 4 can be easily performed. It is in.

[Means for solving problems]

In order to solve these problems, the present invention provides a semiconductor memory device with a switch means for testing a check bit memory cell array.

[Effect]

In the present invention, the switch means connects various signal lines to the check bit memory cell array according to the control signal.

〔Example〕

An embodiment of the semiconductor memory device according to the present invention is shown in FIG. 1. In FIG. is placed on the input side of
The data output switching circuit 12 is arranged on the input side of the address decoder 9, the address switching circuit 13 is arranged on the output side of the address decoder 9, and the data input switching circuit 11. The data output switching circuit 12 and the address switching circuit 13 constitute switching means. 1st
In the figure, the same or equivalent parts as in FIG. 5 are given the same reference numerals.

Next, the operation of this device will be explained. Data input switching circuit 11. Data output switching circuit 12 and address switching circuit 13 each connect a data input, a data output, and an address to check bit memory cell array 4 according to mode switching signal TE. When the logic level of the mode switching signal TE is rLJ, normal operation is performed, and when the logic level of the mode switching signal TH is rHJ, the operation mode is a test mode, and the data input signal line 14. Data output signal line 15. Address signal line 16 is connected to check bit memory cell array 4, making check bit memory cell array 4 externally accessible. That is, data can be input/output to the corresponding bit according to the input address, and a functional test similar to that of a normal data bit memory cell array 3 can be performed.

FIG. 2, FIG. 3, and FIG. 4 each show an address switching circuit 13. Data input switching circuit 11. 3 is a circuit diagram of a data output switching circuit 12. FIG. The configurations of these circuits will be explained below.

In FIG. 2, 20 is an input terminal to which a mode switching signal TE is input, 21 is an input terminal to which address information from address decoder 9 is input, and 22 is an input terminal to which address information is input to data bit memory cell array 3. An output terminal 23 is an output terminal for outputting address information to the check bit memory cell array 4.

In FIG. 3, 30 is an input terminal to which the mode switching signal TE is input, 31 is an input terminal to which data is input,
32 is data bit memory cell array 3
An output terminal 33 is an output terminal for outputting data to the check bit memory cell array 4.

In FIG. 4, 40 is an input terminal to which the mode switching signal TE is input, and 41 is the input terminal for receiving data from the data correction circuit 8.
An input terminal to which bit i is input, 42 is an input terminal to which write check bit d is input from check focus memory cell array 4, and 43 is data bit i or write check bit to address decoder 9. This is an output terminal for outputting d.

The data input switching circuit 11 described above. Data output switching circuit 12. Due to the address switching circuit 13, the check bit memory cell array 4, which normally has a configuration that cannot be accessed from the outside, becomes directly accessible from the outside in the test mode, and data
Similar to bit memory cell array 3, check bit memory cell array 4 can be functionally tested.

Although the above embodiment shows an example of an ECC circuit system using Hamming codes, the present invention is not limited to this. It is applicable to all methods with

〔Effect of the invention〕

As explained above, the present invention provides an operation mode in which the check bit memory cell array is directly accessed from the outside by providing a switch means for testing the check bit memory cell array in a semiconductor memory device. This has the advantage that it is possible to easily perform a functional test of the check bit memory cell array, which is normally inaccessible from the outside.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of an address switching circuit constituting this device, and FIG. 3 is a circuit diagram showing an embodiment of the device. A circuit diagram showing an example of a data manual switching circuit for
FIG. 4 is a circuit diagram showing one embodiment of the data output switching circuit constituting the present device, and FIG. 5 is a system diagram showing a conventional semiconductor memory device. 1...Input terminal, 2...Write check bit generation circuit, 3...Data bit memory cell array, 4...Check bit memory cell.
Array, 5...Read check bit generation circuit, 6...Syndrome generation circuit, 7...Syndrome decoder, 8...Data correction circuit, 9...
・Address decoder, 10... Output terminal, 11...
...Data input switching circuit, 12...Data output switching circuit, 13...Address switching circuit,
14...Data input signal line, 15...Data output signal line, 16...Address signal line.

Claims (2)

[Claims] (1) A semiconductor memory device equipped with a check bit memory cell array for an on-chip error detection/correction function, comprising a switch means for testing the check bit memory cell array; A semiconductor memory device having an operation mode in which the check bit memory cell array is directly accessible from the outside by a switch means. (2) The switch means includes an address signal line in the operation mode;
Check the data input signal line and data output signal line.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is directly connected to a bit memory cell array.