JPS61176871A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To test a multipin VLSI at a high-accuracy timing without increasing hardware or without increasing electric power consumption by providing a piece of basic timing generator and providing timing adjusters to respective pin control parts. CONSTITUTION:The basis timing generator 102 outputs a test period signal 23 having the period of integer times the period of a basic clock signal 1 and plural basic timing signals 3. A pattern generator 101 outputs plural test pattern signals 2 and a selector 104a of the pin control part 103a outputs selectively a test pattern signal 4 and a signal 5 indicating the expected value of the test result from the signal 2. The timing adjusters 106a, 107a receive the basic timing signals selected by the selector 105a and output timing signals 8, 9 having the resolving power higher than the resolving power of the basic clock signal 1. A waveform formatter 108a outputs a test waveform to an element to be tested and a digital comparator 109a compares and discriminates the response signal and the signal 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor testing device, and more particularly to a semiconductor testing device capable of testing a multi-pin VLSI with highly accurate timing.

[Background of the invention]

As a conventional semiconductor test equipment for multi-pin VLSI,
1983 International Test Conference (1983)
Stave B 1s at nalT ast Conference
“The Development of a
TESTER PERPIN BUILDERSEY TEST SYSTEM ARCHITECTURE”
opment of AT es-tar-p
er Pin V L S I Te5t S
systemA architecture), and Michael Catalano.
ano) *Richard Feltman
“Induvidual Signal Path Calibration for Maximum Timing Accuracy in a High Pin Count Vuernis Eye Test System” by R.D. Faldman, Robert Krutiansky, and Richard Swan.
Signal Path Calibration
For Maximum Timing Acc
uracy in A High Pinko
unt V L S I Te5t System
) are known.

The semiconductor testing device described in the above-mentioned document is intended to improve test accuracy, particularly timing accuracy, and has the following configuration. In other words, in order to improve timing accuracy, the accuracy of both the output timing of the test waveform applied to the pin of the device under test and the judgment timing for comparing and determining whether the response signal is normal or abnormal must be improved for each pin. There is a need.

Therefore, the semiconductor testing device described in the above-mentioned document is provided with a timing generator for each pin to determine the above-described output timing and determination timing.

However, as the number of pins of devices under test increases as in VLSI, providing the above-mentioned timing generation circuit for each pin increases the hardware of the semiconductor device, increases the price, and increases power consumption. Causes problems.

[Purpose of the invention]

The present invention was developed in view of the problems of the prior art described above, and allows testing of multi-pin VLSI with high precision timing, while suppressing increases in hardware, price, power consumption, etc. [Summary of the Invention] The semiconductor testing device of the present invention has a first timing signal that outputs a plurality of basic timing signals having a resolution equal to that of the basic clock signal. one means is provided for each pin in common, and a second means for receiving the plurality of basic timing signals and outputting a timing signal having a resolution higher than that of the basic clock signal is provided for each pin. It is characterized by outputting test waveforms and determining pass/fail of the semiconductor according to the test waveform.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and as shown in the figure, an oscillator 100, a pattern generator 101, a basic timing generator 102, and a pin control section 103.
It is composed of a to 103n. The pin control sections 1038 to 103n are provided in a number corresponding to the number of pins of the device under test, and each pin control section 1038 to 103n is provided in a number corresponding to the number of pins of the device under test.
3n has the same configuration. Therefore, in the following explanation, the pin control section 103a will be used.

Oscillator 100 outputs basic clock signal 1 to basic timing generator 102 . The basic timing generator 102 divides the basic clock signal 1 according to the basic timing selection signal 22 output from the pattern generator 101,
As shown in FIG. 2, the period is an integral multiple of the period T of the basic clock signal 1 (nIT, n2T, etc.).

Hereinafter referred to as the test cycle. ) is output. At the same time, the basic timing signal generator 1
02 is a time ml which is an integral multiple of the period T of the basic clock signal 1 from the output time tI, t2 of the test period signal 23 as shown in FIG. 2 according to the basic timing selection signal 22.
A plurality of basic timing signals 3 delayed by T, m2T, etc. are output. Here, as shown in FIG. 2, the test period (
ntTy nzT) changes according to the basic timing selection signal 22, and similarly, the delay time (mIT tm2T, etc.) of one basic timing signal 3 also changes according to the basic timing selection signal 22.

The pattern generator 101 generates the test periodic signal 23 described above.
A plurality of test pattern signals 2 are output over a test period determined by .

The selector 104a of the pin control unit 103a selects one test pattern signal from the plurality of test signals 2 and outputs it as a test pattern signal 4 to the waveform formatter. Similarly, the selector 104a selects a test pattern signal 5 indicating the expected value of the test result from the plurality of test pattern signals 2 and outputs it to the digital comparator 109a. Similarly, the selector 105a selects at least one basic timing signal from the plurality of basic timing signals 3 and outputs it to the timing adjusters 106a and 107a as a basic timing signal 6.7.

Timing adjusters 106a and 107a receive basic timing signals 6 and 7 selected by selector 105a, respectively.
After receiving the basic clock signal 1 and synchronizing with the basic clock signal 1, the timing signals 8 and 9 having a resolution higher than that of the basic clock signal 1 are output.

The waveform formatter 108a receives the test pattern signal 4 and the timing signal 8, creates a test waveform, and outputs it via the driver 109a. This test waveform is input to a device under test (not shown), and a response signal from the device under test is input to a comparator 110a.

Comparator 110a compares the response signal from the device under test with a predetermined voltage and outputs a digital response signal.

The digital comparator 109a receives the digital response signal and a test pattern signal 5 indicating the expected value of the test result.
A comparison determination as to whether or not they match is performed at the input timing of the timing signal 9. In the manner described above, the test of the device under test is performed for each pin.

Next, timing adjusters 106a and 107 shown in FIG.
The details of the operation of a will be explained using FIGS. 3 and 4.

Note that since the timing adjusters 106a and 1078 have the same configuration, only the timing adjuster 106a will be described here. As shown in FIG. 3, the timing adjuster 106a has a memory 202 storing timing setting values less than the period of the basic clock signal 1, and an offset value for adding an arbitrary time offset to the timing settings. Register 201. an ALU 203 that adds the offset value 24 output from the register 201 and the timing information 25 read from the memory 202;
A delay circuit 20 that delays the timing signal 7 created with the resolution of the basic clock signal 1 by the resolution of the basic clock signal.
4, and a D flip-flop 2 which takes the period of the timing signal 20 delayed by the delay circuit 204 and the basic clock signal 1.
05 and.

It is constituted by a delay circuit 206 that delays the output 21 of the D flip-flop 205 with a resolution of one or more of the basic clock signal. Here, the resolution is, for example, the rising time t3y when the timing signals 20 and 9 have the logical value "1".
This indicates the time unit in which t4 can be controlled, and has a time dimension. Specifically, the basic timing signal 3 shown in FIG.
Since the rise time can only be controlled in units of integral multiples of the period T, one resolution is T.

According to FIG. 4, the timing adjuster 106 shown in FIG.
The operation of a will be explained. The timing selection signal 22 causes the memory 202 to be read, and timing information 25 is output. On the other hand, the offset value 24 is output from the register 201, and the ALV 203 outputs the timing information 2.
5 and the offset value 24 and output the added value 26. By this addition value 26, delay circuits 204 and 206
The delay time is set. Here, the delay 204 is configured so that the delay time can be set in units of T/n (n is an integer 1, and T is the period of the basic clock signal 1) according to the addition value 26. Due to the function of this delay circuit 204,
The timing signal 7 with a resolution of T (because the resolution of the basic timing signal 3 is T) is converted into a timing signal 20 with a resolution of T/n. This timing signal 2
0 is synchronized with basic clock 1 by D flip-flop 205 and then input to delay circuit 206 . The delay circuit 206 functions as follows. That is, in FIG. 1, a pattern generator 101 and a basic timing generator 102
The test pattern signal 2 and the basic timing signal 3 respectively output from the selectors 104a and 105a have different transmission times due to the difference in length of the signal lines to the selectors 104a and 105a. Therefore, as shown in FIG. 2, the delay time of the plurality of basic timing signals 3 is an integral multiple of the period T (mIT).

Q, T, etc.), the pin control sections 103a to 1
03n, the phase difference between each basic timing signal 3 deviates from an integral multiple of the period T. If such a situation occurs, each pin control section 103a"1
It becomes impossible to output the test waveform at a predetermined timing from 03n and to perform a comparison judgment between the response signal and the test pattern signal 5 indicating the expected value at a predetermined judgment timing.

The delay circuit 206 has the role of eliminating the test timing deviation due to the length of the signal line described above. In this way, errors in test timing based on the length of the signal lines from the pin control units 103a to 103n are removed.
A timing signal 9 having a resolution of T/n is generated.

As is clear from the above explanation, according to the above embodiment,
Pin control section 103 provided for each pin
Since one basic timing generator is provided without providing a timing generator for all pin control sections 103a to 103n, and a timing adjuster is provided to each pin control section 103a to 103n, test waveforms can be output with high timing accuracy. Accordingly, it is possible to provide a semiconductor testing device that can perform pass/fail determination with high timing accuracy.

〔Effect of the invention〕

According to the present invention, it is possible to provide a semiconductor testing device that can test a multi-pin VLSI with high precision timing without increasing the hardware, increasing the price, or increasing the power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a semiconductor testing device according to the present invention, FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1, and FIG. 3 is a summary of the embodiment shown in FIG. 1. FIG. 4 is a block diagram showing the timing adjuster, which is the third
5 is a time chart showing the operation of the timing adjuster shown in the figure. 100... Oscillator, 101... Pattern generator, 1
02...timing generator, 103a-103n...
・Pin control section, 104a-selector, 105a
-Selector, 106a, 107a...timing generator, 108a...waveform formatter, 109a...
・Digital comparator, 110a...driver,
111a... Comparator, 201... Register,
202...Memory, 203...ALU, 204...
・Delay circuit, 205...D flip-flop, 206
...Delay circuit. Representative Patent Attorney Tadashi Akimoto No. 1 Figure 3 Figure 4 Procedural amendment submitted June 5, 1985

Claims (1)

[Scope of Claims] 1. In a semiconductor testing device that outputs a test waveform to each pin of a semiconductor and determines whether the semiconductor passes or fails from the response signal, a plurality of basic clock signals having a resolution equal to that of the basic clock signal are used. A first means for outputting a timing signal is provided for each pin in common, and a second means for receiving one of the plurality of basic timing signals and outputting a timing signal having a resolution higher than that of the basic clock signal. A semiconductor testing device characterized in that a means is provided corresponding to each pin, and outputs a test waveform and determines pass/fail according to the timing signal. 2. The semiconductor test according to claim 1, wherein the second means includes means for eliminating timing errors caused by the length of the signal line of the basic timing signal in the semiconductor test equipment. Device.