JPS6116324A - Asynchronous data transfer system - Google Patents

Abstract

PURPOSE:To raise the speed of normal data transfer processing by performing the interruption processing only when a first-in first-out memory is filled up. CONSTITUTION:A main processor 1 sets the enable mode, where interruption is accepted, at the beginning of data transfer processing and transfers data to a first-in first-out memory 4 to write data successively without discriminating a data write enable/disable signal 7 of the memory 4. A slave processor 3 performs the processing in accordance with data received in the memory 4. When the memory 4 is filled up, an interruption signal 11 is generated, and the processor 1 takes in the data write enable/disable signal of the memory 4.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an asynchronous data transfer method between a main processor and a slave processor that is equipped with a first-in, first-out memory as a data buffer and performs data transfer processing faster than the main processor. In particular, the present invention relates to two types of data transfer methods between a main processor and a slave processor, and relates to an asynchronous data transfer method for efficiently transferring data from the main processor to the slave processor.

[Prior art]

A conventional asynchronous data transfer method of this type will be explained with reference to FIG. In this figure, l is the main processor, 3 is a slave processor with a data transfer processing function faster than the main processor l, λ is a data input/output path connecting the main processor / and slave processor J, and tI is within the slave processor. A first-in, first-out memory (FIFO memory) as a data buffer; S is a sequencer that controls data transfer processing within the slave processor; 6 is Fl, a data write strobe signal line to the FO memory reader;
The write enable/disable signal line of the PIF'O memory indicates whether the FO memo IJ q is free and data can be written. t is the data read strobe signal line from the FIFO memory reader. 9 indicates whether data is in the FIFO memory. The data read enable/disable signal line io, which indicates whether data has been written and can be read, is a data bus that sends data read from the FIFO memory. Figure 1 shows the processing flow of main processor l.

FIG. 3 shows the processing flow of the sequencer 3 inside the processor 3, respectively. When the main processor l enters the data transfer processing operation, as shown in FIG.

First, transfer data is prepared, and the FIFO memory's loading enable/disable signal 7 is taken in, and it is determined whether or not loading is possible. If the judgment result is not possible, the judgment operation is repeated until the judgment result becomes ``possible.'' When the judgment result becomes ``writeable,'' the main processor 1 loads the prepared data onto the input/output passcode and sends it to the data write strobe signal line 6. A strobe signal is output to read the transfer data into the FIFO memory 9. After this, it is determined whether there is still data to be transferred based on the internal flag data of the main processor L, and if there is data to be transferred, the above transfer process operation is repeated, and if there is no data to be transferred, the data transfer process is performed. finish.

On the other hand, the operation of the slave processor 3 is as follows.

As shown in Figure 3, the processing flow is as follows: Sequencer! While on standby, the signal # indicates whether or not KFIFO memory can be read.
i! The sequencer S sends out a data read strobe signal to the data read strobe signal line j to the FIFO memory reader when reading is possible. The data is read out through the data nozzle 10, and processes 7 to N are performed depending on the content of the read data. Each of these processes has a different processing time, and after performing the process/~N, it returns to the standby state and repeats the above-mentioned processing operation.

In the conventional asynchronous data transfer method between the main processor and the slave processor, data transfer processing is performed as described above, so unless the processing in the slave processor 3 is relatively long, the FIFO memory reader can write. Despite this, the main processor always performs data transfer only after going through a processing routine to determine whether it is possible to omit data to the FIFO memory reader. In other words, data transfer processing in a main processor that is performing other data processing is performed only at a slow frequency even under normal circumstances, and furthermore, data transfer processing in a slave processor that exclusively performs data transfer processing is free. Even though the FIF○ memory register is always fast enough to store data, the main processor's temperature is %FI for 7 data transfers.
There was a problem in that the data transfer was not performed efficiently until after the processing routine for determining whether or not the data could be transferred to the FO memory p was taken in, and the data transfer was not carried out efficiently.

[Summary of the invention]

SUMMARY OF THE INVENTION The present invention aims to solve the drawbacks of the prior art as mentioned above, and to achieve this purpose, in the present invention, the main processor usually uses the FIFO of the slave processor
Data is transferred without determining whether or not the memory can be written to, and only when it is necessary to determine whether or not data can be written to the FIFO memory, writing to the FIFO memory is possible using the interrupt processing function of the main processor. /I am trying to make a determination that it is not possible. By removing the process of determining whether or not to write to the FIFO memory from the normal data transfer process of the main processor, asynchronous data transfer from the main processor to the slave processor can be performed efficiently.

The characteristic feature of the present invention is that the main processor has an interrupt processing function, and the slave processor operates when the main processor starts data transfer when the The present invention includes an interrupt signal generation circuit that generates an interrupt signal to the processor. This allows the main processor to
Data transfer processing is performed to transfer data to the slave processor without performing a process of determining whether writing is possible or not in the FO memory.

In response to an interrupt signal from the slave processor that is generated when there is no space in the FIFO memory of the slave processor during data transfer, the main processor determines whether or not the FIFO memory can be filled as an interrupt process.

After the FIFO memory becomes empty and it is determined whether the FIFO memory can be loaded, the asynchronous data transfer process is performed such that the data transferred at the time of the interrupt signal generation is retransmitted, and then the process returns to the normal data transfer process.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 9 is a system configuration diagram between a main processor and a slave processor showing an embodiment of the present invention, and FIG. 5 is a flowchart of data transfer processing in the main processor according to an embodiment of the present invention. The left side of FIG. 5 shows the flow of normal data transfer processing, and the right side of FIG. 3 shows the flow of interrupt processing.

In FIG. 9, l is the main processor, 2 is the data input/output bus, 3 is the slave processor, and Tei is the first-in first-out memory (F
IFO memory), S is sequencer.

6 is a data write strobe signal line, 7 is a data write enable/disable signal line to the FIFO memory, t is a data read strobe signal line from the FIFO memory, 9 is a FIFO memory
The data read enable/disable signal line IO from the memory is a data bus. These 1 to 10 are the same as the system shown in FIG. /'/ is an interrupt signal line, 7.2 is a reset signal line for the interrupt signal, and /3 is a data valid signal line provided to synchronize the interrupt signal generation circuit. High level while data is being presented on the output bus. /Hiro and /S are D
a Mitsu flip flop, flip bronze/F forced set terminal and forced reset terminal and flip flop 1
The forced set terminal 3 is always kept at a high level by the inverter 1. /6 and /ri are inverters, and /za is an AND gate. The inverter 17 inverts the logical value of the data write enable/disable signal to the F memory F○ memory and transmits it to the data input terminal of the flip-flop /lI.

AND gate ig takes the logic of the condition for writing data to the FIFO memory.

FIG. 3 is a processing flow diagram showing the operation of the main processor of the asynchronous data transfer system according to the present invention.

The operation of the system shown in FIG. 9 will be explained with reference to FIG.

The main processor l is set to an enable mode in which it can accept interrupts at the beginning of data transfer processing.

Data is transferred to the FIFO memory without determining whether or not the data can be written to the FIFO memory.
Write one after another. In this case, the FIFO memory q is empty and a data write enable signal is output, but the main processor l does not perform any determination processing. The slave processor 3 sequentially executes short processing, relatively long processing, etc. according to the data received in the FIFO memory IJ 41. For this reason, data that requires long processing is repeatedly processed through FI.
If received in FO memory q, FIFO memo IJ
As the frequency of writing to q becomes higher than the frequency of reading, the FIFO memory φ gradually becomes less empty, and at some point the FIFO memory becomes empty, and the FIFO memory is writable/unable. It becomes a low level indicating the condition. This state is provided as a data input to flip-flop /4Z through inverter 17, and as will be described later, an interrupt signal // is generated when main processor l attempts to write further data. The write disable signal of the FIFO memory reader is given as the data input of the flip-flop through an inverter, and the data valid signal 1, which is always output in synchronization with the data sent out at the time of data writing, is set by the flip-flop. Ru.

- The data write strobe signal 6 is output a little later than the leading edge of the evening valid signal 13, and an attempt is made to write data to the FIFO memory register. The logic condition of gate 1g is not satisfied, and data writing to FIFO memory IJF is interrupted by the priest.

Also, the leading edge of the data write strobe signal 6 flip-flops /! r is set to generate an interrupt signal l/ to the king processor l. In response to the interrupt signal // generated in this way, the main processor I starts interrupt processing as shown on the right side of FIG. This interrupt processing first masks the interrupt so that it will not accept other interrupts even if another interrupt factor occurs.Next, since the ℃ interrupt has been accepted for the slave processor 3, an interrupt reset signal /2 is sent. Send out. In this interrupt processing, as in the system of FIG. 1, the IcFIFO memory ≠ loading enable/disable signal is taken in and a 1 determination is made. If the result of the determination is not possible, the determination operation is repeated until the result of writing 1 is reached, and when the result of determination 1 becomes write pi, the main processor/
Rewrite the same data that was sent when the interrupt signal was generated.

The interrupt processing is completed with the interrupt enable processing that allows the interrupt to be received, and the process returns to the original data transfer processing. Note that rewriting #
, a flip-flop l is connected at the leading edge of the data valid number 13
lI has been reset, and the condition for loading into the FIFO memory is satisfied in the AND gate tg. The operation of the sequencer 5 is the same as the operation processing flow shown in FIG.

The process to issue the interrupt reset signal within the above interrupt process is as follows:
The process of generating the 1-interrupt reset signal may be omitted by applying a signal synchronized with the acquisition of the write enable/disable signal of the FIFO memory to the reset signal 7.2. Further, in the slave processor, the sequencer on the left side is used to read data from the FIFO memory, but instead of the sequencer, a microprocessor having a processing speed equivalent to or higher than the sequencer may be used.

〔Effect of the invention〕

As explained above, this invention eliminates the process of determining whether or not to interrupt the FIF○ memory, which is always performed, from the normal process due to the asynchronous data transfer process between the main processor and the slave processor. Imprint processing is performed only when the FIFO memory, which does not require immediate data writing, is full, so the normal data transfer processing speed can be increased.

You can transfer data efficiently and.

The efficiency of the system as a whole is improved.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram of a conventional asynchronous data transfer method, Figure 1 is a processing flow diagram of the operation of the main processor in the system in Figure 1, and Figure 3 is a processing flow diagram of the operation of the slave processor in the system in Figure 1. FIG. 5 is a flowchart showing a system configuration of an asynchronous data transfer method which is an example of the present invention, and FIG. 5 is a processing flow diagram illustrating the processing operations of the main processor of the system shown in FIG. In the figure, / is the main processor, ko is the data input/output bus, 3+ is the slave processor, and da is the first-in first-out memory (F
IFO memory), the sequencer on the left, 6 the data write strobe signal line, 7 the write enable/disable signal line, and the data read strobe signal line. Is it 39? , output enable/disable signal line, 10 is data node. /l is an interrupt signal line, and l is an interrupt reset signal line. /3 is a data valid signal line, /Hiro and /Yu are D-type frisopflossos /le and /ri are inno(-ta). /S is an AND gate.In addition, the same symbol in the figure is the same - or the half. The part is shown. 1st figure, 3rd figure, 4th figure, procedural amendment “Spontaneous” Showa year, month, day 6'1.3.12

Claims (1)

[Claims] An asynchronous data transfer method between a main processor and a slave processor that is equipped with first-in, first-out memory as a data buffer and performs data transfer processing faster than the main processor, in which the main processor has an interrupt processing function and the slave processor has first-in, first-out memory. The main processor is equipped with an interrupt signal generation circuit that generates an interrupt signal to the main processor when the main processor starts data transfer when a data write disable signal is generated when there is no space in the main processor.
Data transfer processing is performed to transfer data to the slave processor without determining whether or not writing is possible in the first-in, first-out memory, and an interrupt signal from the slave processor occurs when there is no space in the slave processor's first-in, first-out memory during data transfer. , the main processor determines whether or not the first-in, first-out memory is writable as an interrupt process, and after determining that the first-in, first-out memory is writable, retransmits the data transferred when the interrupt signal is generated, and then returns to normal data transfer processing. An asynchronous data transfer method.