JPH07129368A - Pulse masking circuit - Google Patents

Abstract

PURPOSE:To provide a pulse masking circuit capable of surely executing writing until FIFO capacity is filled and surely executing reading until the FIFO capacity is filled up without generating an incomplete pulse. CONSTITUTION:A full flag indicating the full state of FIFO capacity is inputted to an FF1, an output from the FF1 is inputted to an OR circuit 3 for outputting a masked writing pulse, a writing pulse is inputted to the clock terminal of the FF1, the OR circuit 3 and the reset terminal of an FF2, and an output from the FF2 is inputted to an OR circuit 4 for outputting a masked reading pulse. A reading pulse is inputted to the clock terminal of the FF2, the OR circuit 4 and the reset terminal of the FF1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out buffer (hereinafter referred to as FiFo) used for data transfer between two data write / read logic processing circuits which operate on different time axes. The present invention relates to an improvement of a pulse mask circuit that masks a write pulse to a FiFo by using a full flag indicating that the capacity is full, and masks a read pulse by using an empty flag indicating that the FiFo becomes empty.

Two, which operate on different time axes,
FiFo is generally used for data transfer between logical processing circuits capable of writing and reading data (such as when a CPU reads a certain logical processing result like a CPU interface circuit), and absorbs the operation time difference. However, in this FiFo state, if the data is written to the full capacity, the writing is prohibited, and if the state becomes empty, unless the reading is prohibited, the data is overwritten and the data is destroyed. .

In order to prevent this, a pulse mask circuit for masking the write pulse to the FiFo by using the full flag indicating that the capacity is full and for masking the read pulse by using the empty flag indicating that the FiFo is empty. However, it is demanded that the pulse mask circuit does not generate an incomplete pulse and can surely write until the capacity is full and surely read until the time becomes empty.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional data transfer system using a pulse mask circuit. (A), (B) and (C) of the time chart of FIG.
It corresponds to points b and c.

In FIG. 6, data is transferred from the logic processing circuit 20 to F
This is a data transfer system in which the CPU 22 reads out the data written in the iFo 21 and the data written in the FiFo 21, and the logic processing circuit 20 sends the write pulse as shown in (A) of [A] and the data to be written to the FiFo 21 and writes it.
22 is a FiF read pulse as shown in (A) of [A]
Send the data to O21 and read the written data.
When the capacity of o21 becomes full, the FiFo21 outputs the full flag a little later than the falling edge of the write pulse as shown in (B) of [A] and inputs it to the OR circuit 23 which is a pulse mask circuit to mask the write pulse [ A]
The writing pulse as shown in (C) is input to the FiFo 21.

[0006] Moreover, when FiFo21 becomes empty, FiFo
21 outputs the empty flag a little later than the trailing edge of the read pulse as shown in (B) of [A] and inputs it to the OR circuit 24 which is a pulse mask circuit to mask the read pulse [A] (C The read pulse is input to the FiFo 21 as shown in FIG.

In this way, when the capacity of the FiFo 21 becomes full, no write pulse is input to the FiFo 21,
When the FiFo 21 becomes empty, no read pulse is input to the FiFo 21.

In this case, [A] is slightly delayed from the trailing edges of the write pulse and the read pulse shown in (A).
When the full flag and the empty flag shown in (B) are input to the OR circuits 23 and 24, if the pulse widths of the write pulse and the read pulse are, for example, 5 ns, the incomplete as shown in (A) (C). Write pulses using time constant circuits 25 and 26 that include capacitors so that pulses are not generated.
Although it is delayed by 5 ns from the falling edge of the read pulse (a delay of this degree is difficult to achieve by simply using a plurality of elements, a time constant circuit is used), but in reality it is 2 ns due to variations in the value of the capacitor. The full flag and the empty flag are output with a delay of about 8 ns.

When the full flag and the empty flag are input to the OR circuits 23 and 24 with a delay of 5 ns or less from the falling of the write pulse and the read pulse, [A]
From the middle of the pulse shown in (A), the full flag and the empty flag are input to the OR circuits 23 and 24 as shown in (A) and (B), and the pulse width of the pulse width is changed as shown in (A) and (C). Generates a narrow, imperfect pulse.

When an incomplete pulse occurs, writing and reading may not be possible, and writing cannot be surely performed until the capacity is full and reading cannot be surely performed until the capacity becomes empty.
In addition, when the full flag is output, when the read pulse is input, the output of the full flag must be stopped, when the empty flag is output, and when the write pulse is input, the output of the empty flag must be stopped. In the case of FIG. Is going.

[0011]

As described above, in the conventional pulse mask circuit, an incomplete pulse may be generated and writing or reading may not be possible. Therefore, writing is surely performed until the capacity is full. There is a problem that the reading cannot be surely performed until it becomes.

The present invention does not generate an imperfect pulse and
It is an object of the present invention to provide a pulse mask circuit that can surely write until the iFo becomes full in capacity and can surely read out until it becomes empty.

[0013]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, a full flag indicating that the capacity of FiFo is full is flip-flop (hereinafter referred to as F
1), the output of FF1 is input to the OR circuit 3 that outputs a masked write pulse, and the write pulse is input to the clock terminal of FF1 and the OR circuit 3 and FF2.
To the reset terminal of FF2, the empty flag indicating that the FiFo is exhausted is input to FF2, the output of FF2 is input to the OR circuit 4 that outputs a masked read pulse, and the read pulse is input to FF2. The clock terminal and the OR circuit 4 and the reset terminal of the FF1 are input.

[0014]

According to the present invention, the full flag, which is output a little later than the falling edge of the write pulse, is input to FF1.
At the rising edge of the write pulse, it is output from the FF1 and input to the OR circuit 3, and the OR circuit 3 masks and outputs the input write pulse, so that an incomplete write pulse is not generated, and A masked write pulse is output.

The empty flag which is output a little later than the trailing edge of the read pulse is input to FF2, is output from FF2 at the leading edge of the read pulse, and is input to the OR circuit 4, and is input to the OR circuit 4. Since the read pulse that is being output is masked and output, an incomplete read pulse is not generated, and a completely masked read pulse is output.

That is, an incomplete pulse is not generated, and FiF
Writing can be surely performed until o becomes full, and reading can be surely performed until o becomes full. Since the FF1 is reset at the falling edge of the read pulse, the full flag is not output until the next full flag is input when the read pulse is input, and the FF2 is reset at the falling edge of the write pulse. When the write pulse is input, it is not output until the next empty flag is input.

[0017]

FIG. 2 is a block diagram of a pulse mask circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of each part of FIG. 2 and (A) to (I) correspond to points a to i of FIG. There is.

FIG. 4 is a block diagram of a pulse mask circuit according to another embodiment of the present invention, and FIG. 5 is a time chart of each part of FIG. 4, and (A) to (O) correspond to points a to o of FIG. ing. The following description will be made assuming that when two write pulses are continuously input, the FiFo becomes full, and when two read pulses are continuously input, FiFo becomes empty.

In the initial stage of FIG. 2, the reset pulse shown in FIG. 3A is input, the FF2 is set, and the output of the FF2 is set to the H level as shown in FIG. FF1 is reset and the output of FF1 is shown in FIG.
Set to L level as shown in.

Next, when two write pulses are input as shown in FIG. 3B, FiFo outputs a full flag to FF1 as shown in FIG. 3D, a little later than the trailing edge of the second write pulse. input.

Since the write pulse is input to the clock terminal of FF1, the output of FF1 becomes H level at the rising edge of the second write pulse as shown in FIG. 3 (F), and is input to the OR circuit 3. To do.

Since the write pulse is input to the OR circuit 3, the output of the OR circuit 3 is as shown in FIG.
Two complete write pulses are output and output. Next, when the read pulse shown in FIG. 3 (C) is input, the full flag is not output at the rising edge of the read pulse, but FF1 is reset at the falling edge of the read pulse, and the output of FF1 is shown in FIG. 3 (F). It becomes the L level.

When two read pulses are input, FiFo
Outputs an empty flag as shown in FIG. 3 (E) and inputs it to the FF 2 with a little delay from the second fall. FF
Since the read pulse is input to the clock terminal of 2, the output of the FF2 becomes H level as shown in FIG. 3 (G) and is input to the OR circuit 4.

Since the read pulse is also input to the OR circuit 4, the output of the OR circuit 4 becomes two complete read pulses as shown in FIG. Next in FIG.
When the write pulse shown in (B) is input, the empty flag is not output at the rising edge of the write pulse, but FF2 is reset at the falling edge of the write pulse, and the output of FF2 is L level as shown in FIG. It becomes a level.

When two write pulses are input, FiFo
Outputs a full flag as shown in FIG. 3 (D) and inputs it to FF1 at a slight delay from the second fall, and outputs an H level as shown in FIG. 3 (F) at the rising edge of the write pulse. When a read pulse is input to the FF1 as shown in FIG. 3C, the FF1 is reset at the trailing edge of the read pulse, so that the output of the FF1 becomes the L level as shown in FIG. The output of the circuit 3 outputs two complete write pulses as shown in FIG. 3 (H), and the output of the OR circuit 4 outputs a read pulse as shown in FIG. 3 (I).

That is, when the FiFo outputs the full flag and the empty flag, an incomplete pulse is not generated, and writing can be surely performed until the capacity of the FiFo is full, and reliable reading can be performed until it becomes empty.

It should be noted that the output of the full flag is stopped when the read pulse is input, and the output of the empty flag is stopped when the write pulse is input, which has been conventionally performed by FiFo, but this is also performed by the pulse mask circuit of FIG. , Fi
You don't have to do it at Fo.

FIG. 4 shows a high speed at which rising and falling of the write pulse and the read pulse can be detected.
4 is a pulse mask circuit that operates in synchronization with the clock pulse shown in FIG. 4, and is the same as the pulse mask circuit of FIG. 4 in principle. FIG. 5 shows a write pulse, a full flag, a read pulse, and an empty flag from FiFo. Is a time chart in the case of being output as in FIG.

The rising edge detection circuit 8 and the falling edge detection circuit 11 shown in FIG. 4 detect the rising edge and the falling edge of the write pulse shown in FIG. 5 (B) as shown in FIGS. 5 (M) and 5 (D). Then, the output of the rising edge detection circuit 8 becomes as shown in FIG. 5 (E) through the AND circuit 6 in which the full flag shown in FIG. 5 (C) is input, and is input to the J terminal of the JKFF 12 to fall. The output of the detection circuit 11 is input to the K terminal of the JKFF 13.

In the rising edge detection circuit 9 and the falling edge detection circuit 10 shown in FIG. 4, the rising and falling edges of the read pulse shown in FIG. 5 (H) are changed as shown in FIGS. 5 (J) and 5 (G). The output of the rising edge detection circuit 9 is detected by JKFF12.
5 and the output of the fall detection circuit 10 is as shown in FIG.
Through the AND circuit 7 to which the empty flag shown in (I) is input, the state shown in FIG.
Input to the J terminal of 3.

Then, the output of the JKFF 12 becomes as shown in FIG. 5 (F), which is input to the OR circuit 14 together with the write pulse shown in FIG. 5 (B), and the masked write pulse shown in FIG. 5 (N) is output from the output. Then, the output of the JKFF 13 becomes as shown in FIG. 5 (L), and it is input to the OR circuit 15 together with the read pulse shown in FIG. 5 (H).
A masked read pulse as shown in (O) is output.

That is, the masked write pulse and the masked read pulse are FiFo as in the case of FIG.
When the full flag and the empty flag are output, an incomplete pulse is not generated, and writing can be surely performed until the capacity of FiFo is full, and reliable reading can be performed until it becomes empty.

[0033]

As described above in detail, according to the present invention, when the FiFo outputs the full flag and the empty flag,
An incomplete pulse is not generated, and there is an effect that writing can be surely performed until the capacity of the FiFo becomes full, and reading can be surely performed until it becomes empty.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of a pulse mask circuit according to an embodiment of the present invention,

FIG. 3 is a time chart of each part of FIG.

FIG. 4 is a block diagram of a pulse mask circuit according to another embodiment of the present invention,

5 is a time chart of each part of FIG. 4,

FIG. 6 is a block diagram of a data transfer system using a conventional pulse mask circuit.

[Explanation of symbols]

 1, 2, 12, 13 are flip-flops, 3, 4, 14, 15 are OR circuits, 5, 6, 9 are AND circuits, 8 and 9 are rising detection circuits, 10 and 11 are falling detection circuits, and 20 is A logical processing circuit, 21 is a first-in first-out buffer, 22 is a CPU, and 25 and 26 are time constant circuits.

Claims (1)

[Claims] 1. A full flag indicating that the capacity of the first-in first-out buffer is full is input to a first flip-flop (1), and an output of the first flip-flop (1) is supplied with a masked write pulse. Outputting first OR circuit (3)
To the clock terminal of the first flip-flop (1) and the reset terminals of the first OR circuit (3) and the second flip-flop (2), and the first-in first-out buffer An empty flag indicating that the power supply is open is input to the second flip-flop (2), and an output of the second flip-flop (2) is output as a second OR gate that outputs a masked read pulse. The read pulse is input to the circuit (4) and is input to the clock terminal of the second flip-flop (2) and the reset terminal of the second OR circuit (4) and the first flip-flop (1). A pulse mask circuit characterized in that