JPS61156886A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the gain characteristic by reducing the gate length and increasing the cross-sectional area by a method wherein a resist formed on the surface of a gate electrode is etched wider than the gate electrode to the degree of no reach of the operating layer into the exposure of the surface of the gate electrode, where a metal is deposited by plating. CONSTITUTION:An operating layer 1 on a buffer layer 5 is removed except the necessary part, and ohmic electrodes serving as a source electrode 3 and a drain electrode 4 and an electroplating projection 3a are formed. Next, a gate electrode 2 is formed between the source and drain electrodes 3, 4 on top of the operating layer 1. A bonding pad 2c short-circuits with said projection 3a of the source electrode 3. The surface of the gate electrode 2 is exposed by removing the resist layer 7 applied over this electrode 2. Since the gate length is short and the gate resistance is low, the increase in gain of the FET can be contrived.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses GaAs having a short gate length and low gate resistance.
The present invention relates to a method of manufacturing a semiconductor device for obtaining an FUT.

In order to promote higher gain of GaAsFETs, it is necessary to shorten the gate length, but on the other hand, shortening the gate length also reduces the cross-sectional area of the gate electrode.

Since the gate resistance increases, the gain characteristics are suppressed. Therefore, there is a problem that gate length and gate resistance conflict with each other in improving gain characteristics.

Also, in high output devices.

Electromigration of the gate electrode occurs.

In some cases, the wire may be disconnected.

[Conventional technology]

Therefore, as shown in FIG. 2, the gate electrode 2 formed on the upper part of the active layer 1 shortens the gate length of the narrow portion 2a that contributes to transistor operation.

A gate electrode having a short gate length and a large cross-sectional area is obtained by increasing the cross-sectional area of the wide portion 2b that operates as a power feeding portion. The manufacturing method for obtaining the gate electrode 2 having a T-shaped cross-section as shown in FIG. 2 is to form the gate electrode into a multilayer structure, and then thin the bottom layer of metal by undercutting, which will be subjected to the horizontal-to-retky bonding. How to do it.

By a multilayer resist method, a narrow portion 2a having a small cross-sectional area was first formed by vapor deposition using one resist pattern, and then a cross-sectional area was formed using another resist pattern.

[Problem to be Solved by the Invention] Among the above-mentioned conventional methods, in the former method, when forming the narrow part 2a by etching the lowest metal layer, Moreover, it is difficult to control the amount of etching.

There was a problem in that the vicinity of the Schottky junction between the gate electrode 2 and the active layer 1 was contaminated by the etching solution. Furthermore, since the latter method uses a plurality of resist patterns, it is difficult to improve the alignment accuracy of the resist patterns.

[Means to solve the problem]

In view of the above conventional problems, the present invention provides a method for manufacturing a semiconductor device in which the amount of etching can be easily controlled, Schottky junctions are not contaminated by etching liquid, and resist pattern alignment is easy. The purpose is to

According to the present invention, a step of forming an active layer and source, drain, and gate electrodes on a semiconductor substrate;

forming an insulating film on the surface of the substrate; etching a region of the insulating film on the gate electrode so as to expose the surface of the gate electrode but not the active layer; and etching the exposed gate. The present invention provides a method for manufacturing a semiconductor m, which comprises a step of attaching a plating layer to the surface of an electrode.

[For production]

In the present invention, a portion of the resist formed on the surface of the gate electrode is etched to an extent that does not reach the active layer to expose the surface of the gate electrode, and a metal is plated onto the surface of the gate electrode. In other words, the cross-sectional area of the portion of the gate electrode that contributes to the operation of the gate electrode is reduced by shortening the gate length, and the cross-sectional area of the portion of the gate electrode away from the active layer is increased by plating with metal. This makes it possible to easily manufacture FETs with improved gain characteristics. That is, patterning of the resist to expose the surface of the gate electrode can be done in a region including and surrounding the gate electrode but not reaching the source and drain electrodes, so patterning of the resist is easy. .

The etching of the resist may be done within a range that does not reach the active layer, so there is no need to control the etching time with high precision. Furthermore, metal plating is attached to the surface of one gate electrode.

The etching solution will not contaminate the Schottky junction due to undercutting of the gate electrode.

〔Example〕

FIG. 3(a) is an example of a chip pattern of an FET, and FIG. 3(a) is a cross-sectional view thereof. 1 is an N-type active layer, 2 is a gate electrode, and 2C is a bonding bat formed by forming one end of the gate electrode 2 wide. 3
is a source electrode, which is formed so as to partially overlap the upper part of the active layer 1, and is ohmically connected to AuGe/Au, and extends to a region along the outer periphery of the chip. 4 is a drain electrode, a part of which is connected to the active layer 1. The source electrode 3 is formed so as to overlap with the upper part of the gate electrode 2 to form an ohmic connection of AuGe/Au.
are provided so as to face each other via the and.

5 is a non-doped buffer layer formed by epitaxial growth, and 6 is a semi-insulating GaAs substrate.

Next, FIGS. 4 to 7 and 1t! An embodiment of the semiconductor manufacturing method of the present invention will be described with reference to FIG.

In each figure of FIG. 1, FIG. 4, FIG. 5, FIG. 6, and FIG. 7, (a) is a top view of a chip pattern.

弽) is its cross-sectional view.

First, by removing non-necessary portions of the active layer 1 on the buffer ii5 with a thickness of 3 to 4 μm, for example,
The ohmic electrodes, which will become the source electrode 3 and the drain electrode 4, are formed to have a thickness of 4,000 ohms, for example, of AuGe/Au. At this time, the operating layer 1
An electrolytic plating protrusion 3a is formed in a portion other than that, for example, so as to extend from the chip peripheral portion of the source electrode 3.

Next, as shown in FIGS. 5(a) and 5(b), the operating layer 1
On the upper surface of the gate electrode 2, the gate electrode 2 is formed by using a known lift-off method or the like, with a space between the source electrode 3 and the drain electrode 4, for example, Ti/Pt/Au/0.
Formed at 3/0.1/0.5 μm. The bonding bat 2C formed to extend beyond the upper surface of the active layer 1 of the gate electrode 2 is connected to the protrusion 3 for electrolytic plating of the source electrode 3.
It is shorted to a. Further, the gate length of the gate electrode 2 is formed to be, for example, 0.5 μm.

Next, as shown in FIGS. 6(al) and (bl), a resist 7 is applied to the entire surface. At this time, the thickness of the applied resist 7 (A) on the gate electrode 2 is determined by the shape effect. 0
．． The peripheral part (B) of the gate electrode 2 has a thickness up to the active layer 1, so it is as thin as 2 μm, and is as thick as 0.8 μm. and,
Including the upper surface of the gate electrode 2.

Only the exposure region 8 (the shaded region in the figure) that does not cover the source electrode 3 and drain electrode 4 is exposed. The exposure amount at this time is about 1 normal Z. And 2
If normal development is performed, as shown in FIG. 7, the resist layer 7 on the gate electrode 2 will be removed, and the resist layer 7 on the periphery of the gate electrode 2 will be removed.

It is removed to the extent that it does not reach the active layer 1. Therefore, the surface of the gate electrode 2 is exposed.

Next, the source electrode 3 is made of a conductive film with a thickness of 0.5 μm.
Perform electroplating of u. Then, the Au plating starts from the top of the gate electrode, and as shown in FIG. After the electroplating is completed, the resist layer 7 is removed, and the portion of the plating protrusion 3a of the source electrode 3 that does not overlap with the pounding butt 2c,
That is, the portion indicated by the dotted line in FIG. 1(a) is removed by etching to disconnect the gate electrode 2 and source electrode 3. Then, a SiN thin film layer 9 is formed on the surface of the substrate 9 as a passivation protective film. by this,
It has a source electrode 3, a drain electrode 4, a gate electrode 2, and an N-type operation ri11, and the gate electrode 2 has a wide part 2b that contributes to power supply and a narrow part 2a that contributes to transistor operation. A FET can be formed.

In the above embodiment, the patterning of the exposed region 8 does not require a high degree of precision, and even when the resist layer 7 is etched to expose the surface of the gate electrode 2, the etching speed must be strictly controlled. Moreover, since the U plating starts from the top of the gate electrode 2, alignment for forming the wide portion 2b of the gate electrode 2 is not necessary. Furthermore, since the etching solution does not reach the Schottky junction between the gate electrode 2 and the active layer 1, the Schottky junction is not contaminated.

In addition, in the above embodiment, a portion of the gate electrode is made of ^Ge.
/Au/Ti/Pt/^U is formed, but since it is a part other than the active layer 1, it has no effect on the Schottky characteristics or the like.

〔Effect of the invention〕

According to the present invention, an FET that can achieve high gain due to its short gate length and low gate resistance can be fabricated using a single shot method, in which resist pattern alignment is easy and resist etching speed does not need to be controlled with high accuracy. It is possible to provide a method of manufacturing a semiconductor device that can be manufactured without contaminating key junctions with etching liquid.

[Brief explanation of drawings]

1A and 1B are a plan view and a sectional view, respectively, for explaining the final step of the semiconductor manufacturing method according to the present invention. FIG. 2 is a sectional view showing an ideal gate electrode. (fi), (b) to Figure 6 (a), (b)
1A and 1B are a plan view and a cross-sectional view, respectively, for explaining each step of the method for manufacturing a semiconductor device according to the present invention. FIG. 7 is a cross-sectional view showing the steps of semiconductor manufacturing according to the present invention. 2...Gate electrode 2a...Narrow portion 2b...Wide portion 2c...Ponding pad. 3...Source electrode 3a...Plating protrusion 4...Drain electrode Attorney Hiroshi Matsuoka 1st
Figure and 2 Figure 3 Figure 4 Figure 5 (Q)

Claims (1)

[Claims] A step of forming an active layer, a source, a drain, and a gate electrode on a semiconductor substrate, a step of forming an insulating film on the surface of the substrate, and a step of forming an insulating film on the gate electrode so that the surface of the gate electrode is exposed. A method for manufacturing a semiconductor device, comprising the steps of: etching the active layer so as not to expose it; and depositing a plating layer on the exposed surface of the gate electrode.