JP2003046094A - Schottky barrier diode and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the conventional problem of there being no improvements in shrinkage of a chip, due to the existence of a mesa etching layer and a thick polyimide layer or the like, and characteristics being unable to be improved due to a distance between electrodes, and etching being difficult to control in a Schottky junction section in the manufacture. SOLUTION: By forming an InGaP layer and an n<+> -type ion implanted region in the surface of a substrate, there is no need to form the mesa and the polyimide layer, leading to realization of a compound semiconductor planar type Schottky barrier diode. Since the distance between electrodes can be shortened, chip shrinking can be realized and high-frequency characteristics can be improved. When forming a Schottky electrode, since GaAs is not etched and results in the manufacture of a Schottky barrier diode with good reproducibility.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor Schottky barrier diode used in a high-frequency circuit and a method for manufacturing the same, and more particularly to a compound semiconductor in which an operating region and a chip size are reduced by adopting a planar structure. Of Schottky barrier diode and manufacturing method thereof.

[0002]

2. Description of the Related Art In addition to the expansion of the global mobile phone market, the demand for high frequency devices has been rapidly increasing as the demand for digital satellite broadcasting receivers has increased. As an element thereof, a field effect transistor using gallium arsenide (GaAs) is often used because it handles high frequencies, and along with this, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated, The development of a local oscillation FET is under way.

Demand for GaAs Schottky barrier diodes is also increasing for base stations.

FIG. 9 shows a cross-sectional view of the operating region of a conventional Schottky barrier diode.

An n + type epitaxial layer 22 (5 × 10 ¹⁸ cm ⁻³ ) is laminated on the n + type GaAs substrate 21 to a thickness of about 6 μm, and an n type epitaxial layer 23 (1.
3 × 10 ¹⁷ cm ⁻³ ) is deposited, for example, on the order of 3500 Å.

The first metal layer which becomes the ohmic electrode 28 is AuGe / Ni / Au which makes ohmic contact with the n + type epitaxial layer 22. The second metal layer is T
i / Pt / Au, and there are two types of patterns of the second metal layer, that is, the anode side and the cathode side. A Schottky junction is formed with the n-type epitaxial layer 23 on the anode side. The second metal layer on the anode side having the Schottky junction region 31a is referred to as a Schottky electrode 31 below.
Called. The Schottky electrode 31 also serves as a base electrode of the third Au-plated layer forming the anode bonding pad, and both patterns completely overlap. The second metal layer on the cathode side is in contact with the ohmic electrode and further serves as a base electrode for the third Au plating layer forming the cathode bonding pad, and both patterns are completely overlapped as with the anode side. The Schottky electrode 31 is
Since it is necessary to dispose the end position of the pattern on the upper surface of the polyimide layer, patterning is performed so as to overlap the 16 μm cathode side around the Schottky junction region 31a. The substrate other than the Schottky junction has a cathode potential, and the anode electrode 34 and the cathode have a Ga potential.
A polyimide layer 30 is provided at the intersection with As for insulation. The area of this intersection is 1300 μm
^The parasitic capacitance is about ² and has a large parasitic capacitance. Therefore, it is necessary to reduce the parasitic capacitance by setting the separation distance to a thickness of about 6 to 7 μm. Polyimide has a low dielectric constant,
It is used as an interlayer insulating layer because it can be formed thick.

The Schottky junction region 31a is 1.3 in order to secure a withstand voltage of about 10 V and good Schottky characteristics.
× provided on 10 ¹⁷ cm ^-3 of about n-type epitaxial layer 23. On the other hand, the ohmic electrode 28 is provided on the surface of the n + type epitaxial layer 22 exposed by the mesa etching in order to reduce the extraction resistance. Further, the lower layer of the n + type epitaxial layer 22 is a high-concentration GaAs substrate 21, and AuGe / Ni / Au, which is an ohmic electrode 28, is provided as a backside electrode, and it is possible to support a model taken out from the backside of the substrate. Has become.

FIG. 10 shows a plan view of a conventional compound semiconductor Schottky barrier diode.

A Schottky junction region 31a is formed on the n-type epitaxial layer 23 at approximately the center of the chip. This region has a circular shape with a diameter of about 10 μm, and Ti / Pt / Au, which is the second metal layer, is sequentially deposited in the Schottky contact hole 29 exposing the n-type epitaxial layer 23. Circular Schottky junction area 31
An ohmic electrode 28, which is a first metal layer, is provided so as to surround the outer periphery of a. The ohmic electrode 28 is made of AuGe.
/ Ni / Au is sequentially deposited, and is provided in a region close to half of the chip. Further, in order to take out the electrode, the second metal layer is brought into contact with the ohmic electrode 28 to form a base electrode.

The base electrodes on the anode side and the cathode side are provided for the Au plating layer which is the third layer. The anode side is provided in a minimum area necessary for bonding with the Schottky junction region 31a, and the cathode side is patterned in a shape surrounding the outer periphery of the circular Schottky junction region 31a. Further, in order to reduce the inductor component, which is a factor of high frequency characteristics, it is necessary to fix a large number of bonding wires, and for this reason, a region that occupies about half of the chip is a bonding region.

Further, an Au plating layer is provided so as to overlap the base electrode. The bonding wire is fixed thereto by stitch bonding, and the electrode is taken out. The anode bonding pad portion is 40 × 60 μm ² and the cathode bonding pad portion is 240 × 70 μm ² . In the connection by stitch bond, two bonding wires can be connected by one bonding,
Even if the bonding area is small, the inductor component, which is a parameter of high frequency characteristics, can be reduced, which contributes to the improvement of high frequency characteristics.

11 to 15 show a conventional method of manufacturing a Schottky barrier diode.

In FIG. 11, the n + type epitaxial layer 22 is exposed by mesa etching, and the first metal layer is attached to form the ohmic electrode 28.

That is, an n + type epitaxial layer 22 (5 × 10 ¹⁸ cm ⁻³ ) is deposited on the n + GaAs substrate 21 to a thickness of about 6 μm, and an n type epitaxial layer 23 (1.3
× 10 ¹⁷ cm ^-3 ) is deposited at about 3500 Å. After that, the entire surface is covered with an oxide film 25, and a photolithography process of selectively opening a resist layer on a predetermined ohmic electrode 28 is performed. Then, the oxide film 25 in the planned ohmic electrode 28 portion is etched using this resist layer as a mask, and mesa etching of the n-type epitaxial layer 23 is further performed so that the n + -type epitaxial layer 22 is exposed.

After that, AuGe, which is the first metal layer, is formed.
/ Ni / Au three layers are sequentially vacuum-deposited and laminated. After that, the resist layer is removed, and the planned ohmic electrode 28 is formed.
Leave a metal layer on the part. Subsequent to the alloying heat treatment, n
An ohmic electrode 28 is formed on the + type epitaxial layer 22.

In FIG. 12, a Schottky contact hole 29 is formed. Form a new resist layer on the entire surface,
A photolithography process is performed to selectively open the intended Schottky junction region 31a. After the exposed oxide film 25 is etched, the resist is removed, and the n-type epitaxial layer 23 in the planned Schottky junction region 31a is formed.
An exposed Schottky contact hole 29 is formed.

In FIG. 13, a polyimide layer 3 for insulation is shown.
Form 0. The entire surface is coated with polyimide several times to form a thick polyimide layer 30. A photolithography process is performed in which a new resist layer is formed on the entire surface and a window is selectively opened so that a predetermined polyimide layer 30 portion remains. Then, the exposed polyimide is removed by wet etching. Then, the resist layer is removed and the polyimide layer 30 is cured to a thickness of 6 to 7 μm.

In FIG. 14, the n-type epitaxial layer 23 exposed in the Schottky contact hole 29 is etched to form a Schottky electrode 31.

The n-type epitaxial layer 23 is etched using the oxide film 25 around the Schottky contact hole 29 as a mask. As described above, after forming the contact hole 29, the polyimide layer 30 is formed with the surface of the n-type epitaxial layer 23 exposed. It is essential that the Schottky junction is formed on a clean GaAs surface. Therefore, before forming the Schottky electrode, the n-type epitaxial layer 23 is formed.
Etch the surface. Furthermore, in order to secure the optimum thickness of 2500Å for the operating layer, the temperature and time are precisely controlled to reduce the thickness from about 3500Å to 25
Wet-etch so that it becomes 00Å.

After that, Ti / Pt / Au is sequentially vacuum-deposited to form a base electrode for the Schottky electrode 31 and the cathode electrode 35, which also serves as a base electrode for the anode electrode.

In FIG. 15, an Au plating layer to be the anode electrode 34 and the cathode electrode 35 is formed.

After exposing the underlying electrodes of the planned anode electrode 34 and cathode electrode 35 portions and covering the others with a resist layer, electrolytic gold plating is performed. At that time, the resist layer serves as a mask, and Au plating adheres only to the exposed portion of the base electrode, whereby the anode electrode 34 and the cathode electrode 35 are formed. The base electrode is provided on the entire surface, and after removing the resist,
Ion milling with Ar plasma is performed, and the base electrode in the portion not plated with Au is scraped off and patterned into the shapes of the anode and cathode electrodes 34, 35. At this time, the Au-plated portion is also slightly scraped, but there is no problem because it has a thickness of about 6 μm.

The back side is back-lapped and AuGe / N
i / Au is sequentially vapor-deposited and alloying heat treatment is performed to form the ohmic electrode 28 on the back surface.

When the compound semiconductor Schottky barrier diode is completed in the pre-process, it is moved to the post-process for assembling. The wafer-shaped semiconductor chip is diced,
After the individual semiconductor chips are separated and the semiconductor chips are fixed to a frame (not shown), bonding pads are used to connect the anode and cathode bonding pads of the semiconductor chips to predetermined leads (not shown). Gold wires are used as the bonding wires, and they are connected by known stitch bonding. After that, transfer molding is performed and a resin package is applied.

[0025]

The substrate structure of the conventional Schottky barrier diode has a structure in which the cathode electrode can be taken out from the back surface so that it can be used for a variety of models. The n + type epitaxial substrate is formed on the n + type GaAs substrate. In order to ensure the predetermined characteristics on the upper layer,
The structure has an n-type epitaxial layer of about 1.3 × 10 ¹⁷ cm ⁻³ .

Since it is necessary for the Schottky electrode to secure a predetermined characteristic, a clean surface of the n-type epitaxial layer is exposed and metal is vapor-deposited to form a Schottky junction. The ohmic electrode reduces the extraction resistance,
An ohmic junction is formed in the + type epitaxial layer.

Here, the conventional structure has the following problems. First, in order to form the ohmic electrode 28, a mesa must be formed to expose the n + type epitaxial layer 22. n-type epitaxial layer 23 is 3
It has a thickness of about 500 Å, and mesa etching is essential to expose the n + type epitaxial layer 22 thereunder. An oxide film 25 for protecting the substrate is provided on the surface of the substrate, and the mesa etching is performed by providing a mask of a photoresist on the surface to perform etching, but the adhesion between the surface of the oxide film 25 and the resist varies. If wet etching is performed in this situation, the etching may spread in the lateral direction more than necessary, and even the required oxide film 25 may be etched. If GaAs is exposed, the shape of the mesa becomes unstable. Therefore, the photoresist at the time of forming the ohmic electrode 28 provided in the opening of the mesa also has a sag in the shape of the peripheral edge portion, and as a result, the shape of the ohmic electrode 28 is deteriorated due to lift-off, or GaAs is Schottky. There is a possibility that a problem may occur in which the vicinity of the junction is etched and the characteristics are adversely affected.

Secondly, most of the anode electrode 34 is provided on GaAs, which has a cathode potential.
There is a problem that the parasitic capacitance here becomes large. Since the area of the intersection is 1300 μm ² , it is essential to reduce the parasitic capacitance with a thick interlayer insulating film. In order to embed the mesa and form a thick interlayer insulating film, a polyimide layer 30 of 6 to 7 μm must be provided. In order to take out the electrode in the Schottky junction region 31a, the polyimide layer 30
Although an opening is provided in the opening, the opening is tapered because of the etching of the thick polyimide layer 30 and also for the purpose of considering the step coverage of the electrode on the polyimide layer 30. However, due to variations in the film quality of the polyimide layer 30 and variations in the adhesion between the polyimide layer 30 and the resist, the taper angle greatly varies from 30 to 45 degrees. Therefore, the separation distance between the Schottky junction region 31a, which is the operation region, and the ohmic electrode 28 needs to be secured at about 7 μm in consideration of the taper. However, since the distance between these junctions contributes to the series resistance, a large distance hinders the improvement of high frequency characteristics,
Furthermore, miniaturization of chips has also been a cause of slow progress.

Thirdly, since a taper is formed in the vicinity of the Schottky junction and the ohmic junction, the thickness of the interlayer insulating film of 6 μm cannot be maintained in the vicinity of the operation region of the Schottky barrier diode, which increases the parasitic capacitance. However, there is also a problem that causes deterioration of characteristics.

Further, the conventional manufacturing method has the following problems.

First, the Schottky junction is a Schottky junction with the uppermost n-type epitaxial layer 23, and has an optimum thickness in consideration of the breakdown voltage and resistance of the operating layer 25.
In order to secure 00Å, etching is performed from the n-type epitaxial layer 23 of about 3500Å to 2500Å. Since the etching at this time is wet etching, it is very difficult to control the time and temperature as well as the swing width and swing speed of the wafer in the etching solution, and the etching solution is used within the predetermined freshness retention time. Is required. Therefore, according to this method, there is a problem that variations occur from wafer to wafer, and it is very difficult to improve the reproducibility of the characteristics of the operating region and the high frequency characteristics.

Secondly, by adopting the mesa structure,
Mesa etching, which requires a number of steps, is necessary, and defects may occur due to variations in the adhesion between the resist and the oxide film. In addition, a step of forming a polyimide layer as an interlayer insulating film or providing an electrode lead-out on the polyimide layer is Au.
A plating forming step and the like are required at the same time, which complicates the manufacturing flow and is not efficient in terms of time.

Since the cost of the substrate itself of the compound semiconductor is high, it is necessary to reduce the cost by shrinking the chip size for rationalization. That is, it is inevitable to reduce the chip size, and it is also desired to reduce the cost of the material itself. At the same time, further improvement in high frequency characteristics is required. Furthermore, it has been an important issue to simplify the manufacturing process and to improve efficiency.

[0034]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a compound semiconductor substrate, a flat epitaxial layer of one conductivity type provided on the substrate, and a stable compound semiconductor layer for protecting the epitaxial layer. A high-concentration ion implantation region of one conductivity type provided on the surface of the compound semiconductor layer, a first electrode that makes ohmic contact with the surface of the high-concentration ion implantation region, and a second electrode that forms a Schottky junction with the surface of the epitaxial layer. And a metal layer for taking out the first and second electrodes, wherein an ohmic electrode is provided on the surface of the high-concentration ion implantation region provided on the surface of the substrate to form a mesa, a polyimide layer, and Au. The plating layer is unnecessary. As a result, a planar Schottky barrier diode of a compound semiconductor can be realized, and the area of the operating portion can be reduced, which contributes to downsizing of the chip size, cost reduction, and improvement of high frequency characteristics due to reduction of parasitic capacitance and resistance. It is a thing.

Further, a one-conductivity type epitaxial layer and a stable compound semiconductor layer are laminated on a non-doped compound semiconductor substrate to form a one-conductivity type high-concentration ion implantation region on the surface of the compound semiconductor layer under the planned first electrode. And a step of forming a first electrode that makes ohmic contact with the surface of the high concentration ion implantation region, and a second step of forming a Schottky contact hole in the compound semiconductor layer and forming a Schottky junction with the surface of the epitaxial layer. The present invention is characterized by including a step of forming an electrode and a step of forming a metal layer in contact with each of the first and second electrodes, thereby realizing simplification and efficiency of the manufacturing process, and further improving high frequency characteristics. A method of manufacturing a Schottky barrier diode that can be provided can be provided.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail with reference to FIGS.

The Schottky barrier diode of the present invention comprises a compound semiconductor substrate 1, a high-concentration epitaxial layer 2, an epitaxial layer 3 and a stable compound semiconductor layer 4, a high-concentration ion implantation region 7, and a first electrode 8. , The second electrode 11 and the metal layers 14 and 15.

FIG. 1 shows a sectional view of the operating region portion.

The compound semiconductor substrate 1 is made of non-doped Ga.
As substrate, 5000Å n + type epitaxial layer 2 (5 × 10 ¹⁸ cm ^-3 ), 2500 Å n type epitaxial layer 3 (1.3 × 10 ¹⁷ cm ^-3 ), and 2
A non-doped InGaP layer 4 of 00Å is laminated. No mesas were formed in any of the layers, and the substrate structure was flat. In addition, the uppermost InGaP layer 4 protects the surface of the n-type epitaxial layer 3 which is susceptible to external contamination.

The high-concentration ion implantation region 7 is provided so as to reach the n + epitaxial layer 2 from the surface of the InGaP layer 4 below the ohmic electrode 8. The Schottky electrode 11 and the high-concentration ion-implanted region are provided along the outer circumference of the circular Schottky electrode 11 so as to substantially overlap the ohmic electrode 8 and to extend from the ohmic electrode 8 in a portion adjacent to the Schottky electrode 11. Distance from 7 is 1μ
m. That is, instead of adopting the conventional mesa structure, the structure is such that the high-concentration ion implantation region 7 is provided on the surface while maintaining the planar structure, and ohmic contact can be realized without providing the mesa.

The ohmic electrode 8, which is the first electrode, is the first metal layer in contact with the high-concentration ion implantation region 7. AuGe / Ni / Au is vapor-deposited in sequence, and a Schottky junction is patterned into a circular shape. The separation distance from the adjacent Schottky electrode 11 is 2 μm.

The Schottky electrode 11 which is the second electrode
Is a second metal layer obtained by sequentially depositing Pt / Ti / Pt / Au or Ti / Pt / Au, and is patterned into a circular shape having a diameter of 10 μm. The n-type epitaxial layer 3 under the InGaP layer 4 and the Schottky Form a bond.

The thickness of the n-type epitaxial layer 3 serving as the operating region is 2500 Å because it is necessary to obtain predetermined characteristics such as withstand voltage.
Is desirable. Here, In on the n-type epitaxial layer 3
By providing the GaP layer 4, the n-type epitaxial layer 3 is made of In until the Schottky electrode 11 is formed.
Protected by the GaP layer 4, a high-quality and highly accurate Schottky junction is obtained with the n-type epitaxial layer 3 of 2500 Å. Moreover, since the InGaP layer 4 is non-doped,
It is possible to suppress the generation of capacitance on the side surface of the Schottky junction formed of the second metal layer.

The metal layer is a vapor-deposited metal layer made of Ti / Pt / Au, which is the third layer serving as the anode electrode 14 and the cathode electrode 15. The anode electrode 14 contacts the Schottky electrode 11, extends to the anode bonding region, and becomes the anode bonding pad 14a. Further, it is insulated from the ohmic electrode 8 or GaAs which is the cathode potential through the nitride film 5.

Below the anode bonding pad portion 14a, there is provided a region 6 (hereinafter referred to as an insulated region) which is insulated by injecting boron or the like. Undoped Ga
Since the GaAs, which is the cathode potential, and the anode electrode 14 can be insulated by the insulating region 6 that reaches the As substrate, the wire bond portion can be directly fixed to the substrate without providing the polyimide and nitride films.

The cathode electrode 15 is provided so as to face the anode electrode 14, contacts the ohmic electrode 8, extends to the cathode bonding region, and becomes the cathode bonding pad 15a. The high-concentration ion-implanted region 7 and the n + type epitaxial layer 2 that the ohmic electrode 8 contacts have a cathode potential (electrode). The cathode bonding pad 15a is directly fixed to the surface of the InGaP layer 4.

2 and 3 show plan views of the compound semiconductor Schottky barrier diode of the present invention. Figure 2
3 is a schematic pattern diagram of a chip, and FIG. 3 is an enlarged view of an operation area portion. This drawing is the first embodiment of the present invention, and is the case of one Schottky junction.

A Schottky electrode 11 for forming a Schottky junction on the n-type epitaxial layer 3 almost at the center of the chip.
To provide. This electrode has a circular shape with a diameter of about 10 μm, and is the second metal layer Pt / Ti / Pt / Au or Ti.
/ Pt / Au is sequentially deposited. Only the central circular portion is in direct contact with GaAs, and the anode electrode 14 made of a third vapor-deposited metal layer is provided to take out the electrode, and the anode bonding pad 14 is extended.
a is provided.

Below the anode bonding pad 14a, an insulating region 6 into which B + ions have been implanted is provided. As a result, the anode bonding pad 14a can be directly fixed to the substrate without interposing the insulating film, defects during bonding can be reduced, and parasitic capacitance in the bonding pad portion can be eliminated.

The portion indicated by the broken line is the ohmic electrode 8. It surrounds the outer periphery of the circular Schottky electrode 11 and is in contact with the high concentration ion implantation region 7 (not shown).
The ohmic electrode 8 is a first metal layer in which AuGe / Ni / Au are sequentially deposited. The cathode electrode 15 is provided so as to be almost overlapped with the high-concentration ion-implanted region 7, and a cathode electrode 15 formed of a third vapor-deposited metal layer is provided for taking out the electrode.
A cathode bonding pad 15a is provided so as to extend.
In order to take out the cathode electrode, the inductor component, which is a factor of high frequency characteristics, is lowered, so that it is necessary to fix a large number of bonding wires. Therefore, a region occupying half of the chip is a bonding region.

Bonding wires are fixed to the anode and cathode bonding pads 14a and 15a by stitch bonding to take out the electrodes. The area of the anode bonding pad 14a is 60 × 70 μm, and the area of the cathode bonding pad 15a is 180 × 7.
It is 0 μm. In the connection by stitch bond, since two bonding wires can be connected by one-time bonding, even if the bonding area is small, the inductor component, which is a parameter of high frequency characteristics, can be reduced,
It contributes to the improvement of high frequency characteristics.

As shown in FIG. 3, the intersecting portion of the anode electrode and GaAs having the cathode potential is only a shaded region, and the area of this portion is about 100 μm. Since this can be reduced to about 1/13 of the conventional 1300 μm, the thin polyimide film 5 can be used in place of the polyimide which was the interlayer insulating film.

A feature of the present invention is that the InGaP layer 4 is provided on the GaAs epitaxial layer, and the high-concentration ion implantation region 7 is provided on the surface of the InGaP layer 4 in contact with the ohmic electrode 8. As a result, the Schottky electrode 11 and the ohmic electrode 8 are provided on the GaAs surface, and the planar structure of the Schottky barrier diode is realized.

Since it is not necessary to consider the misalignment due to the variation in the mesa shape, the separation distance between the Schottky electrode 11 and the ohmic electrode 8 can be greatly reduced. Further, the insulating region 6 is provided under the anode electrode 14 in most of the region, and the area of the portion where the GaAs cathode potential and the anode electrode 14 intersect is about 100 μm ² , which is a comparison with the conventional one. And the area is 1/13. Therefore, it is not necessary to suppress the parasitic capacitance by increasing the thickness (separation distance), polyimide can be substituted by a thin nitride film, and it is not necessary to consider the taper portion of polyimide.

As a result, specifically, the separation distance between the Schottky junction region and the ohmic electrode is 7 μm to 2 μm.
Can be reduced to Further, the separation distance from the high-concentration ion implantation region 7 is 1 μm. In this case, the high-concentration ion implantation region 7 is a carrier movement path and has substantially the same effect as that of the ohmic electrode 8. It can be reduced to 1/7. Since the distance between the Schottky electrode 11 and the ohmic electrode 8 contributes to the series resistance,
If the separation distance can be reduced, the resistance can be further reduced, and it can greatly contribute to the improvement of high frequency characteristics.

This contributes to downsizing of the chip, and the chip size is 0.27 × 0.31 m in the conventional case.
What was the size of m ² was 0.25 × 0.25 mm ²
Can shrink up to. The size is currently limited to 0.25 mm square due to the necessity of arranging bonding pads and the limit of chip size that can be handled at the time of assembly, but the operating range can be greatly reduced to about 1/10. As will be described later, the degree of freedom in arranging the operation area becomes very large.

FIG. 4 shows a second embodiment of the present invention, in which a plurality of Schottky electrodes are provided.

In the structure of the present invention, it is possible to provide a plurality of Schottky electrodes 11. For example, when arranged as shown in the figure, the Schottky electrodes 11 are connected in parallel, which can contribute to the reduction of resistance. If the diameter of the Schottky contact hole 19 is reduced and a plurality of Schottky contact holes 19 are arranged, the total Schottky contact hole 19 is reduced.
The distance between the center of the Schottky contact hole 19 and the high-concentration ion implantation region 7 can be further reduced as compared with the case where only one is arranged with the same area, and carrier trapping in the high-concentration ion implantation region 7 is possible. Becomes effective. As a result, the value of the cathode resistance is reduced, and the high frequency characteristics can be further improved.

5 to 8 show in detail the method of manufacturing the Schottky barrier diode of the present invention.

In the Schottky barrier diode, a one-conductivity type epitaxial layer and a stable compound semiconductor layer are laminated on a non-doped compound semiconductor substrate, and one-conductivity type high-concentration ions are formed on the surface of the compound semiconductor layer under the planned first electrode. Forming an implantation region, forming a first electrode that makes ohmic contact with the surface of the high concentration ion implantation region, forming a Schottky contact hole in the compound semiconductor layer,
It comprises a step of forming a second electrode that forms a Schottky junction with the surface of the epitaxial layer, and a step of forming metal layers that contact the first and second electrodes, respectively.

The first step of the present invention is as shown in FIG.
By stacking the one-conductivity-type epitaxial layer 3 and the stable compound semiconductor layer 4 on the non-doped compound semiconductor substrate 1, and forming the high-concentration ion implantation region 7 on the surface of the compound semiconductor layer 4 under the planned first electrode 8. is there.

This step is a characteristic step of the present invention, and n under the region where the planned ohmic electrode 8 is formed.
A high-concentration ion implantation region 7 which penetrates the type epitaxial layer 3 and reaches the n + type epitaxial layer 2 is formed.

That is, n is added to the non-doped GaAs substrate 1.
+ Type epitaxial layer 2 (5 × 10 ¹⁸cm^-3) 500
Deposit about 0Å, and n-type epitaxial layer 3 on top of it
(1.3 x 10¹⁷cm^-3) Is deposited for 2500Å. Further
An undoped InGaP layer 4 of 200 Å is provided on the upper layer.
Kick After that, the entire surface is covered with a nitride film 5 and a resist layer is provided.
Selectively open the resist layer on the planned insulated region 6.
Photolithography process. Then this
B + impurities are ion-implanted using the resist layer of
The insulating region 6 reaching the non-doped GaAs substrate 1
GaAs and cathode bond
Insulation from the swinging pad portion 14a is achieved.

Next, a photolithography process for selectively opening the resist layer on the region where the planned high-concentration ion implantation region 7 is formed is performed. Then, using this resist layer as a mask, high-concentration n-type impurities (Si +, 1 × 1)
Ion implantation (about 0 ¹⁸ cm ⁻³ ) to penetrate the InGaP layer 4 and the n-type epitaxial layer 3 under the planned ohmic electrode 8 to form the high-concentration ion-implanted region 7 reaching the n + -type epitaxial layer 2. At this time, the ion implantation is performed plural times under different conditions so that the impurity concentration of the high-concentration ion implantation region 7 is formed as uniform as possible in the depth direction.

Thereafter, the resist layer is removed, the nitride film 5 is again deposited for annealing, and activation annealing of the high-concentration ion implantation region 7 and the insulating region 6 is performed.

The second step of the present invention is as shown in FIG.
First ohmic contact with the surface of the high concentration ion implantation region 7
To form the electrode 8 of FIG.

A photolithography process is performed in which a resist layer is formed on the entire surface and windows are selectively opened in portions where the ohmic electrodes 8 are to be formed. The nitride film 5 exposed from the resist layer is removed, and the first metal layer AuGe /
Three layers of Ni / Au are sequentially vacuum-deposited and laminated. afterwards,
The resist layer is removed by lift-off, and the first metal layer is left on the planned ohmic electrode 8 portion. Subsequently, an ohmic electrode 8 is formed on the surface of the high concentration ion implantation region 7 by heat treatment for alloying.

The third step of the present invention is as shown in FIG.
This is to form a Schottky contact hole 9 in the compound semiconductor layer 4 and to form a second electrode 11 forming a Schottky junction on the surface of the epitaxial layer 3.

This step is a characteristic step of the present invention,
The Schottky contact hole 9 is formed, and the Schottky junction is formed by vapor deposition metal.

First, in FIG. 7 (A), a resist layer PR is formed on the entire surface, and a photolithography process is performed to selectively open a predetermined Schottky electrode 11 portion. After exposing the exposed nitride film 5 by dry etching, In
The GaP layer 4 is etched. Where InGaP is G
Since the selection ratio of aAs to etching is very large, only the InGaP layer 4 is removed by etching under predetermined conditions, and the Schottky contact hole 9 exposing the n-type epitaxial layer 3 is formed.

Thereafter, as shown in FIG. 7B, three layers of Ti / Pt / Au, which are the second metal layer, are sequentially vacuum-deposited and laminated on the entire surface. After that, the resist layer PR is removed by lift-off, and a Schottky junction is formed on the surface of the n-type epitaxial layer 3 to form the Schottky electrode 11.
The GaAs surface is In until the Schottky junction is formed.
Since it is covered with GaP, the Schottky junction can be formed with the GaAs surface in a good state.

That is, the InGaP layer 4 makes it possible to easily form the Schottky electrode 11 which forms a good Schottky junction with the surface of the n-type epitaxial layer 3. In the conventional manufacturing method, it is very difficult to precisely control the time and temperature, the wafer swing width and the swing speed in the etching solution, and it is required to use the etching solution within the predetermined freshness retention time. To be done. However, according to the manufacturing method of the present invention, if the optimal 2500 Å epitaxial layer 3 is formed in advance as the operating layer, only InGaP is etched by highly selective etching, and the thickness of the operating layer can be controlled. Since it is easy, a Schottky junction having good reproducibility can be formed, and a Schottky barrier diode having stable characteristics can be manufactured.

The fourth step of the present invention is as shown in FIG.
The purpose is to form metal layers 14 and 15 which are in contact with the first electrode 8 and the second electrode 11, respectively.

This step is also a characteristic step of the present invention,
In order to take out the Schottky electrode 11 and the ohmic electrode 8, a vapor-deposited metal layer to be the anode electrode 14 and the cathode electrode 15 is formed.

First, 5000 Å to be an interlayer insulating film on the entire surface.
The nitride film 5 of a certain degree is deposited again. A Schottky electrode 11, an ohmic electrode 8 and an anode bonding pad 14 which form a resist layer and serve as a contact portion are formed.
a, a photolithography process of selectively opening a window in the cathode bonding pad 15a is performed to etch the nitride film 5. After removing the resist, a new resist layer is further provided, and a photolithography process for selectively opening a desired pattern of the anode electrode 14 and the cathode electrode 15 is performed. Ti / Pt / Au is sequentially vapor-deposited on the entire surface, the anode electrode 14 and the cathode electrode 15 are formed by lift-off, and the back surface is back-lapped.

Here, the anode electrode 14 and the cathode electrode 15 are vapor-deposited metal formed by a normal lift-off method. Further, since the interlayer insulating film between the anode electrode 14 and the cathode electrode 15 is the nitride film 5 and the bonding pad portion can also be directly fixed to the substrate, the polyimide layer can be omitted. This makes it possible to omit the Au plating step for forming the wiring and the bonding pad, which is conventionally provided thickly to absorb the defects of the polyimide on the polyimide layer.

The conventional process of forming a thick polyimide layer is time-consuming and complicated by coating and curing several times. Further, the Au plating layer forming step has also been a factor in increasing the number of manufacturing steps. However, according to the manufacturing method of the present invention, these polyimide layer and A
The u-plated layer forming step can be omitted, and the manufacturing process can be greatly simplified and the efficiency can be improved.

When the compound semiconductor Schottky barrier diode has completed the previous process, it is moved to the subsequent process for assembling. The wafer-shaped semiconductor chip is diced into individual semiconductor chips, and the semiconductor chips are fixed to a frame (not shown). Then, bonding pads 14a and 15a of the semiconductor chips and predetermined leads (not shown) are bonded by bonding wires. No)) and connect. Gold wires are used as the bonding wires, and they are connected by known stitch bonding. After that, transfer molding is performed and a resin package is applied.

[0079]

According to the structure of the present invention, the following various effects can be obtained.

First, from the InGaP layer to GaAs n +
A Schottky barrier diode having a planar structure is realized by providing an ohmic electrode on the surface of the high-concentration ion-implanted region reaching the type epitaxial layer. Since no mesa is provided, it is possible to suppress variations in the ohmic electrode shape and deterioration of characteristics due to variations in the mesa shape,
Since it is not necessary to consider misalignment, the separation distance between the Schottky electrode 11 and the ohmic electrode 8 can be greatly reduced. Since the distance between the Schottky electrode 11 and the ohmic electrode 8 contributes to the series resistance, the resistance can be further reduced if the distance can be reduced.

Secondly, the area of the portion where GaAs, which is at the cathode potential, and the anode electrode 14 intersect is about 100 μm ² , and the parasitic capacitance is greatly reduced. This is because the insulating region 6 is provided in most of the region under the anode electrode 14, and the area of the intersection that causes parasitic capacitance is 1 at the Schottky junction portion as compared with the conventional case.
It can be reduced to / 13. Moreover, since the anode bonding pad 14a can be directly fixed to GaAs,
No parasitic capacitance is generated in this portion, and the total parasitic capacitance can be significantly reduced. Conventionally, a polyimide having a low dielectric constant is used to provide a thick interlayer insulating film in order to suppress parasitic capacitance, but a thin nitride film can be used instead. Although the nitride film has a higher dielectric constant than polyimide, the structure of the present invention can reduce the parasitic capacitance as compared with the conventional case even if a nitride film of about 5000 Å is used.

Third, since thick polyimide is not used,
It is not necessary to consider the distance of the taper portion of the polyimide opening which becomes the operation area and the variation of the taper angle.

From the above, the separation distance between the Schottky electrode and the ohmic electrode can be obtained simply by considering only the breakdown voltage and the mask alignment accuracy. Specifically, the separation distance between the Schottky junction region and the ohmic electrode is 7 μm.
To 2 μm. Further, the separation distance from the high-concentration ion implantation region 7 is 1 μm. In this case, the high-concentration ion implantation region 7 is a carrier movement path and has substantially the same effect as that of the ohmic electrode 8. It can be reduced to 1/7. Therefore, a large reduction in resistance, a large reduction in parasitic capacitance, and a reduction in variations in parasitic capacitance can greatly contribute to the improvement of high frequency characteristics.

Fourth, it contributes to downsizing of the chip, and the chip size is 0.27 × 0.31 mm ^{2 in the} conventional case.
It was possible to shrink up to 0.25 x 0.25 mm ² from the size of. The size is currently limited to 0.25 mm square due to the necessity of arranging bonding pads and the limit of chip size that can be handled at the time of assembly, but the operating range can be greatly reduced to about 1/10. , The degree of freedom in arranging the operation area becomes very large.

Fifth, the resistance can be further reduced by providing a plurality of Schottky junction portions forming the Schottky electrodes. When the contact diameter of the Schottky junction is reduced and a plurality of contacts are provided, the resistance is further reduced and high-concentration ion implantation is performed as compared with the case where one Schottky electrode having the same total Schottky contact area is provided. Since the carriers can be effectively trapped in the region, there is an advantage that the high frequency characteristics are further improved.

Sixth, since the polyimide layer and the gold plating are not used, the material cost can be reduced and the chip shrinking can be realized, so that the cost reduction can be realized.

According to the manufacturing method of the present invention, the following effects can be obtained.

First, since it is possible to form a stable Schottky junction, it is possible to suppress variations in characteristics, which is a very important issue for high frequency circuits. The n-type epitaxial layer is I until just before the Schottky junction is formed.
If InGaP is covered with nGaP and Ti / Pt / Au is vapor-deposited by etching InGaP, a Schottky junction can be formed on a crystal surface with no contamination. Further, the n-type epitaxial layer is formed at 2500 Å which is optimum as an operating layer, and InGaP has a very large etching selection ratio with GaAs.
Only GaP can be etched. Therefore, the complicated etching control of GaAs as in the prior art is unnecessary. That is, it is possible to manufacture a Schottky barrier diode having improved yield, good reproducibility, and stable characteristics.

Secondly, the above Schottky barrier diode can be manufactured efficiently and further by simplifying the manufacturing process. Specifically, it includes a mesa etching step, an n-type epitaxial layer etching step before forming a Schottky junction, a polyimide layer forming step, an Au plating step, and the like. The polyimide layer is formed by repeating coating several times so as to have a thickness of 6 to 7 μm. Coating the polyimide layer several times takes time and complicates the manufacturing flow. Further, if the polyimide is unnecessary, the electrode formed by the Au plating layer is also unnecessary. Conventionally, it is necessary to secure the strength of the electrodes in order to prevent the electrodes from being broken or deformed by heat during solder mounting or stress during wire bonding, and the anode electrode and the cathode electrode are formed by a thick Au plating layer. However, if the polyimide layer is unnecessary, it is not necessary to consider its influence. That is, the gold-plated electrode becomes unnecessary, and the anode electrode and the cathode electrode can be formed only by the vapor-deposited metal of Ti / Pt / Au, and the reliability is improved. Further, the above-mentioned factors that have conventionally caused a decrease in yield are eliminated, so that the yield is also improved.

That is, although the Schottky barrier diode is capable of greatly reducing the parasitic capacitance and further reducing the resistance to significantly improve the high frequency characteristics, it is possible to provide a manufacturing method in which the manufacturing process is simplified and the efficiency is improved. Have advantages.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a semiconductor device of the present invention.

FIG. 2 is a top view for explaining a semiconductor device of the present invention.

FIG. 3 is a top view for explaining the semiconductor device of the present invention.

FIG. 4 is a top view for explaining a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating the method for manufacturing the semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 10 is a top view for explaining a conventional semiconductor device.

FIG. 11 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 12 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 13 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 14 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 15 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshifumi Nakajima             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Shigeyuki Murai             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hisashi Tominaga             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Koichi Hirata             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Mikito Sakakibara             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hidetoshi Ishihara             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F-term (reference) 4M104 AA05 BB06 BB11 BB15 CC01                       CC03 DD08 DD17 DD26 DD34                       DD68 DD78 DD83 EE08 EE17                       EE20 FF17 FF22 GG03 HH14                 5F043 DD13 EE07 EE08 EE09

Claims (12)

[Claims] 1. A compound semiconductor substrate, a flat epitaxial layer of one conductivity type provided on the substrate, a stable compound semiconductor layer for protecting the epitaxial layer, and one conductivity type provided on the surface of the compound semiconductor layer. A high-concentration ion-implanted region, a first electrode that makes ohmic contact with the surface of the high-concentration ion-implanted region, a second electrode that forms a Schottky junction with the surface of the epitaxial layer, and a first electrode and a second electrode. A Schottky barrier diode comprising a metal layer to be taken out. 2. A compound semiconductor substrate, a flat one-conductivity-type high-concentration epitaxial layer provided on the substrate, a one-conductivity-type epitaxial layer, and a stable compound semiconductor layer that protects the epitaxial layer; One conductivity type high-concentration ion implantation region reaching from the layer surface to the high-concentration epitaxial layer, a first electrode that makes ohmic contact with the high-concentration ion implantation region surface, and the outer periphery is surrounded by the first electrode, A Schottky barrier comprising: a second electrode that forms a Schottky junction with the surface of the epitaxial layer below the compound semiconductor layer; and a metal layer that serves as a lead-out of the first and second electrodes. diode. 3. The compound semiconductor layer is non-doped InG
The Schottky barrier diode according to claim 1 or 2, wherein the Schottky barrier diode is aP. 4. The compound semiconductor substrate is non-doped Ga
The Schottky barrier diode according to claim 1 or 2, which is an As substrate. 5. The Schottky barrier diode according to claim 1, wherein the second electrode is a vapor-deposited metal whose bottom layer is Pt. 6. The Schottky barrier diode according to claim 1, wherein the distance between the second electrode and the high-concentration ion implantation region is 5 μm or less. 7. The Schottky barrier diode according to claim 1, wherein the Schottky junction region formed by the second electrode is divided into a plurality of regions. 8. The Schottky barrier diode according to claim 1, wherein the high-concentration ion implantation region is provided so as to protrude from the first electrode. 9. A non-doped compound semiconductor substrate is laminated with an epitaxial layer of one conductivity type and a stable compound semiconductor layer, and a high-concentration ion implantation region of one conductivity type is formed on the surface of the compound semiconductor layer under a predetermined first electrode. A step of forming, a step of forming a first electrode in ohmic contact with the surface of the high concentration ion implantation region, a step of forming a Schottky contact hole in the compound semiconductor layer, and a Schottky junction with the surface of the epitaxial layer. A method of manufacturing a Schottky barrier diode, comprising: a step of forming a second electrode; and a step of forming a metal layer in contact with each of the first and second electrodes. 10. A non-doped compound semiconductor substrate on which a high-concentration one-conductivity type epitaxial layer, a one-conductivity type epitaxial layer, and a stable compound semiconductor layer are laminated, and the compound semiconductor layer surface under the first electrode is planned. Forming a one-conductivity-type high-concentration ion-implanted region reaching the high-concentration epitaxial layer; forming a first electrode in ohmic contact with the surface of the high-concentration ion-implanted region; and forming an outer periphery on the first electrode. Forming a Schottky contact hole in the compound semiconductor layer of a second electrode portion to be surrounded, and forming a second electrode forming a Schottky junction with the exposed surface of the epitaxial layer; And a step of forming a metal layer in contact with the second electrode, respectively. Manufacturing method. 11. The method of manufacturing a Schottky barrier diode according to claim 9, wherein the second electrode is formed by sequentially depositing a Ti / Pt / Au multilayer metal layer. 12. The method of manufacturing a Schottky barrier diode according to claim 9, wherein the compound semiconductor layer has a large etching selection ratio with respect to the epitaxial layer.