JPS61155875A - Generating circuit for evaluating signal - Google Patents

Abstract

PURPOSE:To reduce the occupation area of a chip and to simplify a program by providing an evaluation terminal, counting circuit, evaluation mode selecting circuit, output mode setting circuit, etc., and evaluating an LSI. CONSTITUTION:A reset signal RST is applied from a logical circuit Y and a signal phi is applied from the evaluation terminal 5. Then, the signal phi is applied as clock pulses of a binary counter 6 and then led out as a signal Q1 after being counted down to a half. Similarly, a signal Q1 is applied to a binary counter 8 and led out as a signal Q2. Then, signals Q0-Q2 are applied to the evaluation mode selecting circuit C. Further, output signals K1 and K2 of NAND gates 19 and 20 are applied as an evaluation mode signal of the output mode setting circuit D to evaluate output transistor characteristics.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to large-scale integrated circuits (hereinafter referred to as LSIs), and particularly relates to an evaluation signal production circuit for producing evaluation signals for determining the quality of LSIs. It is related to.

[Technical background of the invention]

Generally, LSI evaluation includes output transistor characteristic evaluation, function confirmation evaluation, reliability evaluation, etc.
Here, we will discuss the evaluation of output transistor characteristics.

All descriptions below are explained using negative logic.

The one with higher tb voltage is logic @O”, the one with lower voltage is logic @1”
Yes, logic 10” is GND level, logic @1# is VD
It is set as D level.

In an LSIK, in a normal state, the basic clock φl of the LSI internal circuit and the output signal 01 are manufactured as shown in FIG. Next, in the evaluation state, it is common to shorten the evaluation time. Therefore, if the frequency of the basic tarok of the LSI internal circuit is increased as represented by φ3, the capacitance and resistance of the LSI internal circuit and evaluation device are added, so the output signal of the LSI internal circuit will depend on the time constant of the load resistance and capacitance. Namaj9
0. Since it is output as a waveform as shown in the figure, it is impossible to evaluate the characteristics of the output transistor. To solve this problem, it is necessary to provide evaluation terminals on the chip.

FIG. 5 shows a conventional evaluation signal generation circuit. In the figure, 1, 2.3 are evaluation terminals, X is an LSI internal circuit, and 4
is the output terminal. FIG. 6 is a timing chart of the circuit shown in FIG. 5 above.

The T1 period represents a normal state, the T period represents a characteristic evaluation state of an N-channel transistor, and the T1 period represents a characteristic evaluation state of a P-channel transistor.

The operation will be explained below. For example, signal 1 in period T1
01,10;I! , 103 are all given logic @O", NANDI'-) 11, 12 output signal 105
, 106 are NANDI' as logic @″1″, @1″
-is, J 4, the LSI internal internal circuit specific power signal 104 is inverted and supplied to the output terminal 4 as a signal 108, resulting in a normal state.

Next, during the T3 period, that is, in the evaluation state of the N-channel transistor, logic @l#, @Q", "l
“If we apply each.

NAND f-to 11.12 (D output signal 105, 10
6 is a logic "i", @o", and the inverter 150 input signal 102 is a logic "@O". Therefore, inverter 15
The ON channel transistor is turned on, and the output signal 108 output from the inverter 15 is at the GND level.If this is measured at the output terminal 4, the output characteristics of the N channel transistor can be evaluated.

Similarly, during the TI period, that is, in the evaluation state of the P-channel transistor, the signal 1 input to the evaluation terminal 1.2.3
Since logic ``''11 is applied to all of 01, 102, and 103, the output signals 105 and 106 of NAND f -) 1 i e I J become logic ``@Qll, @Q'', and the input signal of inverter 15 is Logic @1”. Therefore,
Inverter 150P channel transistor turns on,
The output signal 1011 output from this inverter 15 is at the VDD level. By measuring this at the output terminal 4, it is possible to evaluate the output characteristics of the P-channel transistor.

Conventionally, the characteristics of output transistors have been evaluated using the method described above.

[Problems with background technology]

However, in this evaluation method, it is necessary to provide evaluation terminals on the chip according to the need for evaluation signals, and the area occupied cannot be ignored (this leads to an increase in the chip size). leads to increased costs. Moreover, the evaluation terminal is completely unnecessary for the K used by Needy. Furthermore, since several types of input signals are required for a plurality of evaluation terminals depending on the purpose of evaluation, the program of the evaluation device becomes complicated, which causes a problem that the evaluation takes a long time.

[Object of the invention].

The present invention was made in view of the above-mentioned circumstances, and its purpose is to enable evaluation of L8L by simply providing one evaluation terminal on the LSI chip, thereby reducing the chip occupation area. Another object of the present invention is to provide an evaluation signal generation circuit that can simplify programming.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, an LSI chip includes one evaluation terminal, a count circuit that counts signals supplied from this evaluation terminal, and several types of signals output from this count circuit. an evaluation mode selection circuit that creates an evaluation mode by combining the logic of the signals;
and an output mode setting circuit for setting the output signal of the internal circuit of the LSI to an evaluation output level in accordance with the evaluation mode signal output from the evaluation mode selection circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an evaluation signal generating circuit of the present invention, Y is a logic circuit, 5 is an evaluation terminal, and X is an LSI internal circuit, which is the same as X in FIG. 6 above. 6 represents an output terminal. The circuit is composed of four parts: part A is an evaluation terminal, part B is a count circuit, part 0 is an evaluation mode selection circuit, and part D is an output mode setting circuit. Figure 2 shows the binary counter used in the counting circuit of section B.
9.NOR? -) and four clocked inverters. Y is a logic circuit, which is the same as Y in FIG.

Hereinafter, the operation of the infinitely counter will be explained by dividing it into three cases of time t1+t**ts shown in the timing chart of FIG.

Logic circuit Y is provided inside the LSI, and performs the instantaneous logic @11 when power is applied, and J) resets the LSI internal circuit.
It is used as a reset signal for a binary counter in a circuit that maintains a logic 10'' after a period of time.Here, the output signal of logic circuit Y is expressed as R8T.Note that T4
The period is before the power is applied, and the T8 period is after the power is applied. The signal φ is also a clock/4 pulse applied to the binary counter. First, in the t1 section, the signal R8T assumes the logic @1" at the moment of power application, so N0II"-t2
5. : Inverted by IF, signal H1a Qo is logic 1
Since the signal φ is logic @0'', the clocked inverter 26 acts as an inverter and outputs the signal H.
, invert.

The signal H1 takes the logic "1".The signal H3 takes the logic "1" because the signal φ is the logic "0", and the signal H3 takes the logic "1".
acts as a signal and inverts the signal H1, and the signal H3 becomes a logic
Take "1".

Next, the operation of the tx unit will be explained. In this case, the signal φ is logic @
1'', the impedance impedance 26 is in a high impedance state, black.

Since the quad inverter 29 becomes an inverter, the signal Q
Since the signal H is the logic 101, the signal H maintains the logic "1". Also, since the clocked inverter 24 acts as an inverter, the signal Hs takes the logic @0.

Further, the signal Hs is inverted by the N0Rr-to-2B, making the signal H1 logic @1''.

Next, we will explain the operation of the ts section. In this case, the signal φ is at logic ""01. Clocked (y park 24 is in high impedance state, black, black inverter 28
is not an inverter, and the signal H1 is inverted to become the signal H3, so the signal H3 maintains logic 01. Since the black inverter 26 acts as an inverter,
The signal H1 is inverted, and the signal H3 becomes a logic "O".The signal Qo is inverted by the primary KNORr-to-2:F, and the signal Qo becomes a logic "O".
Take 1”.

Through similar operations, the binary counter counts down the signal φ to IA and outputs the signal Qo.

Next, the operation of the evaluation signal generating circuit of the present invention will be explained using the timing chart of FIG. In the evaluation signal generating circuit of the present invention, three binary counters shown in FIG. 2 are used to form a counting circuit B. First, a reset signal R8T is applied from the logic circuit Y, and a signal φ is applied from the evaluation terminal 5.

The signal φ is applied as a clock/4 pulse of the binary counter 16, and after counting down to IA, the signal Q0 is applied.
As a result. The signal Qo is applied as the clock/4 pulse of the binary counter 17 of the next stage, and is output as the signal Q1 after counting down to 1/2. Similarly, the signal Q1 is applied as the clock/4 pulse of the binary counter 18 of the next stage It is applied as signal Q3 after counting down by 1/2 K.

Next, the output signal Qo from the count circuit B.

QIIQI is applied to the evaluation mode selection circuit CK.

The evaluation mode selection circuit is composed of two NAND e-), and the NAND l'-) J s has a signal Q.
o-Qs.

NAND? Since the signal Qo-Q is applied to NANDr-) 20, the output signals of NANDr-) 19 and 20 are output as waveforms shown in the timing chart of FIG. The output signal Kl.

By applying Kl as an evaluation mode signal to the D section output-mode setting circuit, the output transistor characteristics are evaluated.

Hereinafter, a method for evaluating output transistor characteristics will be explained with reference to a timing chart shown in FIG. In addition.

The T6 period is a normal state, the T7 period is an N-channel transistor evaluation state, and the Ts period is a P-channel transistor evaluation state. First, in the normal state during the T6 period, the evaluation signals 1 and 1 are respectively set to logic ``1'' l1llj. Then NAND e-t21,2:l
Since the logic @1'' is applied to D, the LSI internal internal circuit specific force signal 110 is inverted and reaches the evaluation terminal 6 as a signal 112. , to logical “01, @1
”, the input signal 11 of the inverter 23 becomes logic 101, so the N-channel transistor of the inverter 23 turns on, and the output signal 112 becomes the potential of the VDD level.Then, the level of the output signal 112 is output. By measuring at the terminal 6, it is possible to evaluate the output characteristics of the N-channel transistor.

Similarly, in the evaluation state of the P-channel reduced transistor in the TI period, the evaluation signal K 1 + K z is
When set to "l", @O" or logic ""O", @O, the input signal 111 of IN/4-Y23 becomes logic "L", so the P channel shop of IN/4-Y23 becomes The transistor is turned on, and the output signal 112 has a potential of GND level. Therefore, by measuring the output signal 112 at the proper output terminal 6, it is possible to evaluate the output characteristics of the P-channel transistor. The above results are summarized in Table 1.

Table 1 In the embodiments described above, only two types of evaluation signals are prepared, and the evaluation potential is VDD.

This is because only the binary level of GND is used, and if it is desired to perform evaluation at a ternary level or higher, three or more types of evaluation signals may be created. This can be done by simply adjusting the number of count circuits, evaluation mode selection circuits, and output mode setting circuits.

Furthermore, in Fig. 1, the evaluation mode selection circuit and the output mode setting circuit are made up of NAND gates, but N0Rr
−), but if you change the polarity of the input, you can get a similar circuit.

Note that T and IT are evaluation possible timings.

The location of the R8T signal can be easily determined from the I4 pulse number of the clock φ after the R8T signal changes from 1 to 0.

The evaluation signal generation circuit described above is composed of one evaluation terminal provided on LSI chips, a count circuit, an evaluation mode P selection circuit, and an output mode setting circuit.
It is possible to significantly reduce the number of evaluation terminals compared to the prior art. Also, the area occupied by the evaluation terminal in the chip area is
Since it is larger than the counter circuit and the evaluation mode selection circuit, the chip size of the LSI can be reduced, which is extremely effective in reducing costs.

Furthermore, by simply applying a type of signal from the evaluation terminal, LSI
Since it is possible to evaluate, the program of the evaluation device can be simplified and the evaluation time can be shortened.

〔Effect of the invention〕

As explained above, according to the present invention, the evaluation signal generation circuit can evaluate the L8I by simply providing one evaluation terminal on the LSI chip, reducing the chip area and simplifying the program. is obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an evaluation signal generation circuit of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of an inary counter in the circuit shown in FIG. 1, and FIG. 3 is an operation of the circuit shown in FIG. 2 above. 4 is a timing chart for explaining the above timing chart.
A timing chart to explain the operation of the circuit shown in the figure,
FIG. 5 is a timing chart for explaining the basic clock inside the LSI, the normal state of the output signal, and the evaluation state.
FIG. 6 is a diagram showing a conventional evaluation signal generation circuit, and FIG. 7 is a timing chart for explaining the operation of the circuit shown in FIG. 6. 1-j e j -1;...Evaluation terminal, 4.6...
・Output terminal, 11, 12, 13.14, 19.20, 2
1°J 2 ・NAND ff −), f 5 , 23
-...Iy i4- Jl, 16, 17.18...Nono Inary Counter, 24.26.2'8.29...
・Clocked inverter, sr s, 2 v-N
ORr −), X/LSI internal circuit, Y...logic circuit.

Claims (1)

[Claims] an evaluation terminal for supplying an evaluation signal to a large-scale integrated circuit;
a count circuit that counts signals supplied from the evaluation terminal; an evaluation mode selection circuit that decodes several types of signals output from the count circuit to create an evaluation mode setting signal; An evaluation signal production circuit comprising: an output mode setting circuit that sets an output terminal of a large-scale integrated circuit to an evaluation output level.