JPS609134A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS609134A JPS609134A JP58115891A JP11589183A JPS609134A JP S609134 A JPS609134 A JP S609134A JP 58115891 A JP58115891 A JP 58115891A JP 11589183 A JP11589183 A JP 11589183A JP S609134 A JPS609134 A JP S609134A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- same function
- pad
- semiconductor device
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は半導体装置、特に、半導体チップ上の？ンディ
ングパッド（本明細書では、単にパッドとする）の配置
に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to semiconductor devices, particularly semiconductor devices on semiconductor chips. The present invention relates to the arrangement of landing pads (herein simply referred to as pads).
技術の背景
半導体装置の・母ッケージ形式としては、外形上の相違
から言ってＤＩＰ （デュアルインライン／やッケージ
）、リードレスノ？、ケージ、フラットパッケージ等が
あり、その材質乃至封止形態としても、メタルシール、
サーディズプラスチック等があり、これらのパッケージ
においては、ビンディングポストの位置が異なる。Technical background The main package formats for semiconductor devices are DIP (dual in-line/ya package) and leadless package based on the differences in external shape. , cages, flat packages, etc., and their materials and sealing forms include metal seals,
There are Sardis plastics, etc., and the positions of the binding posts are different in these packages.
従来技術と問題点
従来の半導体チップにおける同一機能を有する／ｅ ｙ
ドは１つである。従って、半導体チップの・ぐラド配置
を１種類のパッケージのボンディングポスト位置に合わ
せて設計すると、他のパッケージに不適切となシ、つま
り、リード配線が長くなシ、この結果、キャピテイの減
少、配ね容量の増加等の問題点が生じ、しかも、ワイヤ
デンディングにも無理が生じ、延いては製造コストが高
くなるという問題点があった。Conventional technology and problems It has the same function as the conventional semiconductor chip/e y
There is one C. Therefore, if the semiconductor chip layout is designed to match the bonding post position of one type of package, it may not be suitable for other packages. Problems such as an increase in the wiring capacity arise, and in addition, there is a problem in that wire endings become difficult, and as a result, manufacturing costs increase.
発明の目的
本発明の目的は、上述の従来形の問題点に鑑み、同一機
能を有するパッドを複数個設け、各パッケージに適切な
パッドを選択して接続することにより、リード配線を短
かくシ、キャビティの増加、配線容力士の減少等に貢献
し、しかもワイヤがンディングをし易くして製造コスト
を低減することにある。Purpose of the Invention In view of the above-mentioned problems with the conventional method, an object of the present invention is to provide a plurality of pads having the same function, and to select and connect the appropriate pads to each package, thereby shortening the lead wiring length and making the system short. This contributes to an increase in the number of cavities, a decrease in the number of wiring engineers, etc., and also makes it easier to wire the wires, thereby reducing manufacturing costs.
発明の構成
上述の目的を達成するために本発明によれば、同一機能
を有する／ぐラドを複数個配置し、該同一機能を有する
パッド同志を電気的に接続する手段を設け、且つ該同一
機能を有する複数個の・フッドのうちの少なくとも１つ
を除く所望の・やラドのみに選択的にノへツケージのリ
ードへのワイヤデンディングを施したことを特徴とする
半導体装置が提供される。Structure of the Invention In order to achieve the above-mentioned object, according to the present invention, a plurality of pads having the same function are arranged, a means for electrically connecting the pads having the same function is provided, and the pads having the same function are provided. Provided is a semiconductor device characterized in that wires are selectively wired to the leads of a hinge cage only on desired rads excluding at least one of a plurality of hoods having a function. .
発明の実施例
第１図は本発明に係る半導体装置の一実施例を示す平面
図である。第１図においては、１６ビンの半導体装置を
示しである。つま９、・ぐラド１〜１６はそれぞれ異種
機能を有する。このような異種機能を有する／、ｏラド
は２辺に沿って配置されている。パッド４’、 ５’、
１２’、 １３’は本発明によって付加されたもので
あって、それぞれ、パッド４゜５．１２，１３と同一機
能を有する。従って、パッケージに実装した場合には、
パッド４，４′のうち１つ、パッド５，５′の１つ、ノ
Ｐツド１２ 、１２’の１つ、パッド１３．１３’の１
つにリード配線を行えばよい。Embodiment of the Invention FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the invention. FIG. 1 shows a 16-bin semiconductor device. The claws 9 and 1 to 16 each have different functions. The / and orads having such different functions are arranged along two sides. Pads 4', 5',
Pads 12' and 13' are added according to the present invention and have the same functions as pads 4, 5, and 12 and 13, respectively. Therefore, when implemented in a package,
One of pads 4, 4', one of pads 5, 5', one of pads 12, 12', one of pads 13, 13'.
Just do the lead wiring.
第２図は第１図の装置をメタルシール型のセラミック製
・ぐツケ〜ジに実装した場合を示す。この場合、ビンデ
ィングポストは左右に配置されているので、パッド４，
５，１２．１３がビンディングポストに接続される。ま
た、メタルシールの場合は、上下の部分にボンディング
ポストを設ける事はキャビディの減少を招き困難でちる
。また、第３図は第１図の装置をサーディフ０やプラス
チック型のパッケージに実装した場合を示す。この場合
、上下にもン」ビンディングポストが存在するので、パ
ッド４’、 ５’、 １２’、 １３’がボンディング
ポストに接続される。即ち、サーディゾやプラスチック
の場合は全ポストを左右両辺に配置することは困難であ
る。さらに、第４図は第１図の装置をリードレステップ
キャリアに実装した場合を示す。この場合、４辺共もほ
ぼ等間隔にビンディングポストが存在し、しかもすべて
のボンディングポストにビンディングを行う必要はない
ので、図示のととぐ、ビンディングが行われる。FIG. 2 shows a case in which the device shown in FIG. 1 is mounted in a metal-sealed ceramic cage. In this case, the binding posts are placed on the left and right, so pad 4,
5, 12 and 13 are connected to the binding post. In addition, in the case of a metal seal, it is difficult to provide bonding posts in the upper and lower portions because this reduces the cavity. Further, FIG. 3 shows a case where the device shown in FIG. 1 is mounted in a SARDIF0 or plastic type package. In this case, since there are bonding posts on the top and bottom, pads 4', 5', 12', and 13' are connected to the bonding posts. That is, in the case of Sardizo or plastic, it is difficult to arrange all the posts on both the left and right sides. Furthermore, FIG. 4 shows a case where the device of FIG. 1 is mounted on a leadless step carrier. In this case, binding posts are present at approximately equal intervals on all four sides, and it is not necessary to perform binding on all the bonding posts, so binding is performed as shown.
このように同一機能を有するパッドを複数個設けである
ので、パッケージのボンディングポスト配置に適したぎ
ンディングを行うことができる。Since a plurality of pads having the same function are provided in this way, it is possible to perform bonding suitable for the bonding post arrangement of the package.
上述の同一機能を有するパッドは半導体装置において接
続等が行われていなければならない。これを第５図〜第
８図を参照して説明する。なお、第５図〜第８図におい
ては、例としてパッド１３゜１３′について説明しであ
る。The pads having the same function as described above must be connected to each other in the semiconductor device. This will be explained with reference to FIGS. 5 to 8. In addition, in FIGS. 5 to 8, pads 13° and 13' are explained as an example.
第５図においては、ノクツド１３とノクツド１３′とを
直接同一金属層たとえばアルミニウム層で接続し、これ
を内部回路に導いている。なお、この場合には、たとえ
ばパッド４を使用した場合に、使用されていないパッド
４′がパッド４の配線容量として作用し、信号伝播速度
が低下するという不利な点がある。In FIG. 5, the notches 13 and 13' are directly connected through the same metal layer, such as an aluminum layer, and this is led to the internal circuit. In this case, for example, when pad 4 is used, there is a disadvantage that unused pad 4' acts as a wiring capacitance of pad 4, reducing the signal propagation speed.
第６図においては、パッド１３．１３’を内部回路で並
列されたグー）Ｇｔ＋Ｇｚにそれぞれ接続しである。従
って、この場合には、第５図における不利な点は解消さ
れているが、使用されてパッドたとえば１３′がフロー
ティング状態となるので、何らかの原因でゲートＧ２が
動作する可能性があるという不利な点がある。In FIG. 6, pads 13 and 13' are connected to Gt+Gz which are connected in parallel in an internal circuit. Therefore, in this case, the disadvantage in FIG. 5 has been eliminated, but since the used pad, for example 13', is in a floating state, there is a disadvantage that the gate G2 may operate for some reason. There is a point.
第７図においては、各パッド１３．１３’にデプレッシ
ョン形トランジスタＧ３＋Ｇ４を接続してあり、これに
よシ、使用されていないパッドはアースされ、従って、
フローティング状態を逸脱できる。もちろん、使用され
ているパッドの電位が適切であることを考慮してグー）
Ｇ３ ｒ ０４の導電率は設計される。なお、グー）Ｇ
３ ＊ Ｇ４は、デプレッション形である必俊はなく、
ドレインーケ゛−ト接続された玉ンハンスメント形トラ
ンジスタでもよい。In FIG. 7, depletion mode transistors G3+G4 are connected to each pad 13, 13', so that the unused pads are grounded, so that
It is possible to deviate from the floating state. Of course, taking into account that the potential of the pads used is appropriate)
The conductivity of G3 r 04 is designed. In addition, Goo)G
3 * G4 does not have a depression type Hissun,
It may also be an enhancement type transistor with a drain-to-case connection.
第８図においては−、フローティング逸脱手段として、
エンハンスメント形トランジスタＧ３’。In FIG. 8 -, as a floating deviation means,
Enhancement type transistor G3'.
０４′を用い、これをケ” ）Ｇ５ ｒ Ｇｓ ＋ Ｇ
７により構成される選択回路によって制御する。なお、
グー）Ｇ６ 、Ｇ、はインバータＩＮＶを構成する。04', and convert this into ")G5 r Gs + G
It is controlled by a selection circuit constituted by 7. In addition,
G) G6 and G constitute an inverter INV.
つまシ、新しく設けられたノぞラドＶｃｃ”ヲオーｆン
にすると、ノードＮ１の電位はアース電位となシ、この
結果、トランジスタ０３′がオフとなってパッド１３は
使用状態にされ、さらに、ノードＮ２の電位はハイレベ
ルとなってトランジスタＱ４／がオンとなるのでパッド
１３′は不使用状態となる。When the newly provided pad Vcc is turned on, the potential of the node N1 becomes the ground potential, and as a result, the transistor 03' is turned off and the pad 13 is put into use. Since the potential of node N2 becomes high level and transistor Q4/ is turned on, pad 13' becomes unused.
他方、第８図において、パッドｖｃｃ＊を第１図のパッ
ド８（電源７００機能を有する）にダンティングするこ
とにより、ノードＮ１の電位はハイレベルとなシ、この
結果、トランジスタＧ３／はオンとなってノぐット１３
は不使用状態となり、さらに、ノードＮ２の電位はロー
レベルとなシ、この結果、トランジスタ０４′はオフと
なってノやット１３′は使用状態となる。On the other hand, in FIG. 8, by damping pad vcc* to pad 8 (having a power supply 700 function) in FIG. 1, the potential of node N1 is kept at a high level, and as a result, transistor G3/ is turned on. Natte Nogut 13
becomes unused, and furthermore, the potential of node N2 becomes low level. As a result, transistor 04' is turned off and node 13' becomes used.
このように第８図において、フローティング状態を逸脱
するパッドを選択できる。In this manner, in FIG. 8, pads that deviate from the floating state can be selected.
発明の詳細
な説明したように本発明によれば、パッケージに適切な
パッドを選択できるので、リード配線を短縮でき、従う
て、キャビティの増加、配線容量の減少に役立ち、また
、ワイヤボンディングをし易くできるので製造コストの
点でも有利である。DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, it is possible to select appropriate pads for the package, so lead wiring can be shortened, which is useful for increasing cavities and reducing wiring capacitance, and also reduces wire bonding. Since it is easy to manufacture, it is also advantageous in terms of manufacturing cost.
第１図は本発明に係る半導体装置の一実施例を示す平面
図、第２図は第１図の装置をメタルシール型パッケージ
に実装した場合の平面図、第３図は第１図の装置をサー
ディプ又はプラスチック型・やッケージに実装した場合
の平面図、第４図は第１図の装置１′ｔをリードレスチ
ッゾキャリアに実装した場合の平面図、第５図〜第８図
は第１図における同一機能を治するパッド１３．１３’
の接続を示す回路図である。
１〜１６ ：パッド、４’、 ５’、 １２’、 １３
’：パッド４．５．１２．１３と同一機能を有するパッ
ド、Ｇｌ ｒ Ｇ２ ：リード、Ｇ３ ＋ Ｇ４ ＊
Ｇｓ’ ｒ Ｇ４’ ：フローティング防止手段、Ｇ５
１ｃ６ 、ｃ７ ：選択手段。
第 １図
第５図
亭６図
第７図
第８図
手続補正書（自発）
昭和５９年６月７２日
特許庁長官若杉和夫 殿
１、事件の表示
昭和５８年 特許願 第１１５８９１ 号２、発明の名
称
半導体装置
３、補正をする者
事件との関係 特許出願人
名称 （５２２）富士通株式会社
４、代理人
（外 ３名）
５、補正の対象
明細書の「発明の詳細な説明」の榴
６、補正の内容
１）明細書第６頁第１５行および第１６行目「４」を「
１３」と補正する。
２）明細書第６頁第１６行目
「４′」を１ｒ１３’Ｊｌと補正する。
３）明ｉ［１書第７頁第２行目
「使用されて」の後に「いない」を挿入する。
４）明細書第８頁第８行目
「ボンティ」を「ポンディ」と補正する。1 is a plan view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a plan view of the device shown in FIG. 1 mounted in a metal seal type package, and FIG. 3 is a plan view of the device shown in FIG. 1. Fig. 4 is a plan view when the device 1't of Fig. 1 is mounted on a leadless Chizzo carrier, and Figs. 5 to 8 are Pad 13.13' which serves the same function as in Fig. 1
FIG. 2 is a circuit diagram showing the connections. 1-16: Pad, 4', 5', 12', 13
': Pad with the same function as pad 4.5.12.13, Gl r G2: Lead, G3 + G4 *
Gs' r G4': Floating prevention means, G5
1c6, c7: selection means. Figure 1 Figure 5 Pavilion 6 Figure 7 Figure 8 Procedural amendment (spontaneous) June 72, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1. Indication of the case 1988 Patent Application No. 115891 2. Invention Name of semiconductor device 3. Relationship with the case of the person making the amendment Name of the patent applicant (522) Fujitsu Ltd. 4. Agent (3 others) 5. 6. Contents of amendment 1) Change “4” in page 6, line 15 and line 16 of the specification to “
13”. 2) Correct "4'" on page 6, line 16 of the specification to 1r13'Jl. 3) Mei [Book 1, page 7, line 2, insert ``not used'' after ``used.'' 4) "Bonti" on page 8, line 8 of the specification is corrected to "pondi".
Claims (1)
能を有するｉｅラッド志を電気的に接続する手段を設け
、且つ該同一機能を有する複数個の・ぐラドのうちの少
なくとも１つを除く所望の・フッドのみに選択的にパッ
ケージのリードへのワイヤぎンディングを飾したことを
特徴とする半導体装置。 ２、前記電気的接続手段が、前記同一機能を有するパッ
ド同志を接続するだめの配線を有する特許請求の範囲第
１項に記載の半導体装置。 ３、前記電気的接続手段が、前記同一機能を有する各パ
ッドに接続され且つ並列に内部回路に接続された複数の
ダートを有する特許請求の範囲第１項に記載の半導体装
置。 ４、同一機能を有する・フッドを複数個配置し、前記同
一機能を有する各パッドに接続され且つ並列に内部回路
に接続された複数のダートを設け、前記同一機能を有す
る各・ぐラドに電位フローティング防止手段を接続した
ことを特徴とする半導体装置。 ５、同一機能を有するパッドを複数個配置し、前記同一
機能を有する各パッドに接続され且つ並列に内部回路に
接続された複数のダートを設け、前記同一機能を有する
各パッドに電位フローティング防止手段を接続し、該各
電位フローティング防止手段を選択的に動作させる選択
手段を設けたことを特徴とする半導体装置。[Claims] 1. A plurality of pads having the same function are arranged, a means is provided for electrically connecting the pads having the same function, and a plurality of pads having the same function are provided. A semiconductor device characterized in that only desired hoods except at least one of the hoods are selectively decorated with wire binding to leads of a package. 2. The semiconductor device according to claim 1, wherein the electrical connection means has wiring for connecting the pads having the same function. 3. The semiconductor device according to claim 1, wherein the electrical connection means includes a plurality of darts connected to each pad having the same function and connected in parallel to an internal circuit. 4. A plurality of hoods having the same function are arranged, a plurality of darts are connected to each pad having the same function and connected to the internal circuit in parallel, and a potential is applied to each hood having the same function. A semiconductor device characterized in that a floating prevention means is connected. 5. Arranging a plurality of pads having the same function, providing a plurality of darts connected to each pad having the same function and connected to the internal circuit in parallel, and providing potential floating prevention means for each pad having the same function. What is claimed is: 1. A semiconductor device comprising a selection means for selectively operating each potential floating prevention means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58115891A JPH0763066B2 (en) | 1983-06-29 | 1983-06-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58115891A JPH0763066B2 (en) | 1983-06-29 | 1983-06-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS609134A true JPS609134A (en) | 1985-01-18 |
| JPH0763066B2 JPH0763066B2 (en) | 1995-07-05 |
Family
ID=14673749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58115891A Expired - Lifetime JPH0763066B2 (en) | 1983-06-29 | 1983-06-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0763066B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6098645A (en) * | 1983-11-02 | 1985-06-01 | Mitsubishi Electric Corp | Manufacture of ic package |
| JPS6251231A (en) * | 1985-08-30 | 1987-03-05 | Fujitsu Ltd | Semiconductor integrated circuit device |
| US4974053A (en) * | 1988-10-06 | 1990-11-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for multiple packaging configurations |
| US5287000A (en) * | 1987-10-20 | 1994-02-15 | Hitachi, Ltd. | Resin-encapsulated semiconductor memory device useful for single in-line packages |
| JP2006286688A (en) * | 2005-03-31 | 2006-10-19 | Elpida Memory Inc | Semiconductor device |
| JP2006339338A (en) * | 2005-06-01 | 2006-12-14 | Elpida Memory Inc | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192046A (en) * | 1981-05-21 | 1982-11-26 | Fujitsu Ltd | Integrated circuit device |
| JPS59100550A (en) * | 1982-11-30 | 1984-06-09 | Mitsubishi Electric Corp | Semiconductor device |
-
1983
- 1983-06-29 JP JP58115891A patent/JPH0763066B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192046A (en) * | 1981-05-21 | 1982-11-26 | Fujitsu Ltd | Integrated circuit device |
| JPS59100550A (en) * | 1982-11-30 | 1984-06-09 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6098645A (en) * | 1983-11-02 | 1985-06-01 | Mitsubishi Electric Corp | Manufacture of ic package |
| JPS6251231A (en) * | 1985-08-30 | 1987-03-05 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JPH0455333B2 (en) * | 1985-08-30 | 1992-09-03 | Fujitsu Ltd | |
| US5287000A (en) * | 1987-10-20 | 1994-02-15 | Hitachi, Ltd. | Resin-encapsulated semiconductor memory device useful for single in-line packages |
| US4974053A (en) * | 1988-10-06 | 1990-11-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for multiple packaging configurations |
| JP2006286688A (en) * | 2005-03-31 | 2006-10-19 | Elpida Memory Inc | Semiconductor device |
| JP2006339338A (en) * | 2005-06-01 | 2006-12-14 | Elpida Memory Inc | Semiconductor device |
| JP4618598B2 (en) * | 2005-06-01 | 2011-01-26 | エルピーダメモリ株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0763066B2 (en) | 1995-07-05 |
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