JPS6085489A - Memory circuit device - Google Patents

Abstract

PURPOSE:To provide the device with multiple system reading line of high integration density by precharging a common output line by an element exclusively used for precharging. CONSTITUTION:A common output line OL1 is precharged by an FETT13 and becomes high level. That is, when an FETT12 is in the state of non-conduction, phiPC is made low level, and MOSFETT13 for precharging becomes on state and the output line OL1 is made high level. Then, phiPC becomes high level and the FETT13 is made off state. However, the otput line OL1 is kept in high level by charge accumulated in parasitic capacity, etc. After this, when a clock signal phiC becomes high level, and the FETT12 becomes to the conduction state, the output line OL1 becomes low level or high level depending on whether a signal applied to the gate of an MOSFETT11 is high level or low level. The output data is latched by a proper latch circuit when necessary, and supplied to a display unit, etc. Thus, a memory device having multiple system reading line of high integration density can be realized.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is particularly effective when applied to a semiconductor memory device. For example, the present invention relates to a technique that is particularly effective when applied to a semiconductor memory device. It is related to technology.

[Background technology]

Prior to the present invention, the inventor considered a semiconductor memory device as shown in FIGS. 1 and 2 as a semiconductor memory device. FIG. 1 is a schematic diagram of a semiconductor memory device, and FIG. 2 is a partial circuit diagram thereof.

In FIG. 1, UC, . . . , UCnm are memory cells each storing information to be displayed.

Information from the desired memory cell is sent to the output line OL or OL.
n to a display device (not shown), which causes the display device to display a pattern according to the information from the memory cells. DL, DL, word line WL, and P-channel MO8FET T1.

'r, IT? t 'I'll and N channel M
O8FETT.

'r, + 'r, l 're l Ta I T1
Consists of 0. In addition, in this specification, the same or corresponding parts are indicated by the same reference numerals in the drawings.

This memory device is a static R used for driving an LCD (liquid crystal display), etc. in a calculator IC, etc.
It's A'M. In this type of memory, in addition to normal reading, a method is adopted in which the memory contents of the cells are directly drawn out using a clocked inverter as shown in FIG. 2 through an output line OL dedicated to a display device. However, in this method, for one memory cell, that is, one unit circuit, one
The inventor revealed that it is difficult to create a large capacity memory because 0 MOSFETs are required.

[Purpose of the invention]

One object of the present invention is to provide a memory device having multiple read lines with high integration density.

One object of the present invention is to provide a memory device that has high integration density and that allows memory contents to be read out substantially independently of normal memory operations.

One object of the present invention is to provide a semiconductor memory device having multiple read lines with a small number of elements per cell.

The above and other objects and novel features of the present invention include:
It will become clear from the description herein and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the present invention provides a memory device having multiple readout E lines in which the number of elements in the memory content detection inverter can be reduced by precharging a common output line with an element dedicated to precharging.

〔Example〕

The present invention will be explained according to examples. FIG. 3 is a specific circuit diagram of a cell portion of a memory device according to an embodiment of the present invention. In the same figure, T11 and Tl2 are N-channel MO8
FET, T, indicates a P-channel MO8FET. Other symbols are the same as in FIG.

In FIG. 3, an ordinary static CMOS memory cell is constituted by MO8FETT, ~T6+ complementary data lines DL, DL, and a word line. OL is a read line other than the normal data line DL and 3, and the contents of the memory cell can be read even when the word line WL is not selected. F E T T,
, %T, constitutes a readout circuit.

φpc is a precharge signal for controlling MOSFET QCs for precharging the output line OL.

The operation of this memory circuit will be explained. The read operation described here is performed when normal memory read/write operations are not being performed, more precisely when the FETs T, T6 are in a non-conducting state.

At this time, the common output line OL is precharged by Tl11 and becomes high level. (In this application, positive logic is adopted.) That is, when 'rtt is in a non-conducting state, φpc
is set to low level, MO8FET for precharging
+s is turned on, and the output line OL is set to high level. Next, φpc becomes high level and F E
T'rls'd off state, but output line O
It is kept at a high level by the charge accumulated in L, parasitic capacitance, etc. After that, the clock signal φ. When becomes high level and FET T, , becomes conductive, MO8
Depending on whether the signal applied to the gate of the FETT is high or low, the output line OL, , becomes low or high. This output data is latched by an appropriate notch circuit as required and supplied to a display device or the like.

The configuration of this embodiment will be explained in more detail. The unit cells (memory cells) in FIG. 1 are connected to a common output line OL, etc., so that the data in the memory cells, that is, the binary information memory means, can be read out without using the normal data line DL or DL. It is configured. Output terminal OL,
etc., are connected, for example, to a suitable latch circuit so that they can be supplied to an LCD or the like. The layout of the output lines may be parallel to the data lines, parallel to the word lines, or in other ways as required.

In FIG. 3, the precharge MO8FETTIM dynamically sets the output line OL to V, for example. .

It is provided to set the level. That is, O
Before data is output from L, to the outside, T,3 becomes conductive due to the precharge signal φpc, and OL, becomes v
Precharge to cc level. Therefore, at least one MO8FETVi for precharging is required for each output line. However, in order to prevent delays due to wiring, it is effective to arrange them at both ends of the output line or at various locations.

As mentioned above, the output line is set to v by MO8FETT, 3.
After ccVC is set, Tl1l becomes non-conductive, but this state is dynamically maintained by the parasitic capacitance of the output terminal OL. In FIG. 3, the clock pulse φ. is set to high level, M08FEi
'T, conducts, the binary information memory means c
The information stored in the Mos static memory cell turns the MO8FET T'u on or off. Memory information, ie, memory cell MOS F E
T T3 , T4.

When the common connection point of T, is at a high level, Tl+ is rendered conductive, causing the output line OL to be at a low level. Conversely, when the memory information is at a low level, 'I'll is rendered non-conductive, and the output line OL is kept at a high level, that is, at the vcc level.

〔effect〕

By precharging the common output line and performing dynamic operation, it is possible to realize a memory device having multiple read lines with high integration density.

By precharging the output line with a dedicated MOSFET, the memory contents can be read directly from the memory cell at high speed.

MO for precharging common to each memory cell on the output line
By installing 8 FETs and operating dynamically,
The number of elements constituting a memory cell can be reduced.

By providing a separate circuit for reading data in addition to the normal memory read line.

It is possible to provide memory circuit technology that is compatible with microcomputer technology.

Although the invention made by the present inventor has been specifically explained using examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof. Needless to say. For example, although the CMOS memory has been described as the binary information memory means, N
It goes without saying that channel MOS static and dynamic RAM, shift registers, COD, etc. can also be used. Furthermore, in the above description, a memory circuit having multiple readout lines has been described, but the invention is not limited to this. For example, one line may be used only for writing,
It goes without saying that the present invention can also be applied to systems having multiple memory information input/output lines in the sense that other systems are used only for reading.

Further, in the above embodiment, the precharging of the output line in FIG. 3 is performed by a MOSFET driven by a clock pulse.
Although this is done by ET, it goes without saying that static circuits such as simply adding a load resistor and other modifications are also corridors.

[Application field]

In the above description, the invention made by the present inventor has mainly been explained with respect to reading of CMOS static RAM, which is the field of application behind the invention, but it is not limited thereto. For example, writing of static RAM, bipolar RAM, It can also be applied to reading various types of RAM, etc. The present invention is applicable to at least information storage means having a plurality of read or write systems.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the present invention and a memory device studied by the inventor, FIG. 2 is a specific circuit diagram of the unit circuit of FIG. 1 studied by the inventor, and FIG. FIG. 2 is a specific circuit diagram of the unit circuit shown in the figure according to the present invention. OL1 to OLn: Output lines, UC, to a display device, etc. ~UCnm: Unit circuit of memory cell section, DPR: Memory device used for display devices, etc., DL and *R: Complementary data line, WL: Word line, 'r, l T, ! T, ＋
To + Tls: P-channel MO8FET, T!
,T. ~ Ta s Ta + T+o ”=T12: N-channel MO8FET, φ. and Oka.: Complementary clock pulse. Agent Patent attorney Akio Takahashi'-゛・. (11,. Ql) Fig. 1 Fig. 2

Claims (1)

[Claims] 1. (a) Binary information memory means (b) Output terminal (c) Means for dynamically setting the output terminal to the first value of the two values (d) The memory A memory circuit device having multiple readout lines, comprising means for setting the output terminal to a second value only when the output of the means is one of the two values.