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KR940002860B1 - Ram lead / light circuit - Google Patents

Ram lead / light circuit Download PDF

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Publication number
KR940002860B1
KR940002860B1 KR1019900012450A KR900012450A KR940002860B1 KR 940002860 B1 KR940002860 B1 KR 940002860B1 KR 1019900012450 A KR1019900012450 A KR 1019900012450A KR 900012450 A KR900012450 A KR 900012450A KR 940002860 B1 KR940002860 B1 KR 940002860B1
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clock
clock signal
signal
output
inverter
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KR920005154A (en
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정수목
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금성일렉트론 주식회사
문정환
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음.No content.

Description

램 리드/라이트 회로Ram lead / light circuit

제1도는 종래의 램 리드/라이트 회로.1 is a conventional ram lead / light circuit.

제2도는 종래 회로에 따른 각 신호 타이밍도.2 is a signal timing diagram according to a conventional circuit.

제3도는 본 발명에 다른 램 리드/라이트 회로도.3 is a RAM lead / light circuit diagram according to the present invention.

제4도는 본 발명 회로에 따른 각 신호 타이밍도.4 is a signal timing diagram according to the circuit of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1, 2, 37 : 엔모스트랜지스터 3, 4, 35, 36 : 피모스트랜지스터1, 2, 37: NMOS transistors 3, 4, 35, 36: PMOS transistors

13, 14 : 인버터 28 : 램셀13, 14: inverter 28: ramcell

31-34 : 클락트 인버터31-34: Clock Inverter

본 발명은 램 리드/라이트 회로에 관한 것으로, 특히 램셀의 라이트(Write) 및 리드(Read) 오퍼레이션(Operation) 회로를 디지탈 회로로 간단하게 구성한 램 리드/라이트 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ram read / write circuit, and more particularly, to a ram read / write circuit in which a write and read operation circuit of a ram cell is simply configured as a digital circuit.

종래에는 제1도에 도시된 바와같이 엔모스트랜지스터(5,6) 및 엔모스트랜지스터(7,8)의 드레인이 각각 서로 연결되고, 엔모스트랜지스터(5,6) 및 엔모스트랜지스터(6,7)의 게이트가 각기 연결되어 센스앰프(25)가 구성되고, 데이타(Data)(DA) 및 라이트 인에이블 신호(Write Enable)

Figure kpo00001
를 입력받는 노아게이트(19)의 출력과, 라이트 인에이블 신호
Figure kpo00002
및 인버터(15)를 통해 인가되는 데이타(DA)를 입력받는 노아게이트(18)의 출력이 상기 센스앰프(25)의 게이트 입력(C),(D)으로 각기 인가되며, 그 센스앰프(25)의 출력(BIT,
Figure kpo00003
)은 엔모스트랜지스터(10,12)의 소오스(Source)가 되고, 피모스트랜지스터(9,11)와 엔모스트랜지스터(10,12)의 게이트 입력에는 리드 인에이블신호(RE)가 연결되며, 피모스트랜지스터(9)와 엔모스트랜지스터(10)의 드레인 및 피모스트랜지스터(11)와 엔모스트랜지스터(12)의 드레인이 각각 연결되어(F와 G 노드) 낸드게이트(16,17)의 각 일측 입력이 되고, 낸드게이트(16,17)의 출력은 각각 낸드게이트(17,16)의 입력으로 궤환되고 낸드게이트(18)의 출력은 램데이타 출력이 되고, 또 상기 센스앰프(5)의 출력(BIT),(
Figure kpo00004
)은 엔모스트랜지스터(1,2), 피모스트랜지스터(3,4) 및 인버터(13,14)로 구성되는 램셀(28)의 피모스 트랜지스터(3,4)와 엔모스트랜지스터(1,2)의 소오스가 되고 엔모스트랜지스터(1)의 드레인은 인버터(13,14)의 서로 역방향 병렬 연결을 통해 엔모스트랜지스터(2)의 드레인과 연결되고, 엔모스트랜지스터(1,2)의 게이트에는 어드레스신호(AD)가 인가되고, 피모스트랜지스터(3,4)의 게이트에는 프리챠지(Precharge)(
Figure kpo00005
)전압이 인가되는 구성이고, 상기 회로에서 엔모스트랜지스터(5-8), 인버터(15) 및 노아게이트(18,19)로 구성된 회로는 라이트(Write)회로(26)이고, 피모스트랜지스터(9,11), 엔모스트랜지스터(10,12) 및 낸드게이트(16,17)로 구성된 회로는 리드(Read)회로(27)이다.In the related art, as shown in FIG. 1, the drains of the n-mo transistors 5 and 6 and the n-mo transistors 7 and 8 are connected to each other, respectively, and the n-mo transistors 5 and 6 and the n-mo transistor 6, The gates of 7) are connected to each other to form the sense amplifier 25, and the data (DA) and the write enable signal (write enable)
Figure kpo00001
The output of the NOA gate 19 receiving the signal and the write enable signal
Figure kpo00002
And an output of the NOA gate 18, which receives data DA applied through the inverter 15, is respectively applied to the gate inputs C and D of the sense amplifier 25, and the sense amplifier 25. ) Output (BIT,
Figure kpo00003
) Is a source of the NMOS transistors 10 and 12, and a read enable signal RE is connected to the gate inputs of the PMOS transistors 9 and 11 and the NMOS transistors 10 and 12. The drains of the PMOS transistors 9 and the NMOS transistors 10 and the drains of the PMOS transistors 11 and the NMOS transistors 12 are connected (F and G nodes), respectively. It becomes one side input, and the outputs of the NAND gates 16 and 17 are fed back to the inputs of the NAND gates 17 and 16, respectively, and the outputs of the NAND gates 18 are ram data outputs. Output (BIT), (
Figure kpo00004
) Is a PMOS transistor (3,4) and the MOS transistor (1,2) of the ram cell 28 consisting of the n-mo transistor (1,2), the PMOS transistor (3,4) and the inverter (13,14) Source) and the drain of the NMOS transistor 1 is connected to the drain of the NMOS transistor 2 through the inverted parallel connection of the inverters 13 and 14, and the gate of the NMOS transistors 1 and 2 The address signal AD is applied and a precharge (Precharge) is applied to the gates of the PMOS transistors 3 and 4.
Figure kpo00005
Voltage is applied, and the circuit composed of the NMOS transistors 5-8, the inverters 15, and the NOA gates 18, 19 is a write circuit 26, and a PMOS transistor. The circuit composed of 9, 11, n-MOS transistors 10, 12, and NAND gates 16, 17 is a read circuit 27.

상기 구성회로의 동작상태를 제2도의 타이밍도를 참조하여 설명하면, 라이트 인에이블신호

Figure kpo00006
가 '로우'로 떨어지기 이전(t1이전)에는 램셀(28)의 값은 임의의 값을 가지게 되나, 제2도 'D'와 같은 데이타(DA)를 데이타 입력단에 인가하고, 라이트 인에이블신호
Figure kpo00007
를 로우로 하면(제2도 'B'파형에서 t1-t2구간), 데이타(DA)가 고전위 이때 노아게이트(18)에서 고전위 신호가 출력되고 노아게이트(19)에서 저전위 신호가 출력되어 엔모스 트랜지스터(6,7)가 도통되고 엔모스 트랜지스터(5,8)가 오프되며, 데이타(DA)가 저전위 일때 상기와 반대로 되어 엔모스 트랜지스터(6,7)가 오프되고 엔모스 트랜지스터(5,8)가 도통되며, 이에따라 출력(BIT)에는 데이타(DA)의 값이, 출력(
Figure kpo00008
)에는 데이타(DA)의 값이 반전 출력되어 기록상태로 된다.The operation state of the configuration circuit will be described with reference to the timing diagram of FIG.
Figure kpo00006
The value of the ram cell 28 has an arbitrary value before the voltage falls to 'low' (before t1), but data DA such as FIG. 2 'D' is applied to the data input terminal and the write enable signal is applied.
Figure kpo00007
To low (Fig. 2, section t1-t2 in the 'B' waveform), when the data DA is at high potential, the high potential signal is output from the noble gate 18 and the low potential signal is output from the noble gate 19. The NMOS transistors 6 and 7 are turned on and the NMOS transistors 5 and 8 are turned off. When the data DA is at low potential, the NMOS transistors 6 and 7 are reversed and the NMOS transistors 6 and 7 are turned off. (5,8) is turned on. Accordingly, the value of the data DA is displayed in the output BIT.
Figure kpo00008
) Is inverted and outputted to the recording state.

라이트 인에이블 신호

Figure kpo00009
를 '하이'로 유지한 상태에서 리드인에이블 신호(RE)가 '하이'(제2도 'C'파형에서 t3-t4구간)가 되면, 램셀(RAM Cell)(28)의 값이 0로 출력되어 리드상태로 된다.Light enable signal
Figure kpo00009
When the read enable signal RE becomes 'high' (t3-t4 section of the second waveform 'C' waveform) while maintaining 'high', the value of the RAM cell 28 becomes zero. It is output to the lead state.

리드 인에이블 신호(RE)가 '로우'인 동안은 그 이전에 출력된 데이타값을 래치하게 된다.While the read enable signal RE is 'low', the data value previously output is latched.

그런데 상기와 같은 종래의 램셀 리드/라이트 회로는 소자 수가 많아 레이아웃 면적이 커지고 그에 따른 가격이 증가하게 되는 단점이 있었다.However, the conventional ram cell lead / write circuit as described above has a disadvantage in that the number of devices increases and the layout area increases, thereby increasing the cost.

본 발명은 이러한 종래의 단점을 감안하여, 디지탈 회로에 의해 간단한 구조의 램 리드/라이트 회로를 창안한 것으로, 이를 첨보된 도면을 참조하여 상세히 설명하면 다음과 같다.In view of the above disadvantages, the present invention has been invented a RAM lead / light circuit having a simple structure by a digital circuit, which will be described in detail with reference to the accompanying drawings.

먼저 제3도에서 그 구성을 보면, 어드레스 신호(AD)가 클락트 인버터(Clocked Inverter)(31)를 거쳐 램셀(28)의 엔모스트랜지스터(1,2)의 게이트신호가 되고 출력(

Figure kpo00010
),(BIT)라인에 프리챠지(Precharge)를 위하여 피모스트랜지스터(3,4)가 연결되고 피모스트랜지스터(3,4)의 게이트 입력에는 클락신호(CK1)가 인가되며, 데이타(DA)가 클락트 인버터(32)를 거쳐 출력(
Figure kpo00011
) 라인에 연결되는 동시에 클락트 인버터(33)를 다시 통해 출력(BIT)라인에 연결되고, 상기 출력(
Figure kpo00012
)라인은 클락트 인버터(34)를 통해 피모스트랜지스터(36)의 게이트와 연결된다.First, the configuration of FIG. 3 shows that the address signal AD becomes the gate signal of the NMOS transistors 1 and 2 of the ram cells 28 through the clocked inverter 31 and the output (
Figure kpo00010
PIM transistors 3 and 4 are connected to the (BIT) lines for precharge, and the clock signal CK1 is applied to the gate inputs of the PMOS transistors 3 and 4, and the data DA is applied. Output via clock inverter 32
Figure kpo00011
) And at the same time through the clock inverter 33 to the output (BIT) line, the output (
Figure kpo00012
The line is connected to the gate of the PMOS transistor 36 through the clock inverter 34.

그리고 클락트 인버터(32,33)의 P형 트랜지스터 게이트 입력은

Figure kpo00013
가 되고 N형 트랜지스터의 게이트 입력은 CKW가 되며, 피모스트랜지스터(35,36) 및 엔모스트랜지스터(37)는 전원(VDD)과 접지사이에 직렬로 연결되고, 피모스트랜지스터(35)의 게이트 입력에는 클락신호(
Figure kpo00014
)가 인가되고, 엔모스트랜지스터(37)의 게이트 입력에는 클락신호(CK1)가 인가되며 피모스트랜지스터(36)와 엔모스트랜지스터(37)의 드레인에는 데이타(DA)신호가 인가되며, 클락트 인버터(34)의 P형 트랜지스터 게이트 입력은
Figure kpo00015
가 되고, N형 트랜지스터 게이트 입력은 CKR이다.The P-type transistor gate inputs of the clock inverters 32 and 33
Figure kpo00013
The gate input of the N-type transistor is CKW, and the PMOS transistors 35 and 36 and the NMOS transistor 37 are connected in series between the power supply VDD and the ground, and the gate of the PMOS transistor 35 is The clock signal at the input
Figure kpo00014
Is applied, the clock signal CK1 is applied to the gate input of the NMOS transistor 37, and the data DA signal is applied to the drain of the PMOS transistor 36 and the NMOS transistor 37. The P-type transistor gate input of the inverter 34 is
Figure kpo00015
The N-type transistor gate input is CKR.

이와같이 구성된 본 발명의 작용효과를 상세히 설명하면 다음과 같다.If described in detail the effects of the present invention configured as described above.

어드레스 신호(AD)가 인가된 상태에서 제4도 'A'의 클락신호(CK1)가 '로우'로 되면서(제4도에서 t1) 클락트 인버터(31)가 도통상태로 되어 그 어드레스 신호(AD)가 그 클락트 인버터(31)를 통하게 되고, 이에 따라 램셀(28)의 워드라인(Word Line)이 선택되어('하이')램셀(28)이 엔모스트랜지스터(1,2)가 '온'되며, 또한 피모스트랜지스터(3,4)가 '온'되어 출력(),(BIT)이 램셀(28)의 인이셜(Initial)값에 따라 출력(

Figure kpo00017
,BIT)에 충전된다(제4도에서 t1-t2구간).When the clock signal CK1 of FIG. 4 'A' becomes 'low' while the address signal AD is applied (t1 in FIG. 4), the clock inverter 31 becomes conductive and the address signal ( AD is passed through the clock inverter 31, and accordingly, the word line of the ram cell 28 is selected ('high'), so that the ram cell 28 causes the enMOS transistors 1 and 2 to become 'high'. ON ', and the PMOS transistors 3 and 4 are' ON 'to output ), (BIT) is output according to the initial value of the ramcell 28
Figure kpo00017
, BIT) (t1-t2 in Figure 4).

이때 클락신호(CK1)는 상기 클락신호

Figure kpo00018
와 반대전위인
Figure kpo00019
상태이므로 엔모스트랜지스터(37)는 도통된다.At this time, the clock signal CK1 is the clock signal.
Figure kpo00018
Antipotential to
Figure kpo00019
Since it is a state, the MOS transistor 37 is turned on.

그후, 제4도 'B'의 클락신호(

Figure kpo00020
)가 '로우'로 되면(제4도에서 t3), 클락트 인버터(32,33)가 '온'되고, 이때 제4도 'C'의 클락신호(
Figure kpo00021
)가 '하이'상태이므로 피모스트랜지스터(35)가 오프되고, 제4도 'A'의 클럭신호
Figure kpo00022
가 '하이'여서 클럭신호(CK1)가 '로우'상태이므로 엔모스트랜지스터(37)가 오프된다.Thereafter, the clock signal of FIG.
Figure kpo00020
) Becomes 'low' (t3 in FIG. 4), the clock inverters 32 and 33 are 'on', and the clock signal of FIG.
Figure kpo00021
) Is the 'high' state, the PMOS transistor 35 is off, the clock signal of FIG.
Figure kpo00022
Since the clock signal CK1 is in the low state, the NMOS transistor 37 is turned off.

따라서, 이때 제4도 'F'의 데이타(DA)가 그 클락트 인버터(32)를 통해 반전되어 램셀(28)의 출력(

Figure kpo00023
)으로 됨과 아울러 클락트 인버터(33)를 통해 다시 반전되어 램셀(28)의 출력(BIT)으로 되어(제4도의 t3-t4구간) 라이트 상태로 된다.Therefore, at this time, the data DA of FIG. 4 'F' is inverted through the clock inverter 32 so that the output of the ram cell 28 (
Figure kpo00023
In addition, it is inverted again through the clock inverter 33 to become the output BIT of the ram cell 28 (t3-t4 section in FIG. 4) to be in the light state.

상기 설명된 바와같이 램셀(28)에 기록된 후 제4도 'D'의 클락신호(

Figure kpo00024
)가 '로우'로 되면(제4도에서 t5), 클락트 인버터(34)가 '온'되어 램셀(28)에 저장된 데이타가 'D'노드로 반전출력되어 유지되고, 이때 제4도 'A'의 클락신호
Figure kpo00025
가 '로우'여서 클락신호(CK1)가 '하이'로 되므로 그 클락신호(CK1)에 의해 엔모스트랜지스터(37)가 '온'되어 데이타(DA)단자가 프라챠지(제4도의 t5-t6구간)된다.As described above, the clock signal of FIG.
Figure kpo00024
) Becomes 'low' (t5 in FIG. 4), the clock inverter 34 is 'on' so that the data stored in the ram cell 28 is inverted and maintained as the 'D' node. A 'clock signal
Figure kpo00025
Since the clock signal CK 1 becomes high because the clock signal CK 1 is 'low', the MOS transistor 37 is turned on by the clock signal CK1, and the data DA terminal is charged (t5- in FIG. 4). section t6).

이후 제4도 'C'의 클락신호(

Figure kpo00026
)가 '로우'로 되면(제4도에서 t7) 피모스트랜지스터(35)가 '온'되어 'D'노드의 값에 따라 데이타(DA)단자에 반전된 출력이 나타나게 된다(제4도의 t7-t8 구간).Thereafter, the clock signal of FIG.
Figure kpo00026
) Becomes 'low' (t7 in FIG. 4), the PMOS transistor 35 is 'on', and an inverted output appears at the data DA terminal according to the value of the 'D' node (t7 in FIG. 4). -t8 interval).

그리고 상기 회로는 클럭신호(CK1)가 50KHz 이상일때 안정되게 동작한다.The circuit operates stably when the clock signal CK1 is 50 KHz or more.

이상에서와 같이 본 발명은 램셀의 라이트 및 리드 회로를 디지탈 회로로 간단히 구성하여 레이아웃 면적을 줄이고 그에 따른 가격도 감소시키게 되는 효과가 있게 된다.As described above, the present invention has an effect of simply configuring the light and lead circuits of the ram cells with digital circuits, thereby reducing the layout area and thus reducing the cost.

Claims (1)

어드레스신호(AD)가 클락신호
Figure kpo00027
의 제어를 받는 클락트 인버터(31)를 통해 램셀(28)의 엔모스트랜지스터(1,2) 게이트 신호로 인가되게 연결되고, 데이타(DA)가 클락신호(
Figure kpo00028
)의 제어를 받는 클락트 인버터(32)를 통해 상기 램셀(28)의 출력(
Figure kpo00029
)라인에 연결됨과 동시에 상기 클락신호(
Figure kpo00030
)의 제어를 받는 클락트 인버터(33)를 다시 통해 그 램셀(28)의 출력(BIT)라인에 연결되며, 전원(VDD)이 클럭신호
Figure kpo00031
를 게이트에 인가받는 피모스트랜지스터(3)(4)를 각기 통해 상기 출력(
Figure kpo00032
),(BIT)라인에 인가되게 연결되며, 상기 클럭(
Figure kpo00033
) 라인이 클락신호
Figure kpo00034
의 제어를 받는 인버터(34)를 통해 피모스트랜지스터(36)의 게이트에 연결되고, 전원(VDD)이 클락신호
Figure kpo00035
)를 게이트에 인가받는 피모스트랜지스터(35) 및 상기 피모스트랜지스터(36)를 통한후 게이트에 클락신호(CK1)를 인가받는 엔모스트랜지스터(37)의 드레인에 인가되게 연결됨과 아울러 그 연결점에 상기 데이타(DA)가 인가되게 연결되어 구성된 것을 특징으로 하는 램 리드/라이트 회로.Address signal AD is clock signal
Figure kpo00027
It is connected to the gate signal of the MOS transistor (1, 2) of the ram cell 28 through the clock inverter 31 under the control of the data, the data DA is the clock signal (
Figure kpo00028
The output of the ram cell 28 through the clock inverter 32 under the control of
Figure kpo00029
Is connected to the line and the clock signal (
Figure kpo00030
Is connected to the output (BIT) line of the gram cell 28 through the clock inverter 33 under the control of
Figure kpo00031
Is output through the PMOS transistors 3 and 4, respectively,
Figure kpo00032
Is connected to the (BIT) line and the clock (
Figure kpo00033
) Line is clock signal
Figure kpo00034
It is connected to the gate of the PMOS transistor 36 through the inverter 34 under the control of the power supply (VDD) the clock signal
Figure kpo00035
) Is applied to the drain of the NMOS transistor 37 receiving the clock signal CK1 through the PMOS transistor 35 and the PMOS transistor 36 to which the gate is applied. And the data DA are configured to be connected to each other.
KR1019900012450A 1990-08-13 1990-08-13 Ram lead / light circuit Expired - Fee Related KR940002860B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900012450A KR940002860B1 (en) 1990-08-13 1990-08-13 Ram lead / light circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900012450A KR940002860B1 (en) 1990-08-13 1990-08-13 Ram lead / light circuit

Publications (2)

Publication Number Publication Date
KR920005154A KR920005154A (en) 1992-03-28
KR940002860B1 true KR940002860B1 (en) 1994-04-04

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KR1019900012450A Expired - Fee Related KR940002860B1 (en) 1990-08-13 1990-08-13 Ram lead / light circuit

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