JPS6072229A - Electrode and wiring structure of semiconductor device - Google Patents
Electrode and wiring structure of semiconductor deviceInfo
- Publication number
- JPS6072229A JPS6072229A JP17801583A JP17801583A JPS6072229A JP S6072229 A JPS6072229 A JP S6072229A JP 17801583 A JP17801583 A JP 17801583A JP 17801583 A JP17801583 A JP 17801583A JP S6072229 A JPS6072229 A JP S6072229A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- mask
- ion implantation
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 19
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- 230000005465 channeling Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000003292 diminished effect Effects 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 14
- 229910052750 molybdenum Inorganic materials 0.000 description 14
- 239000011733 molybdenum Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- -1 arsenic ions Chemical class 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高融点金机からなる電極・配線ケ有する半導体
装置に係シ、特に上記金属をマスクとしてイオン打込全
行ない、半導体基板内に自己整合的に不純物層を設ける
ことを特徴とする半導体装置に好適な電極および配線構
造体に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having electrodes and wiring made of a high-melting point metal. The present invention relates to an electrode and wiring structure suitable for a semiconductor device characterized in that the present invention is provided with an electrode and a wiring structure.
モリブデンゲート電極をマスクとしてひ素イオンの打込
を行ない自己整合的にソース、ドレイン全形成するＭＯ
Ｓトランジスタにおいて、モリブデンがイオン打込のマ
スクとならず、ゲート電極下のシリコン基板までひ素が
突き貫けることが報告されている（村尾他、半導体集積
回路技術第１９回シンポジウム講演論文集、 ９６頁、
１９８０）。MO in which the source and drain are completely formed in a self-aligned manner by implanting arsenic ions using the molybdenum gate electrode as a mask.
It has been reported that in S transistors, molybdenum does not act as a mask for ion implantation, and arsenic can penetrate to the silicon substrate below the gate electrode (Murao et al., Proceedings of the 19th Symposium on Semiconductor Integrated Circuit Technology, p. 96) ,
1980).
また同報告ではこの突き負は防止のために、モリブデン
表ｍ１にシリコン窒化膜分被覆した後、イオン打込する
方法が示されている。この方法では、モリブデン膜とシ
リコン窒化膜の重ね膜をゲート電極および配線として加
工する必要がある。この加工にはプラズマエッチ吟のド
ライエンチングが用イられるが、この場合、モリブデン
およびシリコン窒化膜のエツチング速度が異なるため、
工ないし２ミクロン等の微細加工が難がしくなるという
欠点があった。In order to prevent this negative effect, the same report describes a method in which ions are implanted after coating the molybdenum surface m1 with a silicon nitride film. In this method, it is necessary to process a stacked film of a molybdenum film and a silicon nitride film as a gate electrode and wiring. Dry etching using plasma etching is used for this process, but in this case, since the etching speeds of molybdenum and silicon nitride films are different,
There was a drawback that microfabrication of microns to 2 microns or the like became difficult.
本発明の目的は高融点金塊電極および配線ケマスクとし
てイオン打込を行なう際、打込元素の電極および配線下
への突き貫け？防止するとともに従来の突き貫は防止策
の欠点であった微細加工の困難さを解決した電極および
配線構造体を提供することにある。The purpose of the present invention is to penetrate the implanted element under the electrode and wiring when performing ion implantation as a high melting point gold bullion electrode and wiring mask. It is an object of the present invention to provide an electrode and wiring structure that prevents penetration and solves the difficulty of microfabrication, which is a drawback of conventional penetration prevention measures.
ＬＳＳ理論によるとモリブデンやタングステンに対し、
５０〜１００ＫｅＶのエネルギでひ素のイオン打込全行
なった場合、その射影飛程は１゜〜２Ｑｎｍ、分散は約
Ｉ Ｑｎｍ程度となる。したがって約３ Ｑ Ｑ ｎｍ
の膜厚のモリブデンでは完全にイオン打込のマスクにな
るはずである。このため、前述のひ素イオン打込の突き
貫けはチャンネリング効果によるものと説明されている
。ＬＳＳ理論はイオンを打込まれる金属を非晶質体と仮
定している。しかし蒸着やスパッタ法で形成したモリブ
デンやタングステンは基板面に垂直方向にのびた柱状結
晶になっており、その結晶粒径はｌＯ〜ｌＱＱｎｍで（
１１０）に配向している。このような金属膜にイオンが
垂直方向から入射すると、イオンは原子列に対し、小さ
い角度で近づくため金属原子との間に働く反発力等の作
用により、衝突することなく膜内に侵入する。したがっ
て、このようなチャンネリングの場合は衝突によるエネ
ルギ損失は小さくなシ注入イオンは深くまで侵入する。According to LSS theory, for molybdenum and tungsten,
When arsenic ions are fully implanted with an energy of 50 to 100 KeV, the projected range is 1° to 2 Qnm, and the dispersion is about IQnm. Therefore about 3 Q Q nm
A film of molybdenum with a thickness of 100 to 100 mL should perfectly serve as a mask for ion implantation. For this reason, it is explained that the penetration of the arsenic ion implantation described above is due to the channeling effect. The LSS theory assumes that the metal into which ions are implanted is an amorphous body. However, molybdenum and tungsten formed by vapor deposition or sputtering are columnar crystals that extend perpendicularly to the substrate surface, and the crystal grain size is lO~lQQnm (
110). When ions are incident on such a metal film from a vertical direction, the ions approach the atomic array at a small angle, so they enter the film without colliding with the metal atoms due to the effects of repulsive force between them and the metal atoms. Therefore, in the case of such channeling, the energy loss due to collision is small, and the implanted ions penetrate deeply.
このようなチャンネリングを防止するためには金属表面
に非晶質あるいは金属の格子配列と異なる薄膜を形成す
ることが考えられる。In order to prevent such channeling, it is conceivable to form an amorphous film or a thin film with a lattice arrangement different from that of the metal on the metal surface.
この方法として、前述のシリコン窒化膜が考λられたわ
けであるが、すでに述べたように微細加工が難かしいと
いう欠点を有する。The above-mentioned silicon nitride film has been considered as this method, but as already mentioned, it has the drawback that microfabrication is difficult.
本発明は、この欠点ケ無くシ、チャンネリングを防止す
ることを目的としている。一般に高融点金属の酸化物は
金属の結晶系と異なる。たとえばモリブデンおよびタン
グステンは立方晶系で体心立方構造であるが、その酸化
物は斜方晶系でルチル型構造等を有する。したがって、
高融点金属表面を酸化した後、イオン打込を行なえば、
金属酸化物と金属の原子配列が異なるため、チャンネリ
ングが抑止できる。この金属表面の酸化は、金属を電極
および配線に加工した後に行なえば良いため、前述のシ
リコン窒化物被覆法で問題となった微細加工の難かしさ
を無くすることができる。なお高融点金属分酸化する場
合、高温酸化では昇華および微粉末化するため、これら
を生じさせない低温で酸化する必要がある。The present invention aims to prevent channeling without this drawback. Generally, oxides of high melting point metals differ from the crystalline system of the metal. For example, molybdenum and tungsten are cubic and have a body-centered cubic structure, but their oxides are orthorhombic and have a rutile structure. therefore,
If ion implantation is performed after oxidizing the high melting point metal surface,
Channeling can be suppressed because the atomic arrangement of metal oxide and metal is different. This oxidation of the metal surface can be carried out after the metal has been processed into electrodes and wiring, thereby eliminating the difficulty in microfabrication that was a problem with the silicon nitride coating method described above. Note that when high-melting point metals are oxidized, high-temperature oxidation causes sublimation and pulverization, so it is necessary to oxidize at a low temperature that does not cause these problems.
以下、本発明の一実施例を第１図により説明する。An embodiment of the present invention will be described below with reference to FIG.
本実施例は微細ゲート電極ＭＯＳトランジスタである。This example is a fine gate electrode MOS transistor.
ｌＯΩ・ｃｍ、 Ｐ （１００） シリコン基板１ｅ局
部的に酸化し、７０Ｑｎｍの素子間分離用シリコン酸化
膜２を形成する。続いて２ｏｎｍのゲート酸化膜３を形
成した後、ＭＯＳト？ンジスタのしきい電圧調整のため
ボロンを６０ＫｅＶで７×１０” （ｃＩＩ−２）打込
む。次にスパッタ法にょシａｏ。1OΩ·cm, P (100) The silicon substrate 1e is locally oxidized to form a silicon oxide film 2 for element isolation of 70 Qnm. Subsequently, after forming a gate oxide film 3 of 2 onm, the MOS transistor is formed. In order to adjust the threshold voltage of the transistor, boron was implanted at 60 KeV to a size of 7 x 10" (cII-2). Next, sputtering was performed.
ｎｍの厚さにモリブデン膜４を形成する。続いてホトレ
ジスト５全マスクとしてＣＦ４＋２０％ｏ２ガスを用い
たプラズマエツチングにょジモリブデンを所望の形状に
加工する。次にレジストを除去後、４００ｔ？、酸素雰
囲気中でモリブデン表面を約５Ｑｎｍ酸化６する。その
後、ひ素を８０ＫｅＶＴ Ｉ Ｘ １０１６Ｃｒｎ−”
イオン打込７を行なう。次にｌＱｍｏｌのシん硅酸ガ
ラスＴｈＣＶＤ法により５００ｎｍ堆積８する。ぶつ酸
系エンチング液でコンタクト孔９を開けた後、１００（
１，２０分の窒素殊囲気熱処理を行なった後、コンタク
ト孔に露出したモリブデン酸化物を先のプラズマエンチ
ング法によシ除去し、ｌチシリコン入シアルミニウム電
極ｌＯを形成する。続いて％ ４５０ Ｃｙ ６０分の
水素熱処理を行なった後、パシベーション膜ｌｌ？形成
し、微細ゲート電極ＭＯｓトランジスタが完成する。A molybdenum film 4 is formed to a thickness of nm. Subsequently, the photoresist 5 is processed into a desired shape by plasma etching using CF4+20% O2 gas as an entire mask of molybdenum. Next, after removing the resist, 400t? , the molybdenum surface is oxidized to about 5 Qnm in an oxygen atmosphere. Then, arsenic was added to 80KeVT I X 1016Crn-”
Perform ion implantation 7. Next, 500 nm of 1 Q mol cinsilicate glass is deposited 8 by the ThCVD method. After opening the contact hole 9 with butic acid-based enching liquid, 100 (
After heat treatment in a nitrogen atmosphere for 1 to 20 minutes, the molybdenum oxide exposed in the contact hole is removed by the plasma etching method described above to form a silicon-containing sialuminium electrode IO. Subsequently, after performing hydrogen heat treatment at % 450 Cy for 60 minutes, a passivation film was formed. A fine gate electrode MOs transistor is completed.
板肉にひ素イオンが突き貫け、正常なＭＯ８＋−ランジ
スタ特性を示さなかった。Arsenic ions penetrated the plate and did not exhibit normal MO8+- transistor characteristics.
本実施例によシ形成した１、４μｍゲート長のＭＯｓ−
４−ランジスタは電源電圧５Ｖ、基板バイアス−３Ｖで
０．２４±０．０７Ｖのしきい電圧を示した。また設計
寸法１．４μｍゲート長に対し、モリブデンの加工寸法
は１．４゛μｍで標準偏差０．２μｍであった。MOs with a gate length of 1.4 μm formed according to this example.
The 4-transistor exhibited a threshold voltage of 0.24±0.07V at a power supply voltage of 5V and a substrate bias of -3V. Furthermore, with respect to the designed gate length of 1.4 μm, the processing dimension of molybdenum was 1.4 μm with a standard deviation of 0.2 μm.
【図面の簡単な説明】
嬉１図はＭＯＳトランジスタ製造工程の流れ、および各
工程で得られる断面図である。
ｌ・・・シリコン基板、２・・・菓子間分離用シリコン
酸化膜、３・・・ゲート酸化膜、４・・・モリブデン、
５・・・レジスト、６・・・モリブデン酸化膜、７・・
・ひ素イオン打込層、８・・・シん硅酸ガラス、９・・
・コンタクト孔、１０・・・１％シリコン入クシアルミ
ニウム電極１１・・・パシベーション膜。
代理人 弁理士 傅俳和挙
）へ
すφ[Brief Description of the Drawings] Figure 1 shows the flow of the MOS transistor manufacturing process and cross-sectional views obtained in each process. l... Silicon substrate, 2... Silicon oxide film for separating confectionery, 3... Gate oxide film, 4... Molybdenum,
5...Resist, 6...Molybdenum oxide film, 7...
・Arsenic ion implantation layer, 8... cinsilicate glass, 9...
- Contact hole, 10...1% silicon-containing oxidized aluminum electrode 11...passivation film. Agent: Patent Attorney Fuhai Wagyo) Hesuφ
Claims (1)
金属薄膜形成後、イオン打込工程を有する半導体装置に
おいて、イオン打込前に、上記金属表面に、同金属から
なる酸化膜を設けたことを特徴とする半導体装置の電極
・配線構造体。1. In a semiconductor device having electrodes and wiring made of a high melting point metal and having an ion implantation step after forming the metal thin film, an oxide film made of the same metal is formed on the surface of the metal before ion implantation. An electrode/wiring structure for a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17801583A JPS6072229A (en) | 1983-09-28 | 1983-09-28 | Electrode and wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17801583A JPS6072229A (en) | 1983-09-28 | 1983-09-28 | Electrode and wiring structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6072229A true JPS6072229A (en) | 1985-04-24 |
| JPH0462173B2 JPH0462173B2 (en) | 1992-10-05 |
Family
ID=16041070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17801583A Granted JPS6072229A (en) | 1983-09-28 | 1983-09-28 | Electrode and wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6072229A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6017783A (en) * | 1991-05-16 | 2000-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device using an insulated gate electrode as a mask |
| US6197702B1 (en) | 1997-05-30 | 2001-03-06 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
| US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
| US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5863170A (en) * | 1981-10-13 | 1983-04-14 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
-
1983
- 1983-09-28 JP JP17801583A patent/JPS6072229A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5863170A (en) * | 1981-10-13 | 1983-04-14 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6017783A (en) * | 1991-05-16 | 2000-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device using an insulated gate electrode as a mask |
| US6987069B2 (en) | 1997-05-30 | 2006-01-17 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6528403B2 (en) | 1997-05-30 | 2003-03-04 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6503819B2 (en) | 1997-05-30 | 2003-01-07 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6784116B2 (en) | 1997-05-30 | 2004-08-31 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US6197702B1 (en) | 1997-05-30 | 2001-03-06 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US7122469B2 (en) | 1997-05-30 | 2006-10-17 | Hitachi, Ltd. | Fabrication process of a semiconductor integrated circuit device |
| US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
| US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
| US7144766B2 (en) | 2001-03-12 | 2006-12-05 | Renesas Technology Corp. | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
| US7300833B2 (en) | 2001-03-12 | 2007-11-27 | Renesas Technology Corp. | Process for producing semiconductor integrated circuit device |
| US7375013B2 (en) | 2001-03-12 | 2008-05-20 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
| US7632744B2 (en) | 2001-03-12 | 2009-12-15 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
| US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0462173B2 (en) | 1992-10-05 |
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