JPH01122167A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase gate breakdown strength by thickly forming a gate insulating film at the peripheral end section of recrystallized silicon through a low temperature process. CONSTITUTION:An silicon layer 3 is shaped, and a resist pattern 4 coated so as to expose the peripheral end section 3a of the silicon layer is formed onto the silicon layer 3. Ions are implanted, using the resist 4 as a mask from the upper section of the silicon layer 3, the resist 4 is removed, and the surface of the silicon layer 3 is oxidized and a gate insulating layer 5 is shaped. Consequently, an oxide layer 5a is formed thickly at the external peripheral end section 3a of the recrystallized layer 3, and an internal section is oxidized at a normal silicon oxidizing rate. Accordingly, the gate insulating film 5 can be formed thickly through a low temperature process, thus the breakdown strength may be held.

Description

Detailed Description of the Invention [Summary] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for preventing gate oxide film breakdown voltage in an 801/MO5FET with a mesa structure. The purpose of the present invention is to provide a method for manufacturing a mesa type SOI/MO3FET with a high gate withstand voltage. A method for manufacturing a semiconductor device comprising the step of forming a gate metal layer after forming a silicon layer; a resist coated on the silicon layer so as to expose a peripheral edge of the silicon layer; forming a pattern, implanting ions into the silicon layer from above the silicon layer using the resist as a mask, removing the resist, and then oxidizing the surface of the silicon layer to form the gate insulating layer. shall be.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for preventing gate oxide film breakdown voltage in a Sol/MOSFET having a mesa structure.

[Conventional technology and its problems]

S OI (Silicon On I) with mesa-type structure
MO on nsulatingSubs rate)
A semiconductor device formed by forming an SFET has a higher degree of integration than a semiconductor device having a LOGO5 structure. However, the SOI/
There is a problem in that the gate insulating film of a MOSFET has a lower breakdown voltage than that of a LOGOS structure. The reason for this is that the electric field tends to concentrate at the left and right edge portions of the gate made of, for example, single crystal silicon, resulting in a problem that the breakdown voltage of the gate insulating film decreases.

In order to prevent the breakdown voltage of the gate insulating film from decreasing, (1) the gate oxide film is formed at a high oxidation temperature of, for example, 1000° C. or higher;

(2) Using a mask or the like, oxidize the periphery of a region where a semiconductor device such as an FET is to be formed, as shown in LOGO5, and form a thick oxide layer only in the periphery.

However, if the oxidation temperature is set to a high temperature when forming the gate insulating film as in (1), it goes against the trend of lowering the temperature of So+ and cannot be applied as a three-dimensional Sol device process. Furthermore, as shown in (2), if the thickness is increased only around the semiconductor device forming area, the recrystallized silicon will be oxidized from above and below, and as shown in FIG. There is a high possibility that electric field concentration will occur. Furthermore, in case (2), a long oxidation time is required, which is also inappropriate for a three-dimensional Sol device process.

An object of the present invention is to provide a method for manufacturing a mesa-type SOI/MOSFET with a high gate breakdown voltage using a low-temperature process of 800° C. or lower.

[Means for solving problems]

According to the present invention, the above problem is solved in the step of forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer, forming a gate insulating layer on the silicon layer, and then forming a gate metal layer. A method for manufacturing a semiconductor device comprising: After forming the silicon layer, a resist pattern is formed on the silicon layer so as to expose the peripheral edge of the silicon layer, and a resist pattern is formed on the silicon layer for 8 minutes from above the silicon layer. The problem is solved by a method for manufacturing a semiconductor device, characterized in that the gate insulating layer is formed by implanting ions into a silicon layer using a resist as a mask, removing the resist, and then oxidizing the surface of the silicon layer. Ru.

[For production]

According to the present invention, the gate insulating film can be formed thickly by a low-temperature process, so that breakdown voltage can be maintained.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1A, FIG. 1B, FIG. 2, FIG. 3A, and FIG. 3B are diagrams for explaining one embodiment of the present invention.

As shown in FIG. 1A, an insulating layer 2 made of 5iOz is formed on a silicon (100) substrate 1 to a thickness of about 1 μm by thermal oxidation, then the recrystallized silicon layer 3 is separated into mesa shapes, and then A resist pattern 4 is patterned to leave a width of about 2 μm (FIG. 1B) around the semiconductor device formation region of the single crystal silicon 3, and high-dose ion implantation is performed from above the recrystallized silicon layer 3. For example, in the case of an n-channel Sol/MOSFET, the B9 ion is approximately 6 X 10 I4 at 50 KeV.
Ion implantation is performed under the implantation condition of /ctl. Thereafter, the resist 4 is removed and the recrystallized silicon layer 3 is oxidized in 800'C dryoz.

A thick oxide layer 5a- is formed on the outer peripheral edge part 3a of the recrystallized layer which has been ion-implanted (doped) at a high concentration, and the inner part of the outer peripheral edge part is oxidized at a normal silicon oxidation rate. Figure 2).

Thereafter, a gate metal layer 6 made of polycrystalline silicon is formed on the obtained gate oxide film using the CVD method, and as shown in FIGS. 3A and 3B, S: source, D ni dorain, G : Forming a gate semiconductor device. That is, as particularly shown in FIG. 3B, a thick oxide layer 5a is formed at the outer peripheral edge of the recrystallized layer, so that the lack of gate withstand voltage that has conventionally occurred can be solved, and the recrystallized silicon layer 3 and the gate metal layer 6 are connected to the gate. They are effectively separated via the insulating layer 5.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to form a thick gate insulating film (SiOz) on the peripheral edge of recrystallized silicon, so it is possible to make an SOI/MO5FET with a high gate breakdown voltage, and it is possible to stack devices in multiple layers. 3D S0
1/LSI process and has general versatility.

[Brief explanation of the drawing]

1A, 1B, 2, 3A, and 3B are diagrams for explaining an embodiment of the present invention, and FIG. 4 is a diagram for explaining a conventional example. 1... Silicon substrate, 2... Insulating layer, 3...
silicon layer, 4... resist pattern, 5...
...Gate insulating layer, 6...Gate metal layer, 7.
...Silicon layer. 1 1 1 1B" Fig. 1B Fig. 2 Fig. 3 Pa-silicon layer 4... Renost pattern 5... Dirt insulating layer

Claims (1)

[Claims] 1. Form an insulating layer (2) on a silicon substrate (1), form a silicon layer (3) on the insulating layer (2), and form a gate insulating layer (5) on the silicon layer (3). After forming the silicon layer (3), a peripheral edge portion of the silicon layer (3) is formed on the silicon layer (3). A resist pattern (4) is formed so as to be exposed, and ions are implanted into the silicon layer from above the silicon layer using the resist as a mask. After removing the resist, the surface of the silicon layer (3) is A method for manufacturing a semiconductor device, characterized in that the gate insulating layer is formed by oxidation.