JPS6066524A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce considerably the cost by using an inexpensive D/A converter consisting of bits, whose number is a half of the number of objective output bits, in a successive comparison-type A/D converter. CONSTITUTION:First, switches (a) and (b) are closed to perform the successive comparison operation, and an 8-bit output is stored in a latch circuit 18. Next, the output of a D/A converter 13 is held as it is, and switches (a) and (b) are opened, and a switch (c) is closed, and the D/A output value is stored in a sample holding circuit 15. The switch (c) is opened and switches (d) and (e) are closed to perform the second successive comparison operation. At this time, a differential amplifier 16 operates a difference between an analog input value and the D/A output value attained at the end of the first conversion, and this difference is multiplied by 256 in an amplifier 17, and this multiplication output value is inputted to a comparator 11 for the second operation. This data of the second successive comparison is stored in a latch circuit 19 of lower bits. After the second conversion is terminated, contents of two latch circuits 18 and 19 are read out to obtain 16-bit digital data.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial field of application (4) Used in the field of analog/digital conversion.

The present invention relates to improvements in successive approximation type A/D converters.

←) Prior Art A successive approximation type A/D converter is widely used as a high-speed A/D converter, and a typical example thereof is configured as shown in FIG. In the figure, 1 is an i4 comparator, 12 is a successive approximation register, 13 is a D/A converter, and 18 is a latch circuit. Note that the illustration of the timing clock generator is omitted.

However, if you are trying to manufacture a high-speed, high-resolution successive approximation type A/D converter following this conventional example, you will need a high-speed, high-precision D/A converter with a large number of bits to scan. Therefore, if you try to manufacture a J-order comparison type A/D 7A' converter with a 16-bit resolution, for example, the price will rise rapidly just by combining the /A converter. A 16-bit D/A converter is required,
Prices go up.

(c) Purpose The purpose of tree starting point 1 is to use a high-speed, high-resolution successive approximation type A converter that uses a small number of bits to output a digital value with at least twice the number of bits. /D converter.

The purpose of the above is to
A subtractor that shifts the register output value to one latch circuit upon completion of conversion and outputs the difference value between the D/A converter output value and the analog input value at that time, and converts the difference value to the maximum value depending on the number of bits of the register. By adding a multiplier that multiplies by This is accomplished by switching and shifting to a latch circuit.

(e) Examples A preferred embodiment of the invention is described with respect to FIG.

Here, 11 is a comparator, 12 is a successive approximation register, 13 is an 8-bit D/A converter, and 1 is a successive approximation register.
4 Habatshua, 15 Hazamble hold circuit, l6 (
ri differential amplifier, 17fl amplification factor or 2 (=256) amplifier, 18 719 /i each 8-bit latch circuit. Dimensions a''-e indicate switches.

In this operation, first, switches a and b are closed to perform a successive approximation operation, and an 18-bit output is stored in the latch circuit 18. Next, the output of the D/A converter 13 is set to 1, switches a and b are opened, switch C is closed, and the D/A rB power value is stored in the sample and hold circuit 15. Sample and hold circuit 15 [When the D/A output value is accurately stored by the clock, switch C is opened, switches d and e are closed, and the second successive approximation operation is performed.

At this time, the differential amplifier 16 takes the difference between the analog input value and the D/A output value obtained at the end of the first conversion, multiplies this by 256 in the amplifier 17, and uses this multiplied output value for the second operation. Input comparator ll'r. The data of this second successive approximation is stored in the launch circuit 19 of the lower bits. After the second conversion is completed, the first path 18 and 19 of the two latches are read out to obtain 16-bit digital data. In other words, with the 8-bit D/A converter 13, 2
This means that an output of 16 bits was obtained. In addition, in this illustrated example, the clock generator for timing operation of the switches a"'-e and the timing pulse for the latch circuit that takes in the output of the comparison register]2 upon completion of conversion is omitted from the illustration. The conversion time U and the number of bits of the digital output code are decisive, so switch a”
The operation timing of e can be easily determined.

The configuration of the switch is not limited to the illustrated embodiment.

For example, the switches b and cirj may be configured with one three-way switch.

According to Mizumoto IJI, when designing a 20-bit A/D converter, a 10-bit D/A converter can be used, and the amplification factor of the amplifier should be 210K.

k) #I+ Month 1 Mizumoto EIIIU, which has half the number of target output bits, that is, a cheaper /A converter can be used, which has the effect of greatly reducing the overall cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example, and Fig. 2 is a block diagram showing one embodiment of the invention. 11 is a comparator, 12 is a successive approximation register, 13 is a D/A converter, and 16 is a differential amplifier. , 17 is an amplifier, 18
and 19 Halach circuit.

Claims (2)

[Claims] (1) In a successive approximation type D/A converter that combines a comparator, a successive approximation register, and a D/A converter, upon completion of conversion, the register output value is transferred to the latch circuit, and the D/A converter outputs at that time. A subtracter that outputs the difference value between the value and the analog input value, a multiplier that multiplies the difference value by the maximum value according to the number of bits in the register, and a switch that switches and inputs this multiplication output value to the analog input value and to the comparator. Add , start the conversion repeatedly, and change 1! li! At the end of l, similarly switch and shift the register output value to the other lower bit launch 10 circuit,
An A/D converter characterized by being able to obtain high resolution data. (2) The analog input terminals of the D/A converter, differential amplifier, amplifier, switch, and comparator are connected in series, and at least two latch circuits are movably connected to the output of the register. The A/D converter according to claim 1, characterized by: