JPH0479614A - A/d converter circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of a digital signal by further A/D-converting an inputted analog signal after the signals are once A/D-converted, and amplifying the error between D/A-converted analog signals and the inputted analog signals. CONSTITUTION:When analog signals are converted into digital signals with 12-bit accuracy by using a 4-bit A/D converter 6 and D/A converter 8, the analog signals are A/D-converted and the data of the higher-rank 4 bits of the 12 bits are obtained in the 1st step. When the difference between the output of the A/D converter 6 and the original analog signals is taken after the output is D/A-converted, a 4-bit A/D conversion error is obtained. When the 4-bit A/D conversion is again made after the error is multiplied by 2<4> =l6, data of the intermediate-rank 4 bits of the 12 bits are obtained. By further multiplying the obtained error by 16, the lower-rank 4 bits are similarly obtained. When the higher-, intermediate-, and lower-rank data are added to each other through a shift register 11, digital data with 12-bit accuracy can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an AD converter that uses an n-bit AD converter to create a digital signal with m-bit (m > n) precision.
Regarding converter circuits.

[Prior Art] In an AD converter circuit, when output data with m (m is a positive integer) bit precision is desired, an m-bit AD converter is usually required. Alternatively, a plurality of AD converters with less than m bits are prepared so that the sum of these bit numbers becomes m bits.

[Problems to be Solved by the Invention] In the conventional AD comparator circuit described above, in order to improve its bit precision, it is necessary to
It was necessary to prepare a D converter or combine multiple AD converters. In the former case, the AD converter itself is expensive, and in the latter case, multiple AD converters are required, which also makes it expensive. Further, it is also not possible to programmably change the bit precision of the AD converter circuit.

An object of the present invention is to provide an inexpensive AD converter circuit in which the overall bit precision of the AD converter circuit can be made higher than the bit precision of a single AD converter used, and in which the bit precision can be changed by a programmer. It is.

[Means for Solving the Problems] In order to achieve the above object, an AD converter circuit according to the present invention has the following features.

That is, the present invention uses an n (n is any positive integer) bit AD converter to convert m (m is an integer multiple of n)
In an AD converter circuit that creates a digital signal with bit precision, the first step selects an input analog signal, and the second and subsequent steps include an analog switch that selects an error signal, and a signal from the analog switch that is held. an n-bit AD converter that converts the output signal of the sample and hold circuit into a digital signal; a first latch circuit that latches the output signal of the AD converter; and an output signal of the first latch circuit. n towards the least significant bit
a shift register that shifts by X (number of steps - 1) bits, an n-bit DA converter that converts the output signal of the first latch circuit into an analog signal, and an output signal of the DA converter and an output of the sample hold circuit. an amplifier circuit that amplifies the difference from the signal by 2n times and supplies this as the error signal to the analog switch; and an amplifier circuit that adds together the output signals of the shift register at each step to output a digital signal with m-bit precision. The present invention is characterized in that it has an adding section that does.

[Function] The present invention focuses on the error between the output digital signal and the input analog signal when AD converted, and improves the accuracy of the digital signal by amplifying this error and then performing AD conversion.

An example will be explained in which a 4-bit AD converter and a 4-bit DA converter are used to convert an input analog signal into a 12-bit precision digital signal. In the first step, the input analog signal is AD converted and 12
Data of the upper 4 bits can be obtained. At this time, the digital output of the AD converter is
If we take the difference from the original input analog signal after conversion, we get 4.
The error when AD converting bits is obtained.

If this error is multiplied by 2' = 16 and AD converted again using a 4-bit AD converter, the middle 4 of the 12 bits
Bit data can be obtained.

If the error at this time is further amplified 16 times and AD converted, data of the lower 4 bits of the 12 bits can be obtained. By adding these 4 bits of data for each of the upper, middle, and lower bits, digital data with 12-bit precision can be obtained.

[Example] Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This AD converter circuit is a circuit that uses a 4-bit AD converter 6 and a 4-bit DA converter 8 to output a digital signal with 12-bit precision from an output terminal 15.

An analog signal to be converted into a digital signal is input to an input terminal 1. Analog switch 2 connected to input terminal 1
turns on/off the input signal from the input terminal 1 based on the control signal a. The sample and hold circuit 4 samples and holds the signal from the analog switch 2 and the signal from another analog switch 3 based on the control signal g. In this case, only the signal from one of the analog switches 2.3 arrives at the sample and hold circuit 4. The analog switch 3 controls the amplifier circuit 1, which will be described later, based on the control signal.
This is to turn off the error signal from 0N-OFF.

The 4-bit AD converter 6 is a sample hold circuit 4.
converts the output signal into a digital signal with 4-bit precision.

The first latch circuit 7 latches the output signal of the AD converter 6.

The DA converter 8 converts the 4-bit output of the first latch circuit 7 into an analog signal. The operational amplifier 9 outputs the error between the output of the sample hold circuit 4 and the output of the DA converter 8, and the amplifier circuit 1o amplifies this error by 24=16 times and outputs it. The amplified error signal is sent to analog switch 3.

The 12-bit shift register 11 has a function of shifting the output of the first latch circuit 7 by a predetermined number of bits toward the least significant bit (ie, shifting to the right) based on the control signal d. In this invention, the 4-bit AD converter 6 is operated three times to convert analog data into ADi with 12-bit precision, and the processing stages of the AD converter corresponding to each operation are divided into the first step and the second step. They are called the second step and third step. Based on the control signal d input to the shift register 11, in the first step,
The shift register 11 stores the 4-bit output from the first latch circuit 7 in order from the most significant bit up to the 4th bit, and outputs the lower bits with the lower bits set to zero. In the second step, the shift register 11 stores the 4-bit output of the first latch circuit 7 in the 5th to 8th bits counting from the most significant bit, sets the other bits to zero, and outputs them. In the third step, shift register 1
1 stores the 4-bit output of the first latch circuit 7 in the 9th to 12th bits counting from the third most significant bit, and outputs the higher bits with the higher bits set to zero.

The selector 12 selects the output of the shift register 11 and the output of the adder circuit 14, which will be described later, based on the control signal e.

That is, in the first step, the output of the shift register 11 is selected, and in the second step, the output of the adder circuit 14 is selected.

The second latch circuit 13 latches the output of the selector 12 and transfers this output to the adder circuit 1 at the timing according to the control signal f.
Send to 4.

The adder circuit 14 performs logical addition of the output of the second latch circuit 13 and the output of the shift register 11 in the second and third steps based on the control signal i.

The gate circuit 18 outputs the output of the adder circuit 14 to the output terminal 15 only in the third step based on the control signal j.

The control circuit 17 operates the AD converter circuit using control signals a s b SCs d −, e x f x
This is a circuit that generates g % l, J. A command to make the digital output signal accurate to 12 bits is input to the control terminal 16.

Next, the operation of this AD converter circuit will be explained.

First, the operation up to the shift register 11 will be explained.

In the first step, this AD converter circuit samples and holds an input analog signal in a sample and hold circuit 4, converts it into a digital signal in a 4-bit AD converter 6, and latches it in a first latch circuit 7. The digital output of the latch circuit 7 is converted back to an analog signal by a DA converter 8, and the error with respect to the input analog signal is determined.

After this error is amplified 16 times, it is returned to the sample hold circuit 4 via the analog switch 3.

In the second step, this first error signal is AD converted in the same manner as in the first step, and further DA converted, and the error between the analog output and the first error signal is amplified by 16 times, and a second error signal is generated. get. This second error signal is returned to the sample and hold circuit 4 again.

In the third step, this second error signal is AD converted,
The signal is sent to the first latch circuit 7. A new error signal is not determined in this third step.

Through the above operations, each digital output is latched in the first latch circuit 7 in three steps.

That is, in the first step, of the 12-bit digital signal to be obtained, the first to fourth bits counting from the most significant bit (hereinafter referred to as the upper bit group) are selected.

) data (hereinafter referred to as upper data) will be latched. In the second step, of the 12-bit digital signal to be obtained, data from the 5th bit to the 8th bit counting from the most significant bit (hereinafter referred to as the intermediate bit group) (hereinafter referred to as intermediate data). will be latched. In the third step, of the 12-bit digital signal to be obtained, data from the 9th bit to the 12th bit (hereinafter referred to as the lower bit group) counting from the most significant bit (hereinafter referred to as the lower order data) is obtained. It will latch.

Next, the operations after the shift register 11 will be explained. The shift register 11 has a 12-bit configuration as shown in Figure 2, and in this figure, data is stored in the hatched bits, and zeros are stored in all blank bits. There is. In the first step, the first latch circuit 7 outputs "-" data, so this high-order data is stored in the 1-" bit group as shown in FIG. 2(a), and the other bits are set to zero. do. In the second step, since middle-order data is output from the first latch circuit 7, this middle-order data is shifted to the right by 4 bits and stored in the middle-order bit group as shown in FIG. 2(b). Set other bits to zero. In the third step, the lower data is output from the first latch circuit 7, so this lower data is shifted to the right by 8 bits and stored in the lower bit group as shown in FIG. 2(C), and the other bits are to zero.

The function of the selector 12 to the adder circuit 14 is to add high-order data, middle-order data, and low-order data between the first step and the third step to create digital data with 12-bit precision.

In the first step, the output of the shift register 11 (including only upper data) passes through the selector 12 and is latched by the second latch circuit 13. In the second step, the output of the shift register 11 (containing only intermediate data) and the output of the second latch circuit 13 (containing only high-order data) are added in the adder circuit 14. This addition circuit 14
The output (including upper and middle data) is selector 1
2 and latched by the second latch circuit 13. In the third step, the output of the shift register 11 (including only lower-order data) and the output of the second latch circuit 13 (including upper-order data and middle-order data) are added in the adder circuit 14. The output of the adder circuit 14 (including upper data, middle data, and lower data) is output to the output terminal 15 via the gate circuit 18. This means that the input analog signal is converted to digital data with 12-bit precision.

In this embodiment, the selector 12, second latch circuit 13, adder circuit 14, and gate circuit 18 constitute an adder in the present invention.

Here, the reason why the error signal is multiplied by 16 in the amplifier circuit 10 will be explained using FIG. The vertical axis in FIG. 3 represents voltage, and the horizontal axis represents time.

The operating range of the AD converter 6 is from V+mln to Vma
x, and the resolution of the AD converter 6 is S. Since the AD converter 6 has a precision of 4 bits, the resolution S is 1/16 of the operating range (Vg+ax-Vain).

The sampling time in the sample hold circuit 4 is T
s, the output value of the sample and hold circuit 4 when input analog signal A is sampled and held is vl, and when this is converted to a digital signal by the AD converter 6 and then converted to an analog signal by the DA converter 8, D
The output voltage of A converter 8 becomes V2. That is, △
An error of V-V2-Vl occurs. 4-bit precision AD
In this way, when performing conversion, an error of at most S inevitably occurs. In the present invention, accuracy is increased by enlarging this error and further performing AD conversion. That is, in order to accurately examine the proportion of this error Δ■ in the resolution S, ΔV is set to 24=24 in the amplifier circuit 1.0.
It's multiplied by 16.

Multiplying ΔV by 16 increases the resolution S to the operating range (Vma
x - Vmln ). Then, in the second step, the error ΔV multiplied by 16
is AD converted in the same manner as in the first step, and the 4-bit digital output is used as intermediate data in the 12-bit data. Furthermore, the error signal obtained in the second step is also multiplied by 16, and then AD is added in the third step.
The 4-bit digital output is converted into lower-order data in the 12-bit data.

Incidentally, in the description of the second series, the case where a 4-bit AD converter was used was explained, but when an n-bit AD converter is used, the error ΔV is multiplied by 2° in the amplifier circuit IO.

In the AD converter circuit of this embodiment, the precision of the digital output signal can be changed in units of 4 bits. For example, to obtain a digital output signal with 8-bit precision, the AD conversion step may be repeated twice, and to obtain a 16-bit precision digital output signal, the AD conversion step may be repeated four times. A command regarding the number of repetitions of a step only needs to be input from the control terminal 16 of the control circuit 17.

[Effects of the Invention] As explained above, in the present invention, a digital output signal that has been AD converted with n-bit precision is DA-converted, and then the error with the original analog input signal is calculated. After multiplying the error by 2 degrees, AD conversion is further performed using the same AD converter, and this process is repeated. Then, the digital data obtained in each step is subjected to a predetermined shift and then added together. This results in
Using a single AD converter with n-bit precision, digital data with bit precision that is an integer multiple of n can be obtained.

Furthermore, by increasing or decreasing the number of steps, the bit accuracy can be programmably increased or decreased.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the invention, FIG. 2 is a data storage diagram of a shift register, and FIG. 3 is a graph explaining the invention in detail. 2.3... Analog switch 4... Sample hold circuit 6... AD converter 7... First latch circuit 8... DA converter 10... Amplifier circuit 11... Shift register 12...・Selector 13...Second latch circuit 14...Addition circuit

Claims (1)

[Claims] In an AD converter circuit that uses an n (n is any positive integer) bit AD converter to create a digital signal with m (m is an integer multiple of n) bit precision, in a first step: An analog switch that selects an input analog signal and selects an error signal in the second and subsequent steps, a sample hold circuit that holds the signal from the analog switch, and converts the output signal of the sample hold circuit into a digital signal. an n-bit AD converter, a latch circuit that latches the output signal of the AD converter, and an n×(
Number of steps - 1) a shift register that shifts by bits, and converts the output signal of the latch circuit into an analog signal;
an n-bit DA converter; an amplifier circuit that amplifies the difference between the output signal of the DA converter and the output signal of the sample and hold circuit by 2^n times and supplies this as the error signal to the analog switch; An AD converter circuit comprising: an adder section that adds the output signals of the shift registers in each step to output a digital signal with m-bit precision.