JPS6058644A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the titled device of small parasitic capacitance by a method wherein a contact electrode and a gate electrode are composed of the structure of lamination of a polycrystalline Si layer containing an impurity in the lower layer and a metallic film or a metal silicide layer in the upper layer, and an inner wiring electrode is composed of the structure of lamination of a polycrystalline Si layer containing no impurity in the lower layer and a metallic layer of the same condition in the upper layer. CONSTITUTION:A thick field oxide film 2 for element isolation is formed in the periphery of a P type Si substrate 1, and a thin gate oxide film 7 is adhered to the substrate surface surrounded by that film. Next, the gate electrode 5 is provided at the center of the surface of the film 7. At this time, the electrode 5 is composed of the structure of lamination of the As-doped polycrystalline Si layer 41 of the lower layer and the TaSi2 layer 3 of the upper layer. Besides, the contact electrode 12 mounted on N type source and drain regions 8 and 9 provided on both sides of the layers is put in the same structure, and the inner wiring electrode 6 positioned above the film 2 and intersecting rectangularly to those is composed of a non-doped polycrystalline Si layer 42 of the lower layer and the same TaSi2 layer of the upper layer.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device with improved wiring technology.

[Technical background of the invention and its problems]

As is well known, in semiconductor devices such as MO8 type transistors, At and the like are used as materials for contact electrodes connected to the source and drain regions on the substrate surface, internal wiring electrodes provided on the substrate through element isolation regions, etc. A laminated structure in which the lower layer is made of polycrystalline silicon doped with impurities and the upper layer is made of a metal such as At or metal silicide is used. The reason why polycrystalline silicon is used for the lower layer is that if a metal such as At comes into direct contact with the substrate, it will stick to the substrate during heat treatment.

However, according to the conventional MOS i) runnostar, since polycrystalline silicon doped with impurities is used as the material for the lower layer of the internal wiring electrode, parasitic capacitance between the electrode and the substrate is generated via the element isolation region, etc. It has the disadvantage that it becomes large. However, reducing the parasitic capacitance has become a major technical issue, as well as reducing the resistance of wiring electrodes, in order to improve the operating speed as ICs have become highly integrated in recent years.

For this reason, it is conceivable to increase the thickness of the insulating film between the layers as a means of reducing parasitic capacitance, but in such a case, there is a problem with the processing accuracy as seen in the case of contact hole processing, so it is difficult to insulate There is a limit to how thick the film can be.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to reduce the resistance of contact electrodes and dirt electrodes to increase speed, as well as reduce the parasitic capacitance of internal wiring electrodes provided on the substrate via an insulating film. It is an object of the present invention to provide a semiconductor device that can be degraded.

[Summary of the invention]

In the present invention, the contact electrode and the gate electrode have a stacked structure in which the lower layer is a polycrystalline silicon layer containing impurities and the upper layer is a metal film or metal silicide layer, and the internal wiring electrode is formed of a polycrystalline silicon layer containing no impurities as the lower layer. The main idea is to achieve the above-mentioned object by forming a laminated structure in which the upper layer is a metal layer or a metal silicide layer.

[Embodiments of the invention]

Hereinafter, an MO8 type transistor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3, along with a manufacturing method.

First, a field oxide film 2 as an element isolation region and a thermal oxide film (not shown) were sequentially formed on a predetermined surface of a P-type St substrate 1 as a semiconductor substrate by a conventional method. Subsequently, after forming a polycrystalline silicon layer (not shown) with a film thickness of 2000X on the entire surface, a 7-tone resist film was coated on the entire surface, dried, and photolithography was performed to form a photolithography layer corresponding to the area where the PC electrode was to be formed. The resist film was selectively removed to form a resist pattern (not shown). Next, using this resist pattern as a mask, arsenic was dosed onto the polycrystalline silicon layer at an accelerating voltage of 40 keV.

Ion implantation was carried out under conditions of an amount of 3×1015/1yn2. Subsequently, after removing the resist pattern, a 3000× thick TaSi layer (not shown) was formed on the entire surface. Furthermore, a resist pattern of a predetermined shape was formed on this TaSi2 layer, and after death, the TaSi2 layer and the polycrystalline silicon layer were sequentially etched away using the A turn as a mask, and the Ta512 pattern 3 and the polycrystalline silicon doped with arsenic were removed. A dirt electrode 5 consisting of a pattern 41, and a first electrode consisting of a TaSi2 pattern 3 connected to the dirt electrode 5 and a polycrystalline silicon pattern 42 which does not contain arsenic.
An internal wiring electrode 6 was formed. Thereafter, the thermal oxide film was selectively removed using the dirt electrode 5 as a mask to form a dirt insulating film 7.

Next, using the dirt electrode 5 etc. as a mask, the substrate IK
N type impurities were ion-implanted to form N type source and drain regions 8 and 9. Subsequently, a thermal oxidation treatment is performed to form an oxide film (not shown) on the substrate 1 to a thickness of 50 mm over the entire surface.
After depositing the oo1ocvpsio2 film 10, a C layer corresponding to part of the source and drain regions 8.9 is formed by PEP method.
VD S 102 ilo is opened and contact hole 11. llf was diagnosed. Next, the entire surface is coated with a thickness of 1000X.
After depositing the polycrystalline silicon layer, arsenic ions were implanted into the portion of the polycrystalline silicon layer connected to the source region 8 in the same manner as described above. Furthermore, after depositing an At layer with a thickness of 8000× on the entire surface, this At layer and the polycrystalline silicon layer are properly turned to form a contact electrode 2 which is connected to the source region 8 through the contact hole 1, and this. A second internal wiring electrode 13 connected to the contact electrode 12 was formed.

Here, the contact electrode 12 is doped with arsenic and has a 7'c multi-connected SL+silicon pattern 141 and an 11 pattern 15.
In other words, the internal wiring electrode 13 was made up of a polycrystalline silicon pattern 142 not doped with arsenic and an At oxide turn 15, and an MO8 type transistor was manufactured (as shown in FIGS. 1 to 3).

As shown in FIGS. 1 to 3, the MO8 type transistor according to the present invention has an N+ type source and drain region 8.9 provided on the surface of a P type Si substrate 1, and a source and drain region 8.9 provided on the substrate 1. A polycrystalline silicon pattern 15 whose lower layer is doped with arsenic is connected to a part of the polycrystalline silicon pattern 15. A contact electrode 12 having a two-layer structure consisting of an upper layer Atz# turn 15 is provided,
On the same substrate 1, the lower layer is made of polycrystalline silicon which does not contain arsenic through the dirt insulating film 7, and the upper layer is made of TaS with a turn 51.
A dirt electrode 6 with a two-layer structure consisting of two patterns 3 is provided, and a field oxide film 2 and a CVD5i0 are formed on the same substrate 1.
The internal wiring electrodes 6 and 13 have a two-layer structure in which the lower layer is a polycrystalline silicon pattern 142 not doped with arsenic and the upper layer is an At pattern 15 via two films IQ.

According to the present invention, the electrodes 5.
By lowering the resistance of 12, it is possible to achieve higher operating speed of the element. Furthermore, a polycrystalline silicon pattern 42 which is not doped with arsenic is formed below the first and second internal wiring electrodes 6 and 130, respectively.
142, the patterns 42.14. Since it can be used as a dielectric or an insulator as it is, the parasitic capacitance can be reduced while keeping its specific resistance similar to that of the prior art.

In the above embodiment, the material of the upper layer of the contact electrode and the dirt electrode is Tas i 9, but it may be a negative metal silicide or a metal such as At.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device in which the resistance of contact electrodes and dirt electrodes is reduced to achieve high-speed operation, and the parasitic capacitance of internal wiring electrodes can be reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view of an MO8 type transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line X-X in FIG. 1, and FIG. 3 is a cross-sectional view taken along line Y-Y in FIG. 1. FIG. 1... P-type St substrate (semiconductor substrate), 2... Field oxide film (element isolation region), 3... TaSi2
/' turn, 41+141...Polycrystalline silicon pattern doped with arsenic, 42r142...Polycrystalline silicon pattern not doped with arsenic, 5...Dart electrode, 6.13...Internal wiring electrode, 7...・Dirt+10 insulating film, 8...N-type source region, 9...N-type drain region, 10...CVD5I021[,11・''
Contact hole, 12... Contact electrode, 15.
...At Noreen.

Claims (1)

[Claims] a semiconductor substrate having a diffusion layer on its surface; a contact electrode provided on the substrate to be connected to the diffusion layer;
In a semiconductor device comprising a dirt insulating film, a dirt electrode and an internal wiring electrode provided on the same substrate through an element isolation region, the contact electrode and the dirt electrode are formed of a polycrystalline silicon layer containing impurities as a lower layer and as an upper layer. has a laminated structure consisting of a metal layer or a metal silicide layer, and the internal wiring electrode has a laminated structure in which the lower layer is a polycrystalline 7-lion layer containing no impurities and the upper layer is a metal layer or a metal silicide layer. semiconductor devices.